/* =========================================================================
 * The Synopsys DWC ETHER QOS Software Driver and documentation (hereinafter
 * "Software") is an unsupported proprietary work of Synopsys, Inc. unless
 * otherwise expressly agreed to in writing between Synopsys and you.
 *
 * The Software IS NOT an item of Licensed Software or Licensed Product under
 * any End User Software License Agreement or Agreement for Licensed Product
 * with Synopsys or any supplement thereto.  Permission is hereby granted,
 * free of charge, to any person obtaining a copy of this software annotated
 * with this license and the Software, to deal in the Software without
 * restriction, including without limitation the rights to use, copy, modify,
 * merge, publish, distribute, sublicense, and/or sell copies of the Software,
 * and to permit persons to whom the Software is furnished to do so, subject
 * to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGE.
 * =========================================================================
 */
/*
 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */
#ifndef __EQOS__REGACC__H__

#define __EQOS__REGACC__H__

#define MAKE_MASK_32(e, s) (((e)-(s)) == 31 ?\
	0xffffffffUL : ((1UL<<((e)-(s)+1))-1))

#define MAKE_MASK_64(e, s) (((e)-(s)) == 63 ?\
	0xffffffffffffffffULL : ((1ULL<<((e)-(s)+1))-1))

#define GET_BITS(e, s, reg, data) \
	(data = ((e)-(s) > 31) ?\
	(((reg)>>(s))&MAKE_MASK_64(e, s)) :\
	(((reg)>>(s))&MAKE_MASK_32(e, s)))

#define SET_BITS(e, s, reg, val) do { \
	if ((e)-(s) > 31) { \
	reg = ((((val)<<(s))&(MAKE_MASK_64((e), (s))<<(s)))\
	|((reg)&(~(MAKE_MASK_64((e), (s))<<(s))))); \
	} \
	else { \
	reg = ((((val)<<(s))&(MAKE_MASK_32((e), (s))<<(s)))\
	|((reg)&(~(MAKE_MASK_32((e), (s))<<(s))))); \
	} \
} while (0)

/* virtual_registers Low Bit Macro Name's */
#define RX_CONTEXT_DESC_RDES3_OWN_LBIT_POS  0x1f
#define RX_CONTEXT_DESC_RDES3_CTXT_LBIT_POS  0x1e
#define RX_CONTEXT_DESC_RDES2_RESERVED_BITS_LBIT_POS  0
#define RX_CONTEXT_DESC_RDES1_RTSH_LBIT_POS  0
#define RX_CONTEXT_DESC_RDES0_RTSL_LBIT_POS  0
#define TX_CONTEXT_DESC_TDES3_OWN_LBIT_POS  0x1f
#define TX_CONTEXT_DESC_TDES3_CTXT_LBIT_POS  0x1e
#define TX_CONTEXT_DESC_TDES3_OSTC_LBIT_POS  0x1b
#define TX_CONTEXT_DESC_TDES3_TCMSSV_LBIT_POS  0x1a
#define TX_CONTEXT_DESC_TDES3_CDX_LBIT_POS  0x17
#define TX_CONTEXT_DESC_TDES3_IVTIR_LBIT_POS  0x12
#define TX_CONTEXT_DESC_TDES3_SVLTV_LBIT_POS  0x11
#define TX_CONTEXT_DESC_TDES3_IVLTV_LBIT_POS  0x11
#define TX_CONTEXT_DESC_TDES3_VLTV_LBIT_POS  0x10
#define TX_CONTEXT_DESC_TDES2_IVT_LBIT_POS  0x10
#define TX_CONTEXT_DESC_TDES3_VT_LBIT_POS  0
#define TX_CONTEXT_DESC_TDES2_SVT_LBIT_POS  0xf
#define TX_CONTEXT_DESC_TDES2_MSS_LBIT_POS  0
#define TX_CONTEXT_DESC_TDES1_NDAP_LBIT_POS  0
#define TX_CONTEXT_DESC_TDES0_TTSL_LBIT_POS  0
#define RX_NORMAL_DESC_RDES3_OWN_LBIT_POS  0x1f
#define RX_NORMAL_DESC_RDES3_CTXT_LBIT_POS  0x1e
#define RX_NORMAL_DESC_RDES3_FD_LBIT_POS  0x1d
#define RX_NORMAL_DESC_RDES3_LD_LBIT_POS  0x1c
#define RX_NORMAL_DESC_RDES3_RS2V_LBIT_POS  0x1b
#define RX_NORMAL_DESC_RDES3_RS1V_LBIT_POS  0x1a
#define RX_NORMAL_DESC_RDES3_RS0V_LBIT_POS  0x19
#define RX_NORMAL_DESC_RDES3_CE_LBIT_POS  0x18
#define RX_NORMAL_DESC_RDES3_GP_LBIT_POS  0x17
#define RX_NORMAL_DESC_RDES3_RWT_LBIT_POS  0x16
#define RX_NORMAL_DESC_RDES3_OE_LBIT_POS  0x15
#define RX_NORMAL_DESC_RDES3_RE_LBIT_POS  0x14
#define RX_NORMAL_DESC_RDES3_DE_LBIT_POS  0x13
#define RX_NORMAL_DESC_RDES3_LT_LBIT_POS  0x10
#define RX_NORMAL_DESC_RDES3_ES_LBIT_POS  0xf
#define RX_NORMAL_DESC_RDES3_FL_LBIT_POS  0
#define RX_NORMAL_DESC_RDES2_B2AP_NDA_LBIT_POS  0
#define RX_NORMAL_DESC_RDES1_COP_LBIT_POS  0x10
#define RX_NORMAL_DESC_RDES1_TD_LBIT_POS  0xf
#define RX_NORMAL_DESC_RDES1_TSA_LBIT_POS  0xe
#define RX_NORMAL_DESC_RDES1_PV_LBIT_POS  0xd
#define RX_NORMAL_DESC_RDES1_PFT_LBIT_POS  0xc
#define RX_NORMAL_DESC_RDES1_PMT_LBIT_POS  0x8
#define RX_NORMAL_DESC_RDES1_IPPE_LBIT_POS  0x7
#define RX_NORMAL_DESC_RDES1_IPCB_LBIT_POS  0x6
#define RX_NORMAL_DESC_RDES1_IPV6_LBIT_POS  0x5
#define RX_NORMAL_DESC_RDES1_IPV4_LBIT_POS  0x4
#define RX_NORMAL_DESC_RDES1_IPHE_LBIT_POS  0x3
#define RX_NORMAL_DESC_RDES1_PT_LBIT_POS  0
#define RX_NORMAL_DESC_RDES0_HDR_B1AP_LBIT_POS  0
#define TX_NORMAL_DESC_TDES3_OWN_LBIT_POS  0x1f
#define TX_NORMAL_DESC_TDES3_CTXT_LBIT_POS  0x1e
#define TX_NORMAL_DESC_TDES3_FD_LBIT_POS  0x1d
#define TX_NORMAL_DESC_TDES3_LD_LBIT_POS  0x1c
#define TX_NORMAL_DESC_TDES3_CPC_LBIT_POS  0x1a
#define TX_NORMAL_DESC_TDES3_SAIC_LBIT_POS  0x17
#define TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_LBIT_POS  0x13
#define TX_NORMAL_DESC_TDES3_TSE_LBIT_POS  0x12
#define TX_NORMAL_DESC_TDES3_CIC_LBIT_POS  0x10
#define TX_NORMAL_DESC_TDES3_TIPLH_LBIT_POS  0xf
#define TX_NORMAL_DESC_TDES3_FL_LBIT_POS  0
#define TX_NORMAL_DESC_TDES2_IC_LBIT_POS  0x1f
#define TX_NORMAL_DESC_TDES2_TTSE_LBIT_POS  0x1e
#define TX_NORMAL_DESC_TDES2_B2L_LBIT_POS  0x10
#define TX_NORMAL_DESC_TDES2_VTIR_LBIT_POS  0xe
#define TX_NORMAL_DESC_TDES2_HL_B1L_LBIT_POS  0
#define TX_NORMAL_DESC_TDES1_B2A_NDA_LBIT_POS  0
#define TX_NORMAL_DESC_TDES0_B1A_HAP_LBIT_POS  0
#define TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_LBIT_POS  0x4
#define TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_LBIT_POS  0x3
#define TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_LBIT_POS  0x2
#define TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_LBIT_POS  0x1
#define TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_LBIT_POS  0
#define RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_LBIT_POS  0x5
#define RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_LBIT_POS  0x4
#define RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_LBIT_POS  0x3
#define RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_LBIT_POS  0x2
#define RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_LBIT_POS  0x1
#define RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_LBIT_POS  0
#define RX_PKT_FEATURES_VLAN_TAG_SVT_LBIT_POS  0x10
#define RX_PKT_FEATURES_VLAN_TAG_VT_LBIT_POS  0
#define RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_LBIT_POS  0x1
#define RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_LBIT_POS  0
#define TX_PKT_FEATURES_TCP_HDR_LEN_LEN_LBIT_POS  0
#define TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_LBIT_POS  0x1
#define TX_PKT_FEATURES_PKT_TYPE_IP_PKT_LBIT_POS  0
#define TX_PKT_FEATURES_TUCSE_TCPCSE_LBIT_POS  0
#define TX_PKT_FEATURES_TUCSO_TCPCSO_LBIT_POS  0
#define TX_PKT_FEATURES_TUCSS_TCPCSS_LBIT_POS  0
#define TX_PKT_FEATURES_IPCSE_IPCSE_LBIT_POS  0
#define TX_PKT_FEATURES_IPCSO_IPCSO_LBIT_POS  0
#define TX_PKT_FEATURES_IPCSS_IPCSS_LBIT_POS  0
#define TX_PKT_FEATURES_PAY_LEN_PAY_LEN_LBIT_POS  0
#define TX_PKT_FEATURES_HDR_LEN_HDR_LEN_LBIT_POS  0
#define TX_PKT_FEATURES_MSS_MSS_LBIT_POS  0
#define TX_PKT_FEATURES_VLAN_TAG_SVT_LBIT_POS  0x10
#define TX_PKT_FEATURES_VLAN_TAG_VT_LBIT_POS  0
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_LBIT_POS  0x3
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_LBIT_POS  0x2
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_LBIT_POS  0x1
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_LBIT_POS  0

/* virtual_registers High Bit Macro Name's */
#define RX_CONTEXT_DESC_RDES3_OWN_HBIT_POS  0x1f
#define RX_CONTEXT_DESC_RDES3_CTXT_HBIT_POS  0x1e
#define RX_CONTEXT_DESC_RDES2_RESERVED_BITS_HBIT_POS  0x1f
#define RX_CONTEXT_DESC_RDES1_RTSH_HBIT_POS  0x1f
#define RX_CONTEXT_DESC_RDES0_RTSL_HBIT_POS  0x1f
#define TX_CONTEXT_DESC_TDES3_OWN_HBIT_POS  0x1f
#define TX_CONTEXT_DESC_TDES3_CTXT_HBIT_POS  0x1e
#define TX_CONTEXT_DESC_TDES3_OSTC_HBIT_POS  0x1b
#define TX_CONTEXT_DESC_TDES3_TCMSSV_HBIT_POS  0x1a
#define TX_CONTEXT_DESC_TDES3_CDX_HBIT_POS  0x17
#define TX_CONTEXT_DESC_TDES3_IVTIR_HBIT_POS  0x13
#define TX_CONTEXT_DESC_TDES3_SVLTV_HBIT_POS  0x11
#define TX_CONTEXT_DESC_TDES3_IVLTV_HBIT_POS  0x11
#define TX_CONTEXT_DESC_TDES3_VLTV_HBIT_POS  0x10
#define TX_CONTEXT_DESC_TDES3_VT_HBIT_POS  0xf
#define TX_CONTEXT_DESC_TDES2_IVT_HBIT_POS  0x1f
#define TX_CONTEXT_DESC_TDES2_SVT_HBIT_POS  0x1f
#define TX_CONTEXT_DESC_TDES2_MSS_HBIT_POS  0xe
#define TX_CONTEXT_DESC_TDES1_NDAP_HBIT_POS  0x1f
#define TX_CONTEXT_DESC_TDES0_TTSL_HBIT_POS  0x1f
#define RX_NORMAL_DESC_RDES3_OWN_HBIT_POS  0x1f
#define RX_NORMAL_DESC_RDES3_CTXT_HBIT_POS  0x1e
#define RX_NORMAL_DESC_RDES3_FD_HBIT_POS  0x1d
#define RX_NORMAL_DESC_RDES3_LD_HBIT_POS  0x1c
#define RX_NORMAL_DESC_RDES3_RS2V_HBIT_POS  0x1b
#define RX_NORMAL_DESC_RDES3_RS1V_HBIT_POS  0x1a
#define RX_NORMAL_DESC_RDES3_RS0V_HBIT_POS  0x19
#define RX_NORMAL_DESC_RDES3_CE_HBIT_POS  0x18
#define RX_NORMAL_DESC_RDES3_GP_HBIT_POS  0x17
#define RX_NORMAL_DESC_RDES3_RWT_HBIT_POS  0x16
#define RX_NORMAL_DESC_RDES3_OE_HBIT_POS  0x15
#define RX_NORMAL_DESC_RDES3_RE_HBIT_POS  0x14
#define RX_NORMAL_DESC_RDES3_DE_HBIT_POS  0x13
#define RX_NORMAL_DESC_RDES3_LT_HBIT_POS  0x12
#define RX_NORMAL_DESC_RDES3_ES_HBIT_POS  0xf
#define RX_NORMAL_DESC_RDES3_FL_HBIT_POS  0xe
#define RX_NORMAL_DESC_RDES2_B2AP_NDA_HBIT_POS  0x1f
#define RX_NORMAL_DESC_RDES1_COP_HBIT_POS  0x1f
#define RX_NORMAL_DESC_RDES1_TD_HBIT_POS  0xf
#define RX_NORMAL_DESC_RDES1_TSA_HBIT_POS  0xe
#define RX_NORMAL_DESC_RDES1_PV_HBIT_POS  0xd
#define RX_NORMAL_DESC_RDES1_PFT_HBIT_POS  0xc
#define RX_NORMAL_DESC_RDES1_PMT_HBIT_POS  0xb
#define RX_NORMAL_DESC_RDES1_IPPE_HBIT_POS  0x7
#define RX_NORMAL_DESC_RDES1_IPCB_HBIT_POS  0x6
#define RX_NORMAL_DESC_RDES1_IPV6_HBIT_POS  0x5
#define RX_NORMAL_DESC_RDES1_IPV4_HBIT_POS  0x4
#define RX_NORMAL_DESC_RDES1_IPHE_HBIT_POS  0x3
#define RX_NORMAL_DESC_RDES1_PT_HBIT_POS  0x2
#define RX_NORMAL_DESC_RDES0_HDR_B1AP_HBIT_POS  0x1f
#define TX_NORMAL_DESC_TDES3_OWN_HBIT_POS  0x1f
#define TX_NORMAL_DESC_TDES3_CTXT_HBIT_POS  0x1e
#define TX_NORMAL_DESC_TDES3_FD_HBIT_POS  0x1d
#define TX_NORMAL_DESC_TDES3_LD_HBIT_POS  0x1c
#define TX_NORMAL_DESC_TDES3_CPC_HBIT_POS  0x1b
#define TX_NORMAL_DESC_TDES3_SAIC_HBIT_POS  0x19
#define TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_HBIT_POS  0x16
#define TX_NORMAL_DESC_TDES3_TSE_HBIT_POS  0x12
#define TX_NORMAL_DESC_TDES3_CIC_HBIT_POS  0x11
#define TX_NORMAL_DESC_TDES3_TIPLH_HBIT_POS  0xf
#define TX_NORMAL_DESC_TDES3_FL_HBIT_POS  0xe
#define TX_NORMAL_DESC_TDES2_IC_HBIT_POS  0x1f
#define TX_NORMAL_DESC_TDES2_TTSE_HBIT_POS  0x1e
#define TX_NORMAL_DESC_TDES2_B2L_HBIT_POS  0x1d
#define TX_NORMAL_DESC_TDES2_VTIR_HBIT_POS  0xf
#define TX_NORMAL_DESC_TDES2_HL_B1L_HBIT_POS  0xd
#define TX_NORMAL_DESC_TDES1_B2A_NDA_HBIT_POS  0x1f
#define TX_NORMAL_DESC_TDES0_B1A_HAP_HBIT_POS  0x1f
#define TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_HBIT_POS  0x4
#define TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_HBIT_POS  0x3
#define TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_HBIT_POS  0x2
#define TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_HBIT_POS  0x1
#define TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_HBIT_POS  0
#define RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_HBIT_POS  0x5
#define RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_HBIT_POS  0x4
#define RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_HBIT_POS  0x3
#define RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_HBIT_POS  0x2
#define RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_HBIT_POS  0x1
#define RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_HBIT_POS  0
#define RX_PKT_FEATURES_VLAN_TAG_SVT_HBIT_POS  0x1f
#define RX_PKT_FEATURES_VLAN_TAG_VT_HBIT_POS  0xf
#define RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_HBIT_POS  0x1
#define RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_HBIT_POS  0
#define TX_PKT_FEATURES_TCP_HDR_LEN_LEN_HBIT_POS  0x1f
#define TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_HBIT_POS  0x1
#define TX_PKT_FEATURES_PKT_TYPE_IP_PKT_HBIT_POS  0
#define TX_PKT_FEATURES_TUCSE_TCPCSE_HBIT_POS  0xf
#define TX_PKT_FEATURES_TUCSO_TCPCSO_HBIT_POS  0x7
#define TX_PKT_FEATURES_TUCSS_TCPCSS_HBIT_POS  0x7
#define TX_PKT_FEATURES_IPCSE_IPCSE_HBIT_POS  0xf
#define TX_PKT_FEATURES_IPCSO_IPCSO_HBIT_POS  0x7
#define TX_PKT_FEATURES_IPCSS_IPCSS_HBIT_POS  0x7
#define TX_PKT_FEATURES_PAY_LEN_PAY_LEN_HBIT_POS  0x3f
#define TX_PKT_FEATURES_HDR_LEN_HDR_LEN_HBIT_POS  0x3f
#define TX_PKT_FEATURES_MSS_MSS_HBIT_POS  0x3f
#define TX_PKT_FEATURES_VLAN_TAG_SVT_HBIT_POS  0x1f
#define TX_PKT_FEATURES_VLAN_TAG_VT_HBIT_POS  0xf
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_HBIT_POS  0x3
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_HBIT_POS  0x2
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_HBIT_POS  0x1
#define TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_HBIT_POS  0

/* virtual_registers Register-Field Read-Write Macros */
#define RX_CONTEXT_DESC_RDES3_OWN_RD(ptr, data) do { \
	GET_BITS(RX_CONTEXT_DESC_RDES3_OWN_HBIT_POS,\
	RX_CONTEXT_DESC_RDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES3_OWN_WR(ptr, data) do { \
	SET_BITS(RX_CONTEXT_DESC_RDES3_OWN_HBIT_POS,\
	RX_CONTEXT_DESC_RDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES3_CTXT_RD(ptr, data) do { \
	GET_BITS(RX_CONTEXT_DESC_RDES3_CTXT_HBIT_POS,\
	RX_CONTEXT_DESC_RDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES3_CTXT_WR(ptr, data) do { \
	SET_BITS(RX_CONTEXT_DESC_RDES3_CTXT_HBIT_POS,\
	RX_CONTEXT_DESC_RDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES2_RESERVED_BITS_RD(ptr, data) do { \
	GET_BITS(RX_CONTEXT_DESC_RDES2_RESERVED_BITS_HBIT_POS,\
	RX_CONTEXT_DESC_RDES2_RESERVED_BITS_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES2_RESERVED_BITS_WR(ptr, data) do { \
	SET_BITS(RX_CONTEXT_DESC_RDES2_RESERVED_BITS_HBIT_POS,\
	RX_CONTEXT_DESC_RDES2_RESERVED_BITS_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES1_RTSH_RD(ptr, data) do { \
	GET_BITS(RX_CONTEXT_DESC_RDES1_RTSH_HBIT_POS,\
	RX_CONTEXT_DESC_RDES1_RTSH_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES1_RTSH_WR(ptr, data) do { \
	SET_BITS(RX_CONTEXT_DESC_RDES1_RTSH_HBIT_POS,\
	RX_CONTEXT_DESC_RDES1_RTSH_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES0_RTSL_RD(ptr, data) do { \
	GET_BITS(RX_CONTEXT_DESC_RDES0_RTSL_HBIT_POS,\
	RX_CONTEXT_DESC_RDES0_RTSL_LBIT_POS, ptr, data); \
} while (0)

#define RX_CONTEXT_DESC_RDES0_RTSL_WR(ptr, data) do { \
	SET_BITS(RX_CONTEXT_DESC_RDES0_RTSL_HBIT_POS,\
	RX_CONTEXT_DESC_RDES0_RTSL_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_OWN_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_OWN_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_OWN_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_OWN_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_CTXT_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_CTXT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_CTXT_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_CTXT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_OSTC_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_OSTC_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_OSTC_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_OSTC_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_OSTC_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_OSTC_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_TCMSSV_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_TCMSSV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_TCMSSV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_TCMSSV_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_TCMSSV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_TCMSSV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_CDX_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_CDX_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_CDX_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_CDX_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_CDX_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_CDX_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_IVTIR_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_IVTIR_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_IVTIR_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_IVTIR_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_IVTIR_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_IVTIR_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_SVLTV_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_SVLTV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_SVLTV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_SVLTV_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_SVLTV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_SVLTV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_IVLTV_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_IVLTV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_IVLTV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_IVLTV_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_IVLTV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_IVLTV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_VLTV_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_VLTV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_VLTV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_VLTV_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_VLTV_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_VLTV_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_VT_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES3_VT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_VT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES3_VT_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES3_VT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES3_VT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES2_IVT_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES2_IVT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES2_IVT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES2_IVT_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES2_IVT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES2_IVT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES2_SVT_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES2_SVT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES2_SVT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES2_SVT_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES2_SVT_HBIT_POS,\
	TX_CONTEXT_DESC_TDES2_SVT_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES2_MSS_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES2_MSS_HBIT_POS,\
	TX_CONTEXT_DESC_TDES2_MSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES2_MSS_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES2_MSS_HBIT_POS,\
	TX_CONTEXT_DESC_TDES2_MSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES1_NDAP_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES1_NDAP_HBIT_POS,\
	TX_CONTEXT_DESC_TDES1_NDAP_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES1_NDAP_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES1_NDAP_HBIT_POS,\
	TX_CONTEXT_DESC_TDES1_NDAP_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES0_TTSL_RD(ptr, data) do { \
	GET_BITS(TX_CONTEXT_DESC_TDES0_TTSL_HBIT_POS,\
	TX_CONTEXT_DESC_TDES0_TTSL_LBIT_POS, ptr, data); \
} while (0)

#define TX_CONTEXT_DESC_TDES0_TTSL_WR(ptr, data) do { \
	SET_BITS(TX_CONTEXT_DESC_TDES0_TTSL_HBIT_POS,\
	TX_CONTEXT_DESC_TDES0_TTSL_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_OWN_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_OWN_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_OWN_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_OWN_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_CTXT_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_CTXT_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_CTXT_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_CTXT_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_FD_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_FD_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_FD_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_FD_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_FD_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_FD_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_LD_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_LD_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_LD_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_LD_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_LD_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_LD_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RS2V_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_RS2V_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RS2V_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RS2V_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_RS2V_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RS2V_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RS1V_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_RS1V_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RS1V_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RS1V_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_RS1V_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RS1V_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RS0V_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_RS0V_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RS0V_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RS0V_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_RS0V_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RS0V_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_CE_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_CE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_CE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_CE_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_CE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_CE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_GP_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_GP_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_GP_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_GP_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_GP_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_GP_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RWT_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_RWT_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RWT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RWT_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_RWT_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RWT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_OE_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_OE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_OE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_OE_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_OE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_OE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RE_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_RE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_RE_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_RE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_RE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_DE_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_DE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_DE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_DE_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_DE_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_DE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_LT_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_LT_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_LT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_LT_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_LT_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_LT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_ES_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_ES_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_ES_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_ES_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_ES_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_ES_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_FL_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES3_FL_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_FL_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES3_FL_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES3_FL_HBIT_POS,\
	RX_NORMAL_DESC_RDES3_FL_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES2_B2AP_NDA_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES2_B2AP_NDA_HBIT_POS,\
	RX_NORMAL_DESC_RDES2_B2AP_NDA_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES2_B2AP_NDA_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES2_B2AP_NDA_HBIT_POS,\
	RX_NORMAL_DESC_RDES2_B2AP_NDA_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_COP_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_COP_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_COP_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_COP_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_COP_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_COP_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_TD_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_TD_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_TD_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_TD_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_TD_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_TD_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_TSA_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_TSA_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_TSA_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_TSA_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_TSA_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_TSA_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PV_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_PV_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PV_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PV_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_PV_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PV_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PFT_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_PFT_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PFT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PFT_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_PFT_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PFT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PMT_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_PMT_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PMT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PMT_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_PMT_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PMT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPPE_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_IPPE_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPPE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPPE_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_IPPE_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPPE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPCB_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_IPCB_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPCB_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPCB_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_IPCB_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPCB_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPV6_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_IPV6_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPV6_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPV6_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_IPV6_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPV6_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPV4_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_IPV4_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPV4_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPV4_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_IPV4_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPV4_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPHE_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_IPHE_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPHE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_IPHE_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_IPHE_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_IPHE_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PT_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES1_PT_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES1_PT_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES1_PT_HBIT_POS,\
	RX_NORMAL_DESC_RDES1_PT_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES0_HDR_B1AP_RD(ptr, data) do { \
	GET_BITS(RX_NORMAL_DESC_RDES0_HDR_B1AP_HBIT_POS,\
	RX_NORMAL_DESC_RDES0_HDR_B1AP_LBIT_POS, ptr, data); \
} while (0)

#define RX_NORMAL_DESC_RDES0_HDR_B1AP_WR(ptr, data) do { \
	SET_BITS(RX_NORMAL_DESC_RDES0_HDR_B1AP_HBIT_POS,\
	RX_NORMAL_DESC_RDES0_HDR_B1AP_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_OWN_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_OWN_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_OWN_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_OWN_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_OWN_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_CTXT_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_CTXT_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_CTXT_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_CTXT_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_CTXT_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_FD_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_FD_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_FD_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_FD_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_FD_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_FD_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_LD_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_LD_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_LD_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_LD_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_LD_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_LD_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_CPC_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_CPC_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_CPC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_CPC_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_CPC_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_CPC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_SAIC_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_SAIC_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_SAIC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_SAIC_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_SAIC_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_SAIC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_SLOTNUM_TCPHDRLEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_TSE_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_TSE_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_TSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_TSE_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_TSE_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_TSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_CIC_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_CIC_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_CIC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_CIC_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_CIC_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_CIC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_TIPLH_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_TIPLH_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_TIPLH_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_TIPLH_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_TIPLH_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_TIPLH_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_FL_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES3_FL_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_FL_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES3_FL_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES3_FL_HBIT_POS,\
	TX_NORMAL_DESC_TDES3_FL_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_IC_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES2_IC_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_IC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_IC_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES2_IC_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_IC_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_TTSE_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES2_TTSE_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_TTSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_TTSE_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES2_TTSE_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_TTSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_B2L_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES2_B2L_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_B2L_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_B2L_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES2_B2L_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_B2L_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_VTIR_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES2_VTIR_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_VTIR_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_VTIR_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES2_VTIR_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_VTIR_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_HL_B1L_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES2_HL_B1L_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_HL_B1L_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES2_HL_B1L_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES2_HL_B1L_HBIT_POS,\
	TX_NORMAL_DESC_TDES2_HL_B1L_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES1_B2A_NDA_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES1_B2A_NDA_HBIT_POS,\
	TX_NORMAL_DESC_TDES1_B2A_NDA_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES1_B2A_NDA_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES1_B2A_NDA_HBIT_POS,\
	TX_NORMAL_DESC_TDES1_B2A_NDA_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES0_B1A_HAP_RD(ptr, data) do { \
	GET_BITS(TX_NORMAL_DESC_TDES0_B1A_HAP_HBIT_POS,\
	TX_NORMAL_DESC_TDES0_B1A_HAP_LBIT_POS, ptr, data); \
} while (0)

#define TX_NORMAL_DESC_TDES0_B1A_HAP_WR(ptr, data) do { \
	SET_BITS(TX_NORMAL_DESC_TDES0_B1A_HAP_HBIT_POS,\
	TX_NORMAL_DESC_TDES0_B1A_HAP_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_RD(ptr, data) do { \
	GET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_WR(ptr, data) do { \
	SET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_HEARTBEAT_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_RD(ptr, data) do { \
	GET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_WR(ptr, data) do { \
	SET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_WINDOW_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_RD(ptr, data) do { \
	GET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_WR(ptr, data) do { \
	SET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_FIFO_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_RD(ptr, data) do { \
	GET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_WR(ptr, data) do { \
	SET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_CARRIER_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_RD(ptr, data) do { \
	GET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_WR(ptr, data) do { \
	SET_BITS(TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_HBIT_POS,\
	TX_ERROR_COUNTERS_TX_ERRORS_ABORTED_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_RD(ptr, data) do { \
	GET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_WR(ptr, data) do { \
	SET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_MISSED_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_RD(ptr, data) do { \
	GET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_WR(ptr, data) do { \
	SET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_FIFO_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_RD(ptr, data) do { \
	GET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_WR(ptr, data) do { \
	SET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_FRAME_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_RD(ptr, data) do { \
	GET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_WR(ptr, data) do { \
	SET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_CRC_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_RD(ptr, data) do { \
	GET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_WR(ptr, data) do { \
	SET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_OVERRUN_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_RD(ptr, data) do { \
	GET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_WR(ptr, data) do { \
	SET_BITS(RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_HBIT_POS,\
	RX_ERROR_COUNTERS_RX_ERRORS_LENGTH_ERROR_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_VLAN_TAG_SVT_RD(ptr, data) do { \
	GET_BITS(RX_PKT_FEATURES_VLAN_TAG_SVT_HBIT_POS,\
	RX_PKT_FEATURES_VLAN_TAG_SVT_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_VLAN_TAG_SVT_WR(ptr, data) do { \
	SET_BITS(RX_PKT_FEATURES_VLAN_TAG_SVT_HBIT_POS,\
	RX_PKT_FEATURES_VLAN_TAG_SVT_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_VLAN_TAG_VT_RD(ptr, data) do { \
	GET_BITS(RX_PKT_FEATURES_VLAN_TAG_VT_HBIT_POS,\
	RX_PKT_FEATURES_VLAN_TAG_VT_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_VLAN_TAG_VT_WR(ptr, data) do { \
	SET_BITS(RX_PKT_FEATURES_VLAN_TAG_VT_HBIT_POS,\
	RX_PKT_FEATURES_VLAN_TAG_VT_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_RD(ptr, data) do { \
	GET_BITS(RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_HBIT_POS,\
	RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_WR(ptr, data) do { \
	SET_BITS(RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_HBIT_POS,\
	RX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_RD(ptr, data) do { \
	GET_BITS(RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_HBIT_POS,\
	RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_LBIT_POS, ptr, data); \
} while (0)

#define RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_WR(ptr, data) do { \
	SET_BITS(RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_HBIT_POS,\
	RX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_DONE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TCP_HDR_LEN_LEN_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_TCP_HDR_LEN_LEN_HBIT_POS,\
	TX_PKT_FEATURES_TCP_HDR_LEN_LEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TCP_HDR_LEN_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_TCP_HDR_LEN_LEN_HBIT_POS,\
	TX_PKT_FEATURES_TCP_HDR_LEN_LEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_HBIT_POS,\
	TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_HBIT_POS,\
	TX_PKT_FEATURES_PKT_TYPE_TCP_PKT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_TYPE_IP_PKT_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PKT_TYPE_IP_PKT_HBIT_POS,\
	TX_PKT_FEATURES_PKT_TYPE_IP_PKT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_TYPE_IP_PKT_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PKT_TYPE_IP_PKT_HBIT_POS,\
	TX_PKT_FEATURES_PKT_TYPE_IP_PKT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TUCSE_TCPCSE_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_TUCSE_TCPCSE_HBIT_POS,\
	TX_PKT_FEATURES_TUCSE_TCPCSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TUCSE_TCPCSE_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_TUCSE_TCPCSE_HBIT_POS,\
	TX_PKT_FEATURES_TUCSE_TCPCSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TUCSO_TCPCSO_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_TUCSO_TCPCSO_HBIT_POS,\
	TX_PKT_FEATURES_TUCSO_TCPCSO_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TUCSO_TCPCSO_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_TUCSO_TCPCSO_HBIT_POS,\
	TX_PKT_FEATURES_TUCSO_TCPCSO_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TUCSS_TCPCSS_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_TUCSS_TCPCSS_HBIT_POS,\
	TX_PKT_FEATURES_TUCSS_TCPCSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_TUCSS_TCPCSS_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_TUCSS_TCPCSS_HBIT_POS,\
	TX_PKT_FEATURES_TUCSS_TCPCSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_IPCSE_IPCSE_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_IPCSE_IPCSE_HBIT_POS,\
	TX_PKT_FEATURES_IPCSE_IPCSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_IPCSE_IPCSE_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_IPCSE_IPCSE_HBIT_POS,\
	TX_PKT_FEATURES_IPCSE_IPCSE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_IPCSO_IPCSO_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_IPCSO_IPCSO_HBIT_POS,\
	TX_PKT_FEATURES_IPCSO_IPCSO_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_IPCSO_IPCSO_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_IPCSO_IPCSO_HBIT_POS,\
	TX_PKT_FEATURES_IPCSO_IPCSO_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_IPCSS_IPCSS_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_IPCSS_IPCSS_HBIT_POS,\
	TX_PKT_FEATURES_IPCSS_IPCSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_IPCSS_IPCSS_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_IPCSS_IPCSS_HBIT_POS,\
	TX_PKT_FEATURES_IPCSS_IPCSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PAY_LEN_PAY_LEN_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PAY_LEN_PAY_LEN_HBIT_POS,\
	TX_PKT_FEATURES_PAY_LEN_PAY_LEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PAY_LEN_PAY_LEN_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PAY_LEN_PAY_LEN_HBIT_POS,\
	TX_PKT_FEATURES_PAY_LEN_PAY_LEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_HDR_LEN_HDR_LEN_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_HDR_LEN_HDR_LEN_HBIT_POS,\
	TX_PKT_FEATURES_HDR_LEN_HDR_LEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_HDR_LEN_HDR_LEN_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_HDR_LEN_HDR_LEN_HBIT_POS,\
	TX_PKT_FEATURES_HDR_LEN_HDR_LEN_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_MSS_MSS_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_MSS_MSS_HBIT_POS,\
	TX_PKT_FEATURES_MSS_MSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_MSS_MSS_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_MSS_MSS_HBIT_POS,\
	TX_PKT_FEATURES_MSS_MSS_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_VLAN_TAG_SVT_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_VLAN_TAG_SVT_HBIT_POS,\
	TX_PKT_FEATURES_VLAN_TAG_SVT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_VLAN_TAG_SVT_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_VLAN_TAG_SVT_HBIT_POS,\
	TX_PKT_FEATURES_VLAN_TAG_SVT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_VLAN_TAG_VT_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_VLAN_TAG_VT_HBIT_POS,\
	TX_PKT_FEATURES_VLAN_TAG_VT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_VLAN_TAG_VT_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_VLAN_TAG_VT_HBIT_POS,\
	TX_PKT_FEATURES_VLAN_TAG_VT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_VLAN_PKT_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_PTP_ENABLE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_TSO_ENABLE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_RD(ptr, data) do { \
	GET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_LBIT_POS, ptr, data); \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_WR(ptr, data) do { \
	SET_BITS(TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_HBIT_POS,\
	TX_PKT_FEATURES_PKT_ATTRIBUTES_CSUM_ENABLE_LBIT_POS, ptr, data); \
} while (0)

/* virtual_registers Register Read-Write Macros */
#define RX_CONTEXT_DESC_RDES3_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_CONTEXT_DESC_RDES3_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_CONTEXT_DESC_RDES2_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_CONTEXT_DESC_RDES2_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_CONTEXT_DESC_RDES1_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_CONTEXT_DESC_RDES1_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_CONTEXT_DESC_RDES0_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_CONTEXT_DESC_RDES0_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_CONTEXT_DESC_TDES3_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_CONTEXT_DESC_TDES3_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_CONTEXT_DESC_TDES2_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_CONTEXT_DESC_TDES2_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_CONTEXT_DESC_TDES1_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_CONTEXT_DESC_TDES1_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_CONTEXT_DESC_TDES0_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_CONTEXT_DESC_TDES0_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_RDES3_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_RDES3_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_RDES2_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_RDES2_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_RDES1_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_RDES1_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_RDES0_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_RDES0_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_TX_ERRORS_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_TX_ERRORS_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_RX_BUF_PTR_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_RX_BUF_PTR_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_NEXT_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_NEXT_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_NORMAL_DESC_SKB_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_NORMAL_DESC_SKB_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_NORMAL_DESC_TDES3_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_NORMAL_DESC_TDES3_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_NORMAL_DESC_TDES2_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_NORMAL_DESC_TDES2_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_NORMAL_DESC_TDES1_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_NORMAL_DESC_TDES1_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_NORMAL_DESC_TDES0_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_NORMAL_DESC_TDES0_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_NORMAL_DESC_TX_BUF_PTR_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_NORMAL_DESC_TX_BUF_PTR_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_NORMAL_DESC_NEXT_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_NORMAL_DESC_NEXT_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_ERROR_COUNTERS_TX_ERRORS_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_ERROR_COUNTERS_RX_ERRORS_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_PKT_FEATURES_VLAN_TAG_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_PKT_FEATURES_VLAN_TAG_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define RX_PKT_FEATURES_PKT_ATTRIBUTES_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define RX_PKT_FEATURES_PKT_ATTRIBUTES_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_TCP_HDR_LEN_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_PKT_TYPE_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_PKT_TYPE_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_TUCSE_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_TUCSE_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_TUCSO_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_TUCSO_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_TUCSS_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_TUCSS_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_IPCSE_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_IPCSE_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_IPCSO_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_IPCSO_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_IPCSS_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_IPCSS_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_PAY_LEN_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_PAY_LEN_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_HDR_LEN_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_HDR_LEN_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_MSS_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_MSS_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_VLAN_TAG_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_VLAN_TAG_WR(ptr, data) do { \
	ptr = data; \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_RD(ptr, data) do { \
	data = ptr; \
} while (0)

#define TX_PKT_FEATURES_PKT_ATTRIBUTES_WR(ptr, data) do { \
	ptr = data; \
} while (0)

extern ULONG eqos_base_addr;
#define  BASE_ADDRESS eqos_base_addr

#ifdef EQOS_VER_4_0
#define MAC_ARPA_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x0ae0))
#else
#define MAC_ARPA_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x0210))
#endif

#define MAC_ARPA_WR(data) do {\
	iowrite32(data, (void *)MAC_ARPA_OFFSET);\
} while (0)

#define MAC_ARPA_RD(data) do {\
	(data) = ioread32((void *)MAC_ARPA_OFFSET);\
} while (0)

#define MAC_ARPA_ARPPA_WR(data) do {\
	MAC_ARPA_WR(data);\
} while (0)

#define MAC_ARPA_ARPPA_RD(data) do {\
	MAC_ARPA_RD(data);\
} while (0)

#define MAC_L3A3R7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa6c))

#define MAC_L3A3R7_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R7_OFFSET);\
} while (0)

#define MAC_L3A3R7_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R7_OFFSET);\
} while (0)

#define MAC_L3A3R7_L3A30_WR(data) do {\
	MAC_L3A3R7_WR(data);\
} while (0)

#define MAC_L3A3R7_L3A30_RD(data) do {\
	MAC_L3A3R7_RD(data);\
} while (0)

#define MAC_L3A3R6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa3c))

#define MAC_L3A3R6_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R6_OFFSET);\
} while (0)

#define MAC_L3A3R6_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R6_OFFSET);\
} while (0)

#define MAC_L3A3R6_L3A30_WR(data) do {\
	MAC_L3A3R6_WR(data);\
} while (0)

#define MAC_L3A3R6_L3A30_RD(data) do {\
	MAC_L3A3R6_RD(data);\
} while (0)

#define MAC_L3A3R5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa0c))

#define MAC_L3A3R5_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R5_OFFSET);\
} while (0)

#define MAC_L3A3R5_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R5_OFFSET);\
} while (0)

#define MAC_L3A3R5_L3A30_WR(data) do {\
	MAC_L3A3R5_WR(data);\
} while (0)

#define MAC_L3A3R5_L3A30_RD(data) do {\
	MAC_L3A3R5_RD(data);\
} while (0)

#define MAC_L3A3R4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9dc))

#define MAC_L3A3R4_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R4_OFFSET);\
} while (0)

#define MAC_L3A3R4_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R4_OFFSET);\
} while (0)

#define MAC_L3A3R4_L3A30_WR(data) do {\
	MAC_L3A3R4_WR(data);\
} while (0)

#define MAC_L3A3R4_L3A30_RD(data) do {\
	MAC_L3A3R4_RD(data);\
} while (0)

#define MAC_L3A3R3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9ac))

#define MAC_L3A3R3_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R3_OFFSET);\
} while (0)

#define MAC_L3A3R3_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R3_OFFSET);\
} while (0)

#define MAC_L3A3R3_L3A30_WR(data) do {\
	MAC_L3A3R3_WR(data);\
} while (0)

#define MAC_L3A3R3_L3A30_RD(data) do {\
	MAC_L3A3R3_RD(data);\
} while (0)

#define MAC_L3A3R2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x97c))

#define MAC_L3A3R2_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R2_OFFSET);\
} while (0)

#define MAC_L3A3R2_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R2_OFFSET);\
} while (0)

#define MAC_L3A3R2_L3A30_WR(data) do {\
	MAC_L3A3R2_WR(data);\
} while (0)

#define MAC_L3A3R2_L3A30_RD(data) do {\
	MAC_L3A3R2_RD(data);\
} while (0)

#define MAC_L3A3R1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x94c))

#define MAC_L3A3R1_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R1_OFFSET);\
} while (0)

#define MAC_L3A3R1_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R1_OFFSET);\
} while (0)

#define MAC_L3A3R1_L3A30_WR(data) do {\
	MAC_L3A3R1_WR(data);\
} while (0)

#define MAC_L3A3R1_L3A30_RD(data) do {\
	MAC_L3A3R1_RD(data);\
} while (0)

#define MAC_L3A3R0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x91c))

#define MAC_L3A3R0_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A3R0_OFFSET);\
} while (0)

#define MAC_L3A3R0_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A3R0_OFFSET);\
} while (0)

#define MAC_L3A3R0_L3A30_WR(data) do {\
	MAC_L3A3R0_WR(data);\
} while (0)

#define MAC_L3A3R0_L3A30_RD(data) do {\
	MAC_L3A3R0_RD(data);\
} while (0)

#define MAC_L3A2R7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa68))

#define MAC_L3A2R7_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R7_OFFSET);\
} while (0)

#define MAC_L3A2R7_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R7_OFFSET);\
} while (0)

#define MAC_L3A2R7_L3A20_WR(data) do {\
	MAC_L3A2R7_WR(data);\
} while (0)

#define MAC_L3A2R7_L3A20_RD(data) do {\
	MAC_L3A2R7_RD(data);\
} while (0)

#define MAC_L3A2R6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa38))

#define MAC_L3A2R6_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R6_OFFSET);\
} while (0)

#define MAC_L3A2R6_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R6_OFFSET);\
} while (0)

#define MAC_L3A2R6_L3A20_WR(data) do {\
	MAC_L3A2R6_WR(data);\
} while (0)

#define MAC_L3A2R6_L3A20_RD(data) do {\
	MAC_L3A2R6_RD(data);\
} while (0)

#define MAC_L3A2R5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa08))

#define MAC_L3A2R5_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R5_OFFSET);\
} while (0)

#define MAC_L3A2R5_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R5_OFFSET);\
} while (0)

#define MAC_L3A2R5_L3A20_WR(data) do {\
	MAC_L3A2R5_WR(data);\
} while (0)

#define MAC_L3A2R5_L3A20_RD(data) do {\
	MAC_L3A2R5_RD(data);\
} while (0)

#define MAC_L3A2R4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9d8))

#define MAC_L3A2R4_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R4_OFFSET);\
} while (0)

#define MAC_L3A2R4_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R4_OFFSET);\
} while (0)

#define MAC_L3A2R4_L3A20_WR(data) do {\
	MAC_L3A2R4_WR(data);\
} while (0)

#define MAC_L3A2R4_L3A20_RD(data) do {\
	MAC_L3A2R4_RD(data);\
} while (0)

#define MAC_L3A2R3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9a8))

#define MAC_L3A2R3_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R3_OFFSET);\
} while (0)

#define MAC_L3A2R3_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R3_OFFSET);\
} while (0)

#define MAC_L3A2R3_L3A20_WR(data) do {\
	MAC_L3A2R3_WR(data);\
} while (0)

#define MAC_L3A2R3_L3A20_RD(data) do {\
	MAC_L3A2R3_RD(data);\
} while (0)

#define MAC_L3A2R2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x978))

#define MAC_L3A2R2_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R2_OFFSET);\
} while (0)

#define MAC_L3A2R2_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R2_OFFSET);\
} while (0)

#define MAC_L3A2R2_L3A20_WR(data) do {\
	MAC_L3A2R2_WR(data);\
} while (0)

#define MAC_L3A2R2_L3A20_RD(data) do {\
	MAC_L3A2R2_RD(data);\
} while (0)

#define MAC_L3A2R1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x948))

#define MAC_L3A2R1_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R1_OFFSET);\
} while (0)

#define MAC_L3A2R1_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R1_OFFSET);\
} while (0)

#define MAC_L3A2R1_L3A20_WR(data) do {\
	MAC_L3A2R1_WR(data);\
} while (0)

#define MAC_L3A2R1_L3A20_RD(data) do {\
	MAC_L3A2R1_RD(data);\
} while (0)

#define MAC_L3A2R0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x918))

#define MAC_L3A2R0_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A2R0_OFFSET);\
} while (0)

#define MAC_L3A2R0_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A2R0_OFFSET);\
} while (0)

#define MAC_L3A2R0_L3A20_WR(data) do {\
	MAC_L3A2R0_WR(data);\
} while (0)

#define MAC_L3A2R0_L3A20_RD(data) do {\
	MAC_L3A2R0_RD(data);\
} while (0)

#define MAC_L3A1R7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa64))

#define MAC_L3A1R7_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R7_OFFSET);\
} while (0)

#define MAC_L3A1R7_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R7_OFFSET);\
} while (0)

#define MAC_L3A1R7_L3A10_WR(data) do {\
	MAC_L3A1R7_WR(data);\
} while (0)

#define MAC_L3A1R7_L3A10_RD(data) do {\
	MAC_L3A1R7_RD(data);\
} while (0)

#define MAC_L3A1R6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa34))

#define MAC_L3A1R6_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R6_OFFSET);\
} while (0)

#define MAC_L3A1R6_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R6_OFFSET);\
} while (0)

#define MAC_L3A1R6_L3A10_WR(data) do {\
	MAC_L3A1R6_WR(data);\
} while (0)

#define MAC_L3A1R6_L3A10_RD(data) do {\
	MAC_L3A1R6_RD(data);\
} while (0)

#define MAC_L3A1R5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa04))

#define MAC_L3A1R5_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R5_OFFSET);\
} while (0)

#define MAC_L3A1R5_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R5_OFFSET);\
} while (0)

#define MAC_L3A1R5_L3A10_WR(data) do {\
	MAC_L3A1R5_WR(data);\
} while (0)

#define MAC_L3A1R5_L3A10_RD(data) do {\
	MAC_L3A1R5_RD(data);\
} while (0)

#define MAC_L3A1R4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9d4))

#define MAC_L3A1R4_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R4_OFFSET);\
} while (0)

#define MAC_L3A1R4_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R4_OFFSET);\
} while (0)

#define MAC_L3A1R4_L3A10_WR(data) do {\
	MAC_L3A1R4_WR(data);\
} while (0)

#define MAC_L3A1R4_L3A10_RD(data) do {\
	MAC_L3A1R4_RD(data);\
} while (0)

#define MAC_L3A1R3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9a4))

#define MAC_L3A1R3_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R3_OFFSET);\
} while (0)

#define MAC_L3A1R3_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R3_OFFSET);\
} while (0)

#define MAC_L3A1R3_L3A10_WR(data) do {\
	MAC_L3A1R3_WR(data);\
} while (0)

#define MAC_L3A1R3_L3A10_RD(data) do {\
	MAC_L3A1R3_RD(data);\
} while (0)

#define MAC_L3A1R2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x974))

#define MAC_L3A1R2_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R2_OFFSET);\
} while (0)

#define MAC_L3A1R2_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R2_OFFSET);\
} while (0)

#define MAC_L3A1R2_L3A10_WR(data) do {\
	MAC_L3A1R2_WR(data);\
} while (0)

#define MAC_L3A1R2_L3A10_RD(data) do {\
	MAC_L3A1R2_RD(data);\
} while (0)

#define MAC_L3A1R1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x944))

#define MAC_L3A1R1_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R1_OFFSET);\
} while (0)

#define MAC_L3A1R1_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R1_OFFSET);\
} while (0)

#define MAC_L3A1R1_L3A10_WR(data) do {\
	MAC_L3A1R1_WR(data);\
} while (0)

#define MAC_L3A1R1_L3A10_RD(data) do {\
	MAC_L3A1R1_RD(data);\
} while (0)

#define MAC_L3A1R0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x914))

#define MAC_L3A1R0_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A1R0_OFFSET);\
} while (0)

#define MAC_L3A1R0_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A1R0_OFFSET);\
} while (0)

#define MAC_L3A1R0_L3A10_WR(data) do {\
	MAC_L3A1R0_WR(data);\
} while (0)

#define MAC_L3A1R0_L3A10_RD(data) do {\
	MAC_L3A1R0_RD(data);\
} while (0)

#define MAC_L3A0R7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa60))

#define MAC_L3A0R7_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R7_OFFSET);\
} while (0)

#define MAC_L3A0R7_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R7_OFFSET);\
} while (0)

#define MAC_L3A0R7_L3A00_WR(data) do {\
	MAC_L3A0R7_WR(data);\
} while (0)

#define MAC_L3A0R7_L3A00_RD(data) do {\
	MAC_L3A0R7_RD(data);\
} while (0)

#define MAC_L3A0R6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa30))

#define MAC_L3A0R6_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R6_OFFSET);\
} while (0)

#define MAC_L3A0R6_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R6_OFFSET);\
} while (0)

#define MAC_L3A0R6_L3A00_WR(data) do {\
	MAC_L3A0R6_WR(data);\
} while (0)

#define MAC_L3A0R6_L3A00_RD(data) do {\
	MAC_L3A0R6_RD(data);\
} while (0)

#define MAC_L3A0R5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa00))

#define MAC_L3A0R5_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R5_OFFSET);\
} while (0)

#define MAC_L3A0R5_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R5_OFFSET);\
} while (0)

#define MAC_L3A0R5_L3A00_WR(data) do {\
	MAC_L3A0R5_WR(data);\
} while (0)

#define MAC_L3A0R5_L3A00_RD(data) do {\
	MAC_L3A0R5_RD(data);\
} while (0)

#define MAC_L3A0R4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9d0))

#define MAC_L3A0R4_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R4_OFFSET);\
} while (0)

#define MAC_L3A0R4_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R4_OFFSET);\
} while (0)

#define MAC_L3A0R4_L3A00_WR(data) do {\
	MAC_L3A0R4_WR(data);\
} while (0)

#define MAC_L3A0R4_L3A00_RD(data) do {\
	MAC_L3A0R4_RD(data);\
} while (0)

#define MAC_L3A0R3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9a0))

#define MAC_L3A0R3_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R3_OFFSET);\
} while (0)

#define MAC_L3A0R3_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R3_OFFSET);\
} while (0)

#define MAC_L3A0R3_L3A00_WR(data) do {\
	MAC_L3A0R3_WR(data);\
} while (0)

#define MAC_L3A0R3_L3A00_RD(data) do {\
	MAC_L3A0R3_RD(data);\
} while (0)

#define MAC_L3A0R2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x970))

#define MAC_L3A0R2_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R2_OFFSET);\
} while (0)

#define MAC_L3A0R2_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R2_OFFSET);\
} while (0)

#define MAC_L3A0R2_L3A00_WR(data) do {\
	MAC_L3A0R2_WR(data);\
} while (0)

#define MAC_L3A0R2_L3A00_RD(data) do {\
	MAC_L3A0R2_RD(data);\
} while (0)

#define MAC_L3A0R1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x940))

#define MAC_L3A0R1_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R1_OFFSET);\
} while (0)

#define MAC_L3A0R1_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R1_OFFSET);\
} while (0)

#define MAC_L3A0R1_L3A00_WR(data) do {\
	MAC_L3A0R1_WR(data);\
} while (0)

#define MAC_L3A0R1_L3A00_RD(data) do {\
	MAC_L3A0R1_RD(data);\
} while (0)

#define MAC_L3A0R0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x910))

#define MAC_L3A0R0_WR(data) do {\
	iowrite32(data, (void *)MAC_L3A0R0_OFFSET);\
} while (0)

#define MAC_L3A0R0_RD(data) do {\
	(data) = ioread32((void *)MAC_L3A0R0_OFFSET);\
} while (0)

#define MAC_L3A0R0_L3A00_WR(data) do {\
	MAC_L3A0R0_WR(data);\
} while (0)

#define MAC_L3A0R0_L3A00_RD(data) do {\
	MAC_L3A0R0_RD(data);\
} while (0)

#define MAC_L4AR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa54))

#define MAC_L4AR7_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR7_OFFSET);\
} while (0)

#define MAC_L4AR7_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR7_OFFSET);\
} while (0)

#define MAC_L4AR7_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR7_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR7_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR7_RD(v);\
	v = ((v & MAC_L4AR7_L4SP0_WR_MASK)\
	|((data & MAC_L4AR7_L4SP0_MASK)<<0));\
	MAC_L4AR7_WR(v);\
} while (0)

#define MAC_L4AR7_L4SP0_RD(data) do {\
	MAC_L4AR7_RD(data);\
	data = ((data >> 0) & MAC_L4AR7_L4SP0_MASK);\
} while (0)

#define MAC_L4AR7_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR7_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR7_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR7_RD(v);\
	v = ((v & MAC_L4AR7_L4DP0_WR_MASK)\
	|((data & MAC_L4AR7_L4DP0_MASK)<<16));\
	MAC_L4AR7_WR(v);\
} while (0)

#define MAC_L4AR7_L4DP0_RD(data) do {\
	MAC_L4AR7_RD(data);\
	data = ((data >> 16) & MAC_L4AR7_L4DP0_MASK);\
} while (0)

#define MAC_L4AR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa24))

#define MAC_L4AR6_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR6_OFFSET);\
} while (0)

#define MAC_L4AR6_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR6_OFFSET);\
} while (0)

#define MAC_L4AR6_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR6_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR6_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR6_RD(v);\
	v = ((v & MAC_L4AR6_L4SP0_WR_MASK)\
	|((data & MAC_L4AR6_L4SP0_MASK)<<0));\
	MAC_L4AR6_WR(v);\
} while (0)

#define MAC_L4AR6_L4SP0_RD(data) do {\
	MAC_L4AR6_RD(data);\
	data = ((data >> 0) & MAC_L4AR6_L4SP0_MASK);\
} while (0)

#define MAC_L4AR6_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR6_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR6_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR6_RD(v);\
	v = ((v & MAC_L4AR6_L4DP0_WR_MASK)\
	|((data & MAC_L4AR6_L4DP0_MASK)<<16));\
	MAC_L4AR6_WR(v);\
} while (0)

#define MAC_L4AR6_L4DP0_RD(data) do {\
	MAC_L4AR6_RD(data);\
	data = ((data >> 16) & MAC_L4AR6_L4DP0_MASK);\
} while (0)

#define MAC_L4AR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9f4))

#define MAC_L4AR5_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR5_OFFSET);\
} while (0)

#define MAC_L4AR5_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR5_OFFSET);\
} while (0)

#define MAC_L4AR5_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR5_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR5_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR5_RD(v);\
	v = ((v & MAC_L4AR5_L4SP0_WR_MASK)\
	|((data & MAC_L4AR5_L4SP0_MASK)<<0));\
	MAC_L4AR5_WR(v);\
} while (0)

#define MAC_L4AR5_L4SP0_RD(data) do {\
	MAC_L4AR5_RD(data);\
	data = ((data >> 0) & MAC_L4AR5_L4SP0_MASK);\
} while (0)

#define MAC_L4AR5_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR5_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR5_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR5_RD(v);\
	v = ((v & MAC_L4AR5_L4DP0_WR_MASK)\
	|((data & MAC_L4AR5_L4DP0_MASK)<<16));\
	MAC_L4AR5_WR(v);\
} while (0)

#define MAC_L4AR5_L4DP0_RD(data) do {\
	MAC_L4AR5_RD(data);\
	data = ((data >> 16) & MAC_L4AR5_L4DP0_MASK);\
} while (0)

#define MAC_L4AR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9c4))

#define MAC_L4AR4_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR4_OFFSET);\
} while (0)

#define MAC_L4AR4_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR4_OFFSET);\
} while (0)

#define MAC_L4AR4_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR4_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR4_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR4_RD(v);\
	v = ((v & MAC_L4AR4_L4SP0_WR_MASK)\
	|((data & MAC_L4AR4_L4SP0_MASK)<<0));\
	MAC_L4AR4_WR(v);\
} while (0)

#define MAC_L4AR4_L4SP0_RD(data) do {\
	MAC_L4AR4_RD(data);\
	data = ((data >> 0) & MAC_L4AR4_L4SP0_MASK);\
} while (0)

#define MAC_L4AR4_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR4_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR4_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR4_RD(v);\
	v = ((v & MAC_L4AR4_L4DP0_WR_MASK)\
	|((data & MAC_L4AR4_L4DP0_MASK)<<16));\
	MAC_L4AR4_WR(v);\
} while (0)

#define MAC_L4AR4_L4DP0_RD(data) do {\
	MAC_L4AR4_RD(data);\
	data = ((data >> 16) & MAC_L4AR4_L4DP0_MASK);\
} while (0)

#define MAC_L4AR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x994))

#define MAC_L4AR3_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR3_OFFSET);\
} while (0)

#define MAC_L4AR3_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR3_OFFSET);\
} while (0)

#define MAC_L4AR3_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR3_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR3_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR3_RD(v);\
	v = ((v & MAC_L4AR3_L4SP0_WR_MASK)\
	|((data & MAC_L4AR3_L4SP0_MASK)<<0));\
	MAC_L4AR3_WR(v);\
} while (0)

#define MAC_L4AR3_L4SP0_RD(data) do {\
	MAC_L4AR3_RD(data);\
	data = ((data >> 0) & MAC_L4AR3_L4SP0_MASK);\
} while (0)

#define MAC_L4AR3_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR3_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR3_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR3_RD(v);\
	v = ((v & MAC_L4AR3_L4DP0_WR_MASK)\
	|((data & MAC_L4AR3_L4DP0_MASK)<<16));\
	MAC_L4AR3_WR(v);\
} while (0)

#define MAC_L4AR3_L4DP0_RD(data) do {\
	MAC_L4AR3_RD(data);\
	data = ((data >> 16) & MAC_L4AR3_L4DP0_MASK);\
} while (0)

#define MAC_L4AR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x964))

#define MAC_L4AR2_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR2_OFFSET);\
} while (0)

#define MAC_L4AR2_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR2_OFFSET);\
} while (0)

#define MAC_L4AR2_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR2_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR2_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR2_RD(v);\
	v = ((v & MAC_L4AR2_L4SP0_WR_MASK)\
	|((data & MAC_L4AR2_L4SP0_MASK)<<0));\
	MAC_L4AR2_WR(v);\
} while (0)

#define MAC_L4AR2_L4SP0_RD(data) do {\
	MAC_L4AR2_RD(data);\
	data = ((data >> 0) & MAC_L4AR2_L4SP0_MASK);\
} while (0)

#define MAC_L4AR2_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR2_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR2_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR2_RD(v);\
	v = ((v & MAC_L4AR2_L4DP0_WR_MASK)\
	|((data & MAC_L4AR2_L4DP0_MASK)<<16));\
	MAC_L4AR2_WR(v);\
} while (0)

#define MAC_L4AR2_L4DP0_RD(data) do {\
	MAC_L4AR2_RD(data);\
	data = ((data >> 16) & MAC_L4AR2_L4DP0_MASK);\
} while (0)

#define MAC_L4AR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x934))

#define MAC_L4AR1_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR1_OFFSET);\
} while (0)

#define MAC_L4AR1_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR1_OFFSET);\
} while (0)

#define MAC_L4AR1_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR1_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR1_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR1_RD(v);\
	v = ((v & MAC_L4AR1_L4SP0_WR_MASK)\
	|((data & MAC_L4AR1_L4SP0_MASK)<<0));\
	MAC_L4AR1_WR(v);\
} while (0)

#define MAC_L4AR1_L4SP0_RD(data) do {\
	MAC_L4AR1_RD(data);\
	data = ((data >> 0) & MAC_L4AR1_L4SP0_MASK);\
} while (0)

#define MAC_L4AR1_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR1_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR1_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR1_RD(v);\
	v = ((v & MAC_L4AR1_L4DP0_WR_MASK)\
	|((data & MAC_L4AR1_L4DP0_MASK)<<16));\
	MAC_L4AR1_WR(v);\
} while (0)

#define MAC_L4AR1_L4DP0_RD(data) do {\
	MAC_L4AR1_RD(data);\
	data = ((data >> 16) & MAC_L4AR1_L4DP0_MASK);\
} while (0)

#define MAC_L4AR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x904))

#define MAC_L4AR0_WR(data) do {\
	iowrite32(data, (void *)MAC_L4AR0_OFFSET);\
} while (0)

#define MAC_L4AR0_RD(data) do {\
	(data) = ioread32((void *)MAC_L4AR0_OFFSET);\
} while (0)

#define MAC_L4AR0_L4SP0_MASK (ULONG)(0xffff)

#define MAC_L4AR0_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR0_L4SP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR0_RD(v);\
	v = ((v & MAC_L4AR0_L4SP0_WR_MASK)\
	|((data & MAC_L4AR0_L4SP0_MASK)<<0));\
	MAC_L4AR0_WR(v);\
} while (0)

#define MAC_L4AR0_L4SP0_RD(data) do {\
	MAC_L4AR0_RD(data);\
	data = ((data >> 0) & MAC_L4AR0_L4SP0_MASK);\
} while (0)

#define MAC_L4AR0_L4DP0_MASK (ULONG)(0xffff)

#define MAC_L4AR0_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR0_L4DP0_WR(data) do {\
	ULONG v;\
	MAC_L4AR0_RD(v);\
	v = ((v & MAC_L4AR0_L4DP0_WR_MASK)\
	|((data & MAC_L4AR0_L4DP0_MASK)<<16));\
	MAC_L4AR0_WR(v);\
} while (0)

#define MAC_L4AR0_L4DP0_RD(data) do {\
	MAC_L4AR0_RD(data);\
	data = ((data >> 16) & MAC_L4AR0_L4DP0_MASK);\
} while (0)

#define MAC_L3L4CR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa50))

#define MAC_L3L4CR7_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR7_OFFSET);\
} while (0)

#define MAC_L3L4CR7_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR7_OFFSET);\
} while (0)

#define  MAC_L3L4CR7_MASK_1 (ULONG)(0x1)

#define MAC_L3L4CR7_RES_WR_MASK_1 (ULONG)(0xfffffffd)

#define  MAC_L3L4CR7_MASK_17 (ULONG)(0x1)

#define MAC_L3L4CR7_RES_WR_MASK_17 (ULONG)(0xfffdffff)

#define  MAC_L3L4CR7_MASK_22 (ULONG)(0x3ff)

#define MAC_L3L4CR7_RES_WR_MASK_22 (ULONG)(0x3fffff)

#define MAC_L3L4CR7_L3PEN0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR7_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3PEN0_MASK)<<0));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3PEN0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR7_L3PEN0_MASK);\
} while (0)

#define MAC_L3L4CR7_L3SAM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR7_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3SAM0_MASK)<<2));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3SAM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR7_L3SAM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L3SAIM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR7_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3SAIM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR7_L3SAIM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L3DAM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR7_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3DAM0_MASK)<<4));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3DAM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR7_L3DAM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L3DAIM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR7_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3DAIM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR7_L3DAIM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L3HSBM0_MASK (ULONG)(0x1f)

#define MAC_L3L4CR7_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR7_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3HSBM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR7_L3HSBM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L3HDBM0_MASK (ULONG)(0x1f)

#define MAC_L3L4CR7_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR7_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L3HDBM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR7_L3HDBM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L4PEN0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR7_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR7_L4PEN0_MASK)<<16));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L4PEN0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR7_L4PEN0_MASK);\
} while (0)

#define MAC_L3L4CR7_L4SPM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR7_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L4SPM0_MASK)<<18));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L4SPM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR7_L4SPM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L4SPIM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR7_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L4SPIM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR7_L4SPIM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L4DPM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR7_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L4DPM0_MASK)<<20));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L4DPM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR7_L4DPM0_MASK);\
} while (0)

#define MAC_L3L4CR7_L4DPIM0_MASK (ULONG)(0x1)

#define MAC_L3L4CR7_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR7_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR7_RD(v);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR7_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR7_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR7_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR7_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR7_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR7_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR7_WR(v);\
} while (0)

#define MAC_L3L4CR7_L4DPIM0_RD(data) do {\
	MAC_L3L4CR7_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR7_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa20))

#define MAC_L3L4CR6_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR6_OFFSET);\
} while (0)

#define MAC_L3L4CR6_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR6_OFFSET);\
} while (0)

#define  MAC_L3L4CR6_MASK_1 (ULONG)(0x1)

#define MAC_L3L4CR6_RES_WR_MASK_1 (ULONG)(0xfffffffd)

#define  MAC_L3L4CR6_MASK_17 (ULONG)(0x1)

#define MAC_L3L4CR6_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR6_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR6_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR6_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR6_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3PEN0_MASK)<<0));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3PEN0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR6_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR6_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR6_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3SAM0_MASK)<<2));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3SAM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR6_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR6_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3SAIM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR6_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR6_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3DAM0_MASK)<<4));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3DAM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR6_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR6_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3DAIM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR6_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR6_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR6_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3HSBM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR6_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR6_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR6_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L3HDBM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR6_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR6_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR6_L4PEN0_MASK)<<16));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L4PEN0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR6_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR6_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR6_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L4SPM0_MASK)<<18));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L4SPM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR6_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR6_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L4SPIM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR6_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR6_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L4DPM0_MASK)<<20));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L4DPM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR6_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR6_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR6_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR6_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR6_RD(v);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR6_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR6_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR6_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR6_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR6_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR6_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR6_WR(v);\
} while (0)

#define MAC_L3L4CR6_L4DPIM0_RD(data) do {\
	MAC_L3L4CR6_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR6_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9f0))

#define MAC_L3L4CR5_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR5_OFFSET);\
} while (0)

#define MAC_L3L4CR5_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR5_OFFSET);\
} while (0)


#define  MAC_L3L4CR5_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR5_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define  MAC_L3L4CR5_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR5_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR5_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR5_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR5_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR5_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3PEN0_MASK)<<0));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3PEN0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR5_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR5_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR5_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3SAM0_MASK)<<2));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3SAM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR5_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR5_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3SAIM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR5_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR5_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3DAM0_MASK)<<4));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3DAM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR5_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR5_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3DAIM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR5_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR5_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR5_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3HSBM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR5_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR5_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR5_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L3HDBM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR5_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR5_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR5_L4PEN0_MASK)<<16));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L4PEN0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR5_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR5_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR5_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L4SPM0_MASK)<<18));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L4SPM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR5_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR5_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L4SPIM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR5_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR5_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L4DPM0_MASK)<<20));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L4DPM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR5_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR5_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR5_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR5_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR5_RD(v);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR5_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR5_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR5_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR5_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR5_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR5_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR5_WR(v);\
} while (0)

#define MAC_L3L4CR5_L4DPIM0_RD(data) do {\
	MAC_L3L4CR5_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR5_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9c0))

#define MAC_L3L4CR4_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR4_OFFSET);\
} while (0)

#define MAC_L3L4CR4_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR4_OFFSET);\
} while (0)


#define  MAC_L3L4CR4_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR4_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define  MAC_L3L4CR4_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR4_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR4_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR4_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR4_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR4_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3PEN0_MASK)<<0));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3PEN0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR4_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR4_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR4_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3SAM0_MASK)<<2));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3SAM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR4_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR4_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3SAIM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR4_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR4_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3DAM0_MASK)<<4));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3DAM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR4_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR4_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3DAIM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR4_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR4_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR4_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3HSBM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR4_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR4_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR4_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L3HDBM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR4_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR4_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR4_L4PEN0_MASK)<<16));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L4PEN0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR4_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR4_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR4_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L4SPM0_MASK)<<18));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L4SPM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR4_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR4_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L4SPIM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR4_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR4_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L4DPM0_MASK)<<20));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L4DPM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR4_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR4_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR4_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR4_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR4_RD(v);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR4_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR4_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR4_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR4_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR4_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR4_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR4_WR(v);\
} while (0)

#define MAC_L3L4CR4_L4DPIM0_RD(data) do {\
	MAC_L3L4CR4_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR4_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x990))

#define MAC_L3L4CR3_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR3_OFFSET);\
} while (0)

#define MAC_L3L4CR3_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR3_OFFSET);\
} while (0)


#define  MAC_L3L4CR3_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR3_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define  MAC_L3L4CR3_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR3_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR3_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR3_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR3_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR3_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3PEN0_MASK)<<0));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3PEN0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR3_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR3_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR3_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3SAM0_MASK)<<2));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3SAM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR3_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR3_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3SAIM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR3_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR3_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3DAM0_MASK)<<4));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3DAM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR3_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR3_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3DAIM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR3_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR3_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR3_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3HSBM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR3_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR3_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR3_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L3HDBM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR3_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR3_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR3_L4PEN0_MASK)<<16));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L4PEN0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR3_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR3_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR3_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L4SPM0_MASK)<<18));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L4SPM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR3_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR3_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L4SPIM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR3_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR3_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L4DPM0_MASK)<<20));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L4DPM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR3_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR3_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR3_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR3_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR3_RD(v);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR3_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR3_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR3_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR3_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR3_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR3_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR3_WR(v);\
} while (0)

#define MAC_L3L4CR3_L4DPIM0_RD(data) do {\
	MAC_L3L4CR3_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR3_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x960))

#define MAC_L3L4CR2_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR2_OFFSET);\
} while (0)

#define MAC_L3L4CR2_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR2_OFFSET);\
} while (0)


#define  MAC_L3L4CR2_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR2_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define  MAC_L3L4CR2_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR2_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR2_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR2_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR2_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR2_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3PEN0_MASK)<<0));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3PEN0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR2_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR2_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR2_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3SAM0_MASK)<<2));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3SAM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR2_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR2_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3SAIM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR2_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR2_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3DAM0_MASK)<<4));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3DAM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR2_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR2_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3DAIM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR2_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR2_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR2_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3HSBM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR2_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR2_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR2_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L3HDBM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR2_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR2_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR2_L4PEN0_MASK)<<16));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L4PEN0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR2_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR2_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR2_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L4SPM0_MASK)<<18));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L4SPM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR2_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR2_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L4SPIM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR2_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR2_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L4DPM0_MASK)<<20));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L4DPM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR2_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR2_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR2_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR2_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR2_RD(v);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR2_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR2_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR2_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR2_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR2_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR2_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR2_WR(v);\
} while (0)

#define MAC_L3L4CR2_L4DPIM0_RD(data) do {\
	MAC_L3L4CR2_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR2_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x930))

#define MAC_L3L4CR1_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR1_OFFSET);\
} while (0)

#define MAC_L3L4CR1_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR1_OFFSET);\
} while (0)


#define  MAC_L3L4CR1_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR1_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define  MAC_L3L4CR1_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR1_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR1_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR1_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR1_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR1_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3PEN0_MASK)<<0));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3PEN0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR1_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR1_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR1_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3SAM0_MASK)<<2));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3SAM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR1_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR1_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3SAIM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR1_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR1_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3DAM0_MASK)<<4));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3DAM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR1_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR1_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3DAIM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR1_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR1_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR1_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3HSBM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR1_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR1_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR1_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L3HDBM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR1_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR1_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR1_L4PEN0_MASK)<<16));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L4PEN0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR1_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR1_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR1_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L4SPM0_MASK)<<18));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L4SPM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR1_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR1_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L4SPIM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR1_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR1_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L4DPM0_MASK)<<20));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L4DPM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR1_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR1_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR1_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR1_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR1_RD(v);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR1_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR1_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR1_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR1_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR1_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR1_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR1_WR(v);\
} while (0)

#define MAC_L3L4CR1_L4DPIM0_RD(data) do {\
	MAC_L3L4CR1_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR1_L4DPIM0_MASK);\
} while (0)

#define MAC_L3L4CR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x900))

#define MAC_L3L4CR0_WR(data) do {\
	iowrite32(data, (void *)MAC_L3L4CR0_OFFSET);\
} while (0)

#define MAC_L3L4CR0_RD(data) do {\
	(data) = ioread32((void *)MAC_L3L4CR0_OFFSET);\
} while (0)


#define  MAC_L3L4CR0_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR0_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define  MAC_L3L4CR0_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR0_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR0_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR0_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define MAC_L3L4CR0_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR0_L3PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3PEN0_MASK)<<0));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3PEN0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 0) & MAC_L3L4CR0_L3PEN0_MASK);\
} while (0)


#define MAC_L3L4CR0_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR0_L3SAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3SAM0_MASK)<<2));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3SAM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 2) & MAC_L3L4CR0_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR0_L3SAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3SAIM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 3) & MAC_L3L4CR0_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR0_L3DAM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3DAM0_MASK)<<4));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3DAM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 4) & MAC_L3L4CR0_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR0_L3DAIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3DAIM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 5) & MAC_L3L4CR0_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR0_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR0_L3HSBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3HSBM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 6) & MAC_L3L4CR0_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR0_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR0_L3HDBM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L3HDBM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 11) & MAC_L3L4CR0_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR0_L4PEN0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR0_L4PEN0_MASK)<<16));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L4PEN0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 16) & MAC_L3L4CR0_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR0_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR0_L4SPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L4SPM0_MASK)<<18));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L4SPM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 18) & MAC_L3L4CR0_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR0_L4SPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L4SPIM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 19) & MAC_L3L4CR0_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR0_L4DPM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L4DPM0_MASK)<<20));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L4DPM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 20) & MAC_L3L4CR0_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR0_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR0_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR0_L4DPIM0_WR(data) do {\
	ULONG v;\
	MAC_L3L4CR0_RD(v);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR0_MASK_1))<<1);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR0_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR0_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR0_MASK_22))<<22);\
	v = ((v & MAC_L3L4CR0_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR0_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR0_WR(v);\
} while (0)

#define MAC_L3L4CR0_L4DPIM0_RD(data) do {\
	MAC_L3L4CR0_RD(data);\
	data = ((data >> 21) & MAC_L3L4CR0_L4DPIM0_MASK);\
} while (0)

#define MAC_GPIOS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x20c))

#define MAC_GPIOS_WR(data) do {\
	iowrite32(data, (void *)MAC_GPIOS_OFFSET);\
} while (0)

#define MAC_GPIOS_RD(data) do {\
	(data) = ioread32((void *)MAC_GPIOS_OFFSET);\
} while (0)


#define MAC_GPIOS_GPO_MASK (ULONG)(0xffff)


#define MAC_GPIOS_GPO_WR_MASK (ULONG)(0xffff)

#define MAC_GPIOS_GPO_WR(data) do {\
	ULONG v;\
	MAC_GPIOS_RD(v);\
	v = ((v & MAC_GPIOS_GPO_WR_MASK)\
	|((data & MAC_GPIOS_GPO_MASK)<<16));\
	MAC_GPIOS_WR(v);\
} while (0)

#define MAC_GPIOS_GPO_RD(data) do {\
	MAC_GPIOS_RD(data);\
	data = ((data >> 16) & MAC_GPIOS_GPO_MASK);\
} while (0)


#define MAC_GPIOS_GPIS_MASK (ULONG)(0xffff)

#define MAC_GPIOS_GPIS_RD(data) do {\
	MAC_GPIOS_RD(data);\
	data = ((data >> 0) & MAC_GPIOS_GPIS_MASK);\
} while (0)

#define MAC_PCS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xf8))

#define MAC_PCS_WR(data) do {\
	iowrite32(data, (void *)MAC_PCS_OFFSET);\
} while (0)

#define MAC_PCS_RD(data) do {\
	(data) = ioread32((void *)MAC_PCS_OFFSET);\
} while (0)


#define  MAC_PCS_MASK_22 (ULONG)(0x3ff)


#define MAC_PCS_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define  MAC_PCS_MASK_5 (ULONG)(0x7ff)


#define MAC_PCS_RES_WR_MASK_5 (ULONG)(0xffff001f)


#define  MAC_PCS_MASK_3 (ULONG)(0x1)


#define MAC_PCS_RES_WR_MASK_3 (ULONG)(0xfffffff7)


#define MAC_PCS_FALSCARDET_MASK (ULONG)(0x1)


#define MAC_PCS_FALSCARDET_WR_MASK (ULONG)(0xffdfffff)

#define MAC_PCS_FALSCARDET_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_FALSCARDET_WR_MASK)\
	|((data & MAC_PCS_FALSCARDET_MASK)<<21));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_FALSCARDET_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 21) & MAC_PCS_FALSCARDET_MASK);\
} while (0)


#define MAC_PCS_JABTO_MASK (ULONG)(0x1)


#define MAC_PCS_JABTO_WR_MASK (ULONG)(0xffefffff)

#define MAC_PCS_JABTO_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_JABTO_WR_MASK)\
	|((data & MAC_PCS_JABTO_MASK)<<20));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_JABTO_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 20) & MAC_PCS_JABTO_MASK);\
} while (0)


#define MAC_PCS_LNKSTS_MASK (ULONG)(0x1)


#define MAC_PCS_LNKSTS_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_PCS_LNKSTS_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_LNKSTS_WR_MASK)\
	|((data & MAC_PCS_LNKSTS_MASK)<<19));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_LNKSTS_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 19) & MAC_PCS_LNKSTS_MASK);\
} while (0)


#define MAC_PCS_LNKSPEED_MASK (ULONG)(0x3)


#define MAC_PCS_LNKSPEED_WR_MASK (ULONG)(0xfff9ffff)

#define MAC_PCS_LNKSPEED_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_LNKSPEED_WR_MASK)\
	|((data & MAC_PCS_LNKSPEED_MASK)<<17));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_LNKSPEED_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 17) & MAC_PCS_LNKSPEED_MASK);\
} while (0)


#define MAC_PCS_LNKMOD_MASK (ULONG)(0x1)


#define MAC_PCS_LNKMOD_WR_MASK (ULONG)(0xfffeffff)

#define MAC_PCS_LNKMOD_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_LNKMOD_WR_MASK)\
	|((data & MAC_PCS_LNKMOD_MASK)<<16));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_LNKMOD_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 16) & MAC_PCS_LNKMOD_MASK);\
} while (0)


#define MAC_PCS_SMIDRXS_MASK (ULONG)(0x1)


#define MAC_PCS_SMIDRXS_WR_MASK (ULONG)(0xffffffef)

#define MAC_PCS_SMIDRXS_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_SMIDRXS_WR_MASK)\
	|((data & MAC_PCS_SMIDRXS_MASK)<<4));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_SMIDRXS_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 4) & MAC_PCS_SMIDRXS_MASK);\
} while (0)


#define MAC_PCS_SFTERR_MASK (ULONG)(0x1)


#define MAC_PCS_SFTERR_WR_MASK (ULONG)(0xfffffffb)

#define MAC_PCS_SFTERR_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_SFTERR_WR_MASK)\
	|((data & MAC_PCS_SFTERR_MASK)<<2));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_SFTERR_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 2) & MAC_PCS_SFTERR_MASK);\
} while (0)


#define MAC_PCS_LUD_MASK (ULONG)(0x1)


#define MAC_PCS_LUD_WR_MASK (ULONG)(0xfffffffd)

#define MAC_PCS_LUD_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_LUD_WR_MASK)\
	|((data & MAC_PCS_LUD_MASK)<<1));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_LUD_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 1) & MAC_PCS_LUD_MASK);\
} while (0)


#define MAC_PCS_TC_MASK (ULONG)(0x1)


#define MAC_PCS_TC_WR_MASK (ULONG)(0xfffffffe)

#define MAC_PCS_TC_WR(data) do {\
	ULONG v;\
	MAC_PCS_RD(v);\
	v = (v & (MAC_PCS_RES_WR_MASK_22))\
	|(((0) & (MAC_PCS_MASK_22))<<22);\
	v = (v & (MAC_PCS_RES_WR_MASK_5))\
	|(((0) & (MAC_PCS_MASK_5))<<5);\
	v = (v & (MAC_PCS_RES_WR_MASK_3))\
	|(((0) & (MAC_PCS_MASK_3))<<3);\
	v = ((v & MAC_PCS_TC_WR_MASK)\
	|((data & MAC_PCS_TC_MASK)<<0));\
	MAC_PCS_WR(v);\
} while (0)

#define MAC_PCS_TC_RD(data) do {\
	MAC_PCS_RD(data);\
	data = ((data >> 0) & MAC_PCS_TC_MASK);\
} while (0)

#define MAC_TES_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xf4))

#define MAC_TES_RD(data) do {\
	(data) = ioread32((void *)MAC_TES_OFFSET);\
} while (0)


#define MAC_TES_GFD_MASK (ULONG)(0x1)

#define MAC_TES_GFD_RD(data) do {\
	MAC_TES_RD(data);\
	data = ((data >> 15) & MAC_TES_GFD_MASK);\
} while (0)


#define MAC_TES_GHD_MASK (ULONG)(0x1)

#define MAC_TES_GHD_RD(data) do {\
	MAC_TES_RD(data);\
	data = ((data >> 14) & MAC_TES_GHD_MASK);\
} while (0)

#define MAC_AE_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xf0))

#define MAC_AE_RD(data) do {\
	(data) = ioread32((void *)MAC_AE_OFFSET);\
} while (0)


#define MAC_AE_NPA_MASK (ULONG)(0x1)

#define MAC_AE_NPA_RD(data) do {\
	MAC_AE_RD(data);\
	data = ((data >> 2) & MAC_AE_NPA_MASK);\
} while (0)


#define MAC_AE_NPR_MASK (ULONG)(0x1)

#define MAC_AE_NPR_RD(data) do {\
	MAC_AE_RD(data);\
	data = ((data >> 1) & MAC_AE_NPR_MASK);\
} while (0)

#define MAC_ALPA_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xec))

#define MAC_ALPA_RD(data) do {\
	(data) = ioread32((void *)MAC_ALPA_OFFSET);\
} while (0)


#define MAC_ALPA_NP_MASK (ULONG)(0x1)

#define MAC_ALPA_NP_RD(data) do {\
	MAC_ALPA_RD(data);\
	data = ((data >> 15) & MAC_ALPA_NP_MASK);\
} while (0)


#define MAC_ALPA_ACK_MASK (ULONG)(0x1)

#define MAC_ALPA_ACK_RD(data) do {\
	MAC_ALPA_RD(data);\
	data = ((data >> 14) & MAC_ALPA_ACK_MASK);\
} while (0)


#define MAC_ALPA_RFE_MASK (ULONG)(0x3)

#define MAC_ALPA_RFE_RD(data) do {\
	MAC_ALPA_RD(data);\
	data = ((data >> 12) & MAC_ALPA_RFE_MASK);\
} while (0)


#define MAC_ALPA_PSE_MASK (ULONG)(0x3)

#define MAC_ALPA_PSE_RD(data) do {\
	MAC_ALPA_RD(data);\
	data = ((data >> 7) & MAC_ALPA_PSE_MASK);\
} while (0)


#define MAC_ALPA_HD_MASK (ULONG)(0x1)

#define MAC_ALPA_HD_RD(data) do {\
	MAC_ALPA_RD(data);\
	data = ((data >> 6) & MAC_ALPA_HD_MASK);\
} while (0)


#define MAC_ALPA_FD_MASK (ULONG)(0x1)

#define MAC_ALPA_FD_RD(data) do {\
	MAC_ALPA_RD(data);\
	data = ((data >> 5) & MAC_ALPA_FD_MASK);\
} while (0)

#define MAC_AAD_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe8))

#define MAC_AAD_WR(data) do {\
	iowrite32(data, (void *)MAC_AAD_OFFSET);\
} while (0)

#define MAC_AAD_RD(data) do {\
	(data) = ioread32((void *)MAC_AAD_OFFSET);\
} while (0)


#define  MAC_AAD_MASK_16 (ULONG)(0xffff)


#define MAC_AAD_RES_WR_MASK_16 (ULONG)(0xffff)


#define  MAC_AAD_MASK_14 (ULONG)(0x1)


#define MAC_AAD_RES_WR_MASK_14 (ULONG)(0xffffbfff)


#define  MAC_AAD_MASK_9 (ULONG)(0x7)


#define MAC_AAD_RES_WR_MASK_9 (ULONG)(0xfffff1ff)


#define  MAC_AAD_MASK_0 (ULONG)(0x1f)


#define MAC_AAD_RES_WR_MASK_0 (ULONG)(0xffffffe0)


#define MAC_AAD_NPS_MASK (ULONG)(0x1)


#define MAC_AAD_NPS_WR_MASK (ULONG)(0xffff7fff)

#define MAC_AAD_NPS_WR(data) do {\
	ULONG v;\
	MAC_AAD_RD(v);\
	v = (v & (MAC_AAD_RES_WR_MASK_16))\
	|(((0) & (MAC_AAD_MASK_16))<<16);\
	v = (v & (MAC_AAD_RES_WR_MASK_14))\
	|(((0) & (MAC_AAD_MASK_14))<<14);\
	v = (v & (MAC_AAD_RES_WR_MASK_9))\
	|(((0) & (MAC_AAD_MASK_9))<<9);\
	v = (v & (MAC_AAD_RES_WR_MASK_0))\
	|(((0) & (MAC_AAD_MASK_0))<<0);\
	v = ((v & MAC_AAD_NPS_WR_MASK)\
	|((data & MAC_AAD_NPS_MASK)<<15));\
	MAC_AAD_WR(v);\
} while (0)

#define MAC_AAD_NPS_RD(data) do {\
	MAC_AAD_RD(data);\
	data = ((data >> 15) & MAC_AAD_NPS_MASK);\
} while (0)


#define MAC_AAD_RFE_MASK (ULONG)(0x3)


#define MAC_AAD_RFE_WR_MASK (ULONG)(0xffffcfff)

#define MAC_AAD_RFE_WR(data) do {\
	ULONG v;\
	MAC_AAD_RD(v);\
	v = (v & (MAC_AAD_RES_WR_MASK_16))\
	|(((0) & (MAC_AAD_MASK_16))<<16);\
	v = (v & (MAC_AAD_RES_WR_MASK_14))\
	|(((0) & (MAC_AAD_MASK_14))<<14);\
	v = (v & (MAC_AAD_RES_WR_MASK_9))\
	|(((0) & (MAC_AAD_MASK_9))<<9);\
	v = (v & (MAC_AAD_RES_WR_MASK_0))\
	|(((0) & (MAC_AAD_MASK_0))<<0);\
	v = ((v & MAC_AAD_RFE_WR_MASK)\
	|((data & MAC_AAD_RFE_MASK)<<12));\
	MAC_AAD_WR(v);\
} while (0)

#define MAC_AAD_RFE_RD(data) do {\
	MAC_AAD_RD(data);\
	data = ((data >> 12) & MAC_AAD_RFE_MASK);\
} while (0)


#define MAC_AAD_PSE_MASK (ULONG)(0x3)


#define MAC_AAD_PSE_WR_MASK (ULONG)(0xfffffe7f)

#define MAC_AAD_PSE_WR(data) do {\
	ULONG v;\
	MAC_AAD_RD(v);\
	v = (v & (MAC_AAD_RES_WR_MASK_16))\
	|(((0) & (MAC_AAD_MASK_16))<<16);\
	v = (v & (MAC_AAD_RES_WR_MASK_14))\
	|(((0) & (MAC_AAD_MASK_14))<<14);\
	v = (v & (MAC_AAD_RES_WR_MASK_9))\
	|(((0) & (MAC_AAD_MASK_9))<<9);\
	v = (v & (MAC_AAD_RES_WR_MASK_0))\
	|(((0) & (MAC_AAD_MASK_0))<<0);\
	v = ((v & MAC_AAD_PSE_WR_MASK)\
	|((data & MAC_AAD_PSE_MASK)<<7));\
	MAC_AAD_WR(v);\
} while (0)

#define MAC_AAD_PSE_RD(data) do {\
	MAC_AAD_RD(data);\
	data = ((data >> 7) & MAC_AAD_PSE_MASK);\
} while (0)


#define MAC_AAD_HD_MASK (ULONG)(0x1)


#define MAC_AAD_HD_WR_MASK (ULONG)(0xffffffbf)

#define MAC_AAD_HD_WR(data) do {\
	ULONG v;\
	MAC_AAD_RD(v);\
	v = (v & (MAC_AAD_RES_WR_MASK_16))\
	|(((0) & (MAC_AAD_MASK_16))<<16);\
	v = (v & (MAC_AAD_RES_WR_MASK_14))\
	|(((0) & (MAC_AAD_MASK_14))<<14);\
	v = (v & (MAC_AAD_RES_WR_MASK_9))\
	|(((0) & (MAC_AAD_MASK_9))<<9);\
	v = (v & (MAC_AAD_RES_WR_MASK_0))\
	|(((0) & (MAC_AAD_MASK_0))<<0);\
	v = ((v & MAC_AAD_HD_WR_MASK)\
	|((data & MAC_AAD_HD_MASK)<<6));\
	MAC_AAD_WR(v);\
} while (0)

#define MAC_AAD_HD_RD(data) do {\
	MAC_AAD_RD(data);\
	data = ((data >> 6) & MAC_AAD_HD_MASK);\
} while (0)


#define MAC_AAD_FD_MASK (ULONG)(0x1)


#define MAC_AAD_FD_WR_MASK (ULONG)(0xffffffdf)

#define MAC_AAD_FD_WR(data) do {\
	ULONG v;\
	MAC_AAD_RD(v);\
	v = (v & (MAC_AAD_RES_WR_MASK_16))\
	|(((0) & (MAC_AAD_MASK_16))<<16);\
	v = (v & (MAC_AAD_RES_WR_MASK_14))\
	|(((0) & (MAC_AAD_MASK_14))<<14);\
	v = (v & (MAC_AAD_RES_WR_MASK_9))\
	|(((0) & (MAC_AAD_MASK_9))<<9);\
	v = (v & (MAC_AAD_RES_WR_MASK_0))\
	|(((0) & (MAC_AAD_MASK_0))<<0);\
	v = ((v & MAC_AAD_FD_WR_MASK)\
	|((data & MAC_AAD_FD_MASK)<<5));\
	MAC_AAD_WR(v);\
} while (0)

#define MAC_AAD_FD_RD(data) do {\
	MAC_AAD_RD(data);\
	data = ((data >> 5) & MAC_AAD_FD_MASK);\
} while (0)

#define MAC_ANS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe4))

#define MAC_ANS_RD(data) do {\
	(data) = ioread32((void *)MAC_ANS_OFFSET);\
} while (0)


#define MAC_ANS_ES_MASK (ULONG)(0x1)

#define MAC_ANS_ES_RD(data) do {\
	MAC_ANS_RD(data);\
	data = ((data >> 8) & MAC_ANS_ES_MASK);\
} while (0)


#define MAC_ANS_ANC_MASK (ULONG)(0x1)

#define MAC_ANS_ANC_RD(data) do {\
	MAC_ANS_RD(data);\
	data = ((data >> 5) & MAC_ANS_ANC_MASK);\
} while (0)


#define MAC_ANS_ANA_MASK (ULONG)(0x1)

#define MAC_ANS_ANA_RD(data) do {\
	MAC_ANS_RD(data);\
	data = ((data >> 3) & MAC_ANS_ANA_MASK);\
} while (0)


#define MAC_ANS_LS_MASK (ULONG)(0x1)

#define MAC_ANS_LS_RD(data) do {\
	MAC_ANS_RD(data);\
	data = ((data >> 2) & MAC_ANS_LS_MASK);\
} while (0)

#define MAC_ANC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe0))

#define MAC_ANC_WR(data) do {\
	iowrite32(data, (void *)MAC_ANC_OFFSET);\
} while (0)

#define MAC_ANC_RD(data) do {\
	(data) = ioread32((void *)MAC_ANC_OFFSET);\
} while (0)


#define  MAC_ANC_MASK_19 (ULONG)(0x1fff)


#define MAC_ANC_RES_WR_MASK_19 (ULONG)(0x7ffff)


#define  MAC_ANC_MASK_15 (ULONG)(0x1)


#define MAC_ANC_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  MAC_ANC_MASK_13 (ULONG)(0x1)


#define MAC_ANC_RES_WR_MASK_13 (ULONG)(0xffffdfff)


#define  MAC_ANC_MASK_10 (ULONG)(0x3)


#define MAC_ANC_RES_WR_MASK_10 (ULONG)(0xfffff3ff)


#define  MAC_ANC_MASK_0 (ULONG)(0x1ff)


#define MAC_ANC_RES_WR_MASK_0 (ULONG)(0xfffffe00)


#define MAC_ANC_SGMRAL_MASK (ULONG)(0x1)


#define MAC_ANC_SGMRAL_WR_MASK (ULONG)(0xfffbffff)

#define MAC_ANC_SGMRAL_WR(data) do {\
	ULONG v;\
	MAC_ANC_RD(v);\
	v = (v & (MAC_ANC_RES_WR_MASK_19))\
	|(((0) & (MAC_ANC_MASK_19))<<19);\
	v = (v & (MAC_ANC_RES_WR_MASK_15))\
	|(((0) & (MAC_ANC_MASK_15))<<15);\
	v = (v & (MAC_ANC_RES_WR_MASK_13))\
	|(((0) & (MAC_ANC_MASK_13))<<13);\
	v = (v & (MAC_ANC_RES_WR_MASK_10))\
	|(((0) & (MAC_ANC_MASK_10))<<10);\
	v = (v & (MAC_ANC_RES_WR_MASK_0))\
	|(((0) & (MAC_ANC_MASK_0))<<0);\
	v = ((v & MAC_ANC_SGMRAL_WR_MASK)\
	|((data & MAC_ANC_SGMRAL_MASK)<<18));\
	MAC_ANC_WR(v);\
} while (0)

#define MAC_ANC_SGMRAL_RD(data) do {\
	MAC_ANC_RD(data);\
	data = ((data >> 18) & MAC_ANC_SGMRAL_MASK);\
} while (0)


#define MAC_ANC_LR_MASK (ULONG)(0x1)


#define MAC_ANC_LR_WR_MASK (ULONG)(0xfffdffff)

#define MAC_ANC_LR_WR(data) do {\
	ULONG v;\
	MAC_ANC_RD(v);\
	v = (v & (MAC_ANC_RES_WR_MASK_19))\
	|(((0) & (MAC_ANC_MASK_19))<<19);\
	v = (v & (MAC_ANC_RES_WR_MASK_15))\
	|(((0) & (MAC_ANC_MASK_15))<<15);\
	v = (v & (MAC_ANC_RES_WR_MASK_13))\
	|(((0) & (MAC_ANC_MASK_13))<<13);\
	v = (v & (MAC_ANC_RES_WR_MASK_10))\
	|(((0) & (MAC_ANC_MASK_10))<<10);\
	v = (v & (MAC_ANC_RES_WR_MASK_0))\
	|(((0) & (MAC_ANC_MASK_0))<<0);\
	v = ((v & MAC_ANC_LR_WR_MASK)\
	|((data & MAC_ANC_LR_MASK)<<17));\
	MAC_ANC_WR(v);\
} while (0)

#define MAC_ANC_LR_RD(data) do {\
	MAC_ANC_RD(data);\
	data = ((data >> 17) & MAC_ANC_LR_MASK);\
} while (0)


#define MAC_ANC_ECD_MASK (ULONG)(0x1)


#define MAC_ANC_ECD_WR_MASK (ULONG)(0xfffeffff)

#define MAC_ANC_ECD_WR(data) do {\
	ULONG v;\
	MAC_ANC_RD(v);\
	v = (v & (MAC_ANC_RES_WR_MASK_19))\
	|(((0) & (MAC_ANC_MASK_19))<<19);\
	v = (v & (MAC_ANC_RES_WR_MASK_15))\
	|(((0) & (MAC_ANC_MASK_15))<<15);\
	v = (v & (MAC_ANC_RES_WR_MASK_13))\
	|(((0) & (MAC_ANC_MASK_13))<<13);\
	v = (v & (MAC_ANC_RES_WR_MASK_10))\
	|(((0) & (MAC_ANC_MASK_10))<<10);\
	v = (v & (MAC_ANC_RES_WR_MASK_0))\
	|(((0) & (MAC_ANC_MASK_0))<<0);\
	v = ((v & MAC_ANC_ECD_WR_MASK)\
	|((data & MAC_ANC_ECD_MASK)<<16));\
	MAC_ANC_WR(v);\
} while (0)

#define MAC_ANC_ECD_RD(data) do {\
	MAC_ANC_RD(data);\
	data = ((data >> 16) & MAC_ANC_ECD_MASK);\
} while (0)


#define MAC_ANC_ELE_MASK (ULONG)(0x1)


#define MAC_ANC_ELE_WR_MASK (ULONG)(0xffffbfff)

#define MAC_ANC_ELE_WR(data) do {\
	ULONG v;\
	MAC_ANC_RD(v);\
	v = (v & (MAC_ANC_RES_WR_MASK_19))\
	|(((0) & (MAC_ANC_MASK_19))<<19);\
	v = (v & (MAC_ANC_RES_WR_MASK_15))\
	|(((0) & (MAC_ANC_MASK_15))<<15);\
	v = (v & (MAC_ANC_RES_WR_MASK_13))\
	|(((0) & (MAC_ANC_MASK_13))<<13);\
	v = (v & (MAC_ANC_RES_WR_MASK_10))\
	|(((0) & (MAC_ANC_MASK_10))<<10);\
	v = (v & (MAC_ANC_RES_WR_MASK_0))\
	|(((0) & (MAC_ANC_MASK_0))<<0);\
	v = ((v & MAC_ANC_ELE_WR_MASK)\
	|((data & MAC_ANC_ELE_MASK)<<14));\
	MAC_ANC_WR(v);\
} while (0)

#define MAC_ANC_ELE_RD(data) do {\
	MAC_ANC_RD(data);\
	data = ((data >> 14) & MAC_ANC_ELE_MASK);\
} while (0)


#define MAC_ANC_ANE_MASK (ULONG)(0x1)


#define MAC_ANC_ANE_WR_MASK (ULONG)(0xffffefff)

#define MAC_ANC_ANE_WR(data) do {\
	ULONG v;\
	MAC_ANC_RD(v);\
	v = (v & (MAC_ANC_RES_WR_MASK_19))\
	|(((0) & (MAC_ANC_MASK_19))<<19);\
	v = (v & (MAC_ANC_RES_WR_MASK_15))\
	|(((0) & (MAC_ANC_MASK_15))<<15);\
	v = (v & (MAC_ANC_RES_WR_MASK_13))\
	|(((0) & (MAC_ANC_MASK_13))<<13);\
	v = (v & (MAC_ANC_RES_WR_MASK_10))\
	|(((0) & (MAC_ANC_MASK_10))<<10);\
	v = (v & (MAC_ANC_RES_WR_MASK_0))\
	|(((0) & (MAC_ANC_MASK_0))<<0);\
	v = ((v & MAC_ANC_ANE_WR_MASK)\
	|((data & MAC_ANC_ANE_MASK)<<12));\
	MAC_ANC_WR(v);\
} while (0)

#define MAC_ANC_ANE_RD(data) do {\
	MAC_ANC_RD(data);\
	data = ((data >> 12) & MAC_ANC_ANE_MASK);\
} while (0)


#define MAC_ANC_RAN_MASK (ULONG)(0x1)


#define MAC_ANC_RAN_WR_MASK (ULONG)(0xfffffdff)

#define MAC_ANC_RAN_WR(data) do {\
	ULONG v;\
	MAC_ANC_RD(v);\
	v = (v & (MAC_ANC_RES_WR_MASK_19))\
	|(((0) & (MAC_ANC_MASK_19))<<19);\
	v = (v & (MAC_ANC_RES_WR_MASK_15))\
	|(((0) & (MAC_ANC_MASK_15))<<15);\
	v = (v & (MAC_ANC_RES_WR_MASK_13))\
	|(((0) & (MAC_ANC_MASK_13))<<13);\
	v = (v & (MAC_ANC_RES_WR_MASK_10))\
	|(((0) & (MAC_ANC_MASK_10))<<10);\
	v = (v & (MAC_ANC_RES_WR_MASK_0))\
	|(((0) & (MAC_ANC_MASK_0))<<0);\
	v = ((v & MAC_ANC_RAN_WR_MASK)\
	|((data & MAC_ANC_RAN_MASK)<<9));\
	MAC_ANC_WR(v);\
} while (0)

#define MAC_ANC_RAN_RD(data) do {\
	MAC_ANC_RD(data);\
	data = ((data >> 9) & MAC_ANC_RAN_MASK);\
} while (0)

#define MAC_1US_TIC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdc))

#define MAC_1US_TIC_WR(data) do {\
	iowrite32(data, (void *)MAC_1US_TIC_OFFSET);\
} while (0)

#define MAC_1US_TIC_RD(data) do {\
	(data) = ioread32((void *)MAC_1US_TIC_OFFSET);\
} while (0)

#define MAC_LPC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd4))

#define MAC_LPC_WR(data) do {\
	iowrite32(data, (void *)MAC_LPC_OFFSET);\
} while (0)

#define MAC_LPC_RD(data) do {\
	(data) = ioread32((void *)MAC_LPC_OFFSET);\
} while (0)


#define  MAC_LPC_MASK_26 (ULONG)(0x3f)


#define MAC_LPC_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MAC_LPC_TLPIEX_MASK (ULONG)(0x3ff)


#define MAC_LPC_TLPIEX_WR_MASK (ULONG)(0xfc00ffff)

#define MAC_LPC_TLPIEX_WR(data) do {\
	ULONG v;\
	MAC_LPC_RD(v);\
	v = (v & (MAC_LPC_RES_WR_MASK_26))\
	|(((0) & (MAC_LPC_MASK_26))<<26);\
	v = ((v & MAC_LPC_TLPIEX_WR_MASK)\
	|((data & MAC_LPC_TLPIEX_MASK)<<16));\
	MAC_LPC_WR(v);\
} while (0)

#define MAC_LPC_TLPIEX_RD(data) do {\
	MAC_LPC_RD(data);\
	data = ((data >> 16) & MAC_LPC_TLPIEX_MASK);\
} while (0)


#define MAC_LPC_TWT_MASK (ULONG)(0xffff)


#define MAC_LPC_TWT_WR_MASK (ULONG)(0xffff0000)

#define MAC_LPC_TWT_WR(data) do {\
	ULONG v;\
	MAC_LPC_RD(v);\
	v = (v & (MAC_LPC_RES_WR_MASK_26))\
	|(((0) & (MAC_LPC_MASK_26))<<26);\
	v = ((v & MAC_LPC_TWT_WR_MASK)\
	|((data & MAC_LPC_TWT_MASK)<<0));\
	MAC_LPC_WR(v);\
} while (0)

#define MAC_LPC_TWT_RD(data) do {\
	MAC_LPC_RD(data);\
	data = ((data >> 0) & MAC_LPC_TWT_MASK);\
} while (0)

#define MAC_LPS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd0))

#define MAC_LPS_WR(data) do {\
	iowrite32(data, (void *)MAC_LPS_OFFSET);\
} while (0)

#define MAC_LPS_RD(data) do {\
	(data) = ioread32((void *)MAC_LPS_OFFSET);\
} while (0)


#define  MAC_LPS_MASK_20 (ULONG)(0xfff)


#define MAC_LPS_RES_WR_MASK_20 (ULONG)(0xfffff)


#define  MAC_LPS_MASK_10 (ULONG)(0x3f)


#define MAC_LPS_RES_WR_MASK_10 (ULONG)(0xffff03ff)


#define  MAC_LPS_MASK_4 (ULONG)(0xf)


#define MAC_LPS_RES_WR_MASK_4 (ULONG)(0xffffff0f)


#define MAC_LPS_LPITXA_MASK (ULONG)(0x1)


#define MAC_LPS_LPITXA_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_LPS_LPITXA_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_LPITXA_WR_MASK)\
	|((data & MAC_LPS_LPITXA_MASK)<<19));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_LPITXA_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 19) & MAC_LPS_LPITXA_MASK);\
} while (0)


#define MAC_LPS_PLSEN_MASK (ULONG)(0x1)


#define MAC_LPS_PLSEN_WR_MASK (ULONG)(0xfffbffff)

#define MAC_LPS_PLSEN_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_PLSEN_WR_MASK)\
	|((data & MAC_LPS_PLSEN_MASK)<<18));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_PLSEN_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 18) & MAC_LPS_PLSEN_MASK);\
} while (0)


#define MAC_LPS_PLS_MASK (ULONG)(0x1)


#define MAC_LPS_PLS_WR_MASK (ULONG)(0xfffdffff)

#define MAC_LPS_PLS_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_PLS_WR_MASK)\
	|((data & MAC_LPS_PLS_MASK)<<17));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_PLS_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 17) & MAC_LPS_PLS_MASK);\
} while (0)


#define MAC_LPS_LPIEN_MASK (ULONG)(0x1)


#define MAC_LPS_LPIEN_WR_MASK (ULONG)(0xfffeffff)

#define MAC_LPS_LPIEN_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_LPIEN_WR_MASK)\
	|((data & MAC_LPS_LPIEN_MASK)<<16));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_LPIEN_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 16) & MAC_LPS_LPIEN_MASK);\
} while (0)


#define MAC_LPS_RLPIST_MASK (ULONG)(0x1)

#define MAC_LPS_RLPIST_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 9) & MAC_LPS_RLPIST_MASK);\
} while (0)


#define MAC_LPS_TLPIST_MASK (ULONG)(0x1)

#define MAC_LPS_TLPIST_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 8) & MAC_LPS_TLPIST_MASK);\
} while (0)


#define MAC_LPS_RLPIEX_MASK (ULONG)(0x1)


#define MAC_LPS_RLPIEX_WR_MASK (ULONG)(0xfffffff7)

#define MAC_LPS_RLPIEX_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_RLPIEX_WR_MASK)\
	|((data & MAC_LPS_RLPIEX_MASK)<<3));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_RLPIEX_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 3) & MAC_LPS_RLPIEX_MASK);\
} while (0)


#define MAC_LPS_RLPIEN_MASK (ULONG)(0x1)


#define MAC_LPS_RLPIEN_WR_MASK (ULONG)(0xfffffffb)

#define MAC_LPS_RLPIEN_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_RLPIEN_WR_MASK)\
	|((data & MAC_LPS_RLPIEN_MASK)<<2));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_RLPIEN_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 2) & MAC_LPS_RLPIEN_MASK);\
} while (0)


#define MAC_LPS_TLPIEX_MASK (ULONG)(0x1)


#define MAC_LPS_TLPIEX_WR_MASK (ULONG)(0xfffffffd)

#define MAC_LPS_TLPIEX_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_TLPIEX_WR_MASK)\
	|((data & MAC_LPS_TLPIEX_MASK)<<1));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_TLPIEX_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 1) & MAC_LPS_TLPIEX_MASK);\
} while (0)


#define MAC_LPS_TLPIEN_MASK (ULONG)(0x1)


#define MAC_LPS_TLPIEN_WR_MASK (ULONG)(0xfffffffe)

#define MAC_LPS_TLPIEN_WR(data) do {\
	ULONG v;\
	MAC_LPS_RD(v);\
	v = (v & (MAC_LPS_RES_WR_MASK_20))\
	|(((0) & (MAC_LPS_MASK_20))<<20);\
	v = (v & (MAC_LPS_RES_WR_MASK_10))\
	|(((0) & (MAC_LPS_MASK_10))<<10);\
	v = (v & (MAC_LPS_RES_WR_MASK_4))\
	|(((0) & (MAC_LPS_MASK_4))<<4);\
	v = ((v & MAC_LPS_TLPIEN_WR_MASK)\
	|((data & MAC_LPS_TLPIEN_MASK)<<0));\
	MAC_LPS_WR(v);\
} while (0)

#define MAC_LPS_TLPIEN_RD(data) do {\
	MAC_LPS_RD(data);\
	data = ((data >> 0) & MAC_LPS_TLPIEN_MASK);\
} while (0)

#define MAC_PPS_WIDTH3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xbbc))

#define MAC_PPS_WIDTH3_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_WIDTH3_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH3_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_WIDTH3_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH3_PPSWIDTH0_WR(data) do {\
	MAC_PPS_WIDTH3_WR(data);\
} while (0)

#define MAC_PPS_WIDTH3_PPSWIDTH0_RD(data) do {\
	MAC_PPS_WIDTH3_RD(data);\
} while (0)

#define MAC_PPS_WIDTH2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xbac))

#define MAC_PPS_WIDTH2_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_WIDTH2_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH2_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_WIDTH2_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH2_PPSWIDTH0_WR(data) do {\
	MAC_PPS_WIDTH2_WR(data);\
} while (0)

#define MAC_PPS_WIDTH2_PPSWIDTH0_RD(data) do {\
	MAC_PPS_WIDTH2_RD(data);\
} while (0)

#define MAC_PPS_WIDTH1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb9c))

#define MAC_PPS_WIDTH1_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_WIDTH1_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH1_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_WIDTH1_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH1_PPSWIDTH0_WR(data) do {\
	MAC_PPS_WIDTH1_WR(data);\
} while (0)

#define MAC_PPS_WIDTH1_PPSWIDTH0_RD(data) do {\
	MAC_PPS_WIDTH1_RD(data);\
} while (0)

#define MAC_PPS_WIDTH0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb8c))

#define MAC_PPS_WIDTH0_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_WIDTH0_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH0_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_WIDTH0_OFFSET);\
} while (0)

#define MAC_PPS_WIDTH0_PPSWIDTH0_WR(data) do {\
	MAC_PPS_WIDTH0_WR(data);\
} while (0)

#define MAC_PPS_WIDTH0_PPSWIDTH0_RD(data) do {\
	MAC_PPS_WIDTH0_RD(data);\
} while (0)

#define MAC_PPS_INTVAL3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xbb8))

#define MAC_PPS_INTVAL3_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_INTVAL3_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL3_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_INTVAL3_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL3_PPSINT0_WR(data) do {\
	MAC_PPS_INTVAL3_WR(data);\
} while (0)

#define MAC_PPS_INTVAL3_PPSINT0_RD(data) do {\
	MAC_PPS_INTVAL3_RD(data);\
} while (0)

#define MAC_PPS_INTVAL2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xba8))

#define MAC_PPS_INTVAL2_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_INTVAL2_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL2_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_INTVAL2_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL2_PPSINT0_WR(data) do {\
	MAC_PPS_INTVAL2_WR(data);\
} while (0)

#define MAC_PPS_INTVAL2_PPSINT0_RD(data) do {\
	MAC_PPS_INTVAL2_RD(data);\
} while (0)

#define MAC_PPS_INTVAL1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb98))

#define MAC_PPS_INTVAL1_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_INTVAL1_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL1_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_INTVAL1_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL1_PPSINT0_WR(data) do {\
	MAC_PPS_INTVAL1_WR(data);\
} while (0)

#define MAC_PPS_INTVAL1_PPSINT0_RD(data) do {\
	MAC_PPS_INTVAL1_RD(data);\
} while (0)

#define MAC_PPS_INTVAL0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb88))

#define MAC_PPS_INTVAL0_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_INTVAL0_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL0_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_INTVAL0_OFFSET);\
} while (0)

#define MAC_PPS_INTVAL0_PPSINT0_WR(data) do {\
	MAC_PPS_INTVAL0_WR(data);\
} while (0)

#define MAC_PPS_INTVAL0_PPSINT0_RD(data) do {\
	MAC_PPS_INTVAL0_RD(data);\
} while (0)

#define MAC_PPS_TTNS3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xbb4))

#define MAC_PPS_TTNS3_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTNS3_OFFSET);\
} while (0)

#define MAC_PPS_TTNS3_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTNS3_OFFSET);\
} while (0)


#define MAC_PPS_TTNS3_TTSL0_MASK (ULONG)(0x7fffffff)


#define MAC_PPS_TTNS3_TTSL0_WR_MASK (ULONG)(0x80000000)

#define MAC_PPS_TTNS3_TTSL0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS3_RD(v);\
	v = ((v & MAC_PPS_TTNS3_TTSL0_WR_MASK)\
	|((data & MAC_PPS_TTNS3_TTSL0_MASK)<<0));\
	MAC_PPS_TTNS3_WR(v);\
} while (0)

#define MAC_PPS_TTNS3_TTSL0_RD(data) do {\
	MAC_PPS_TTNS3_RD(data);\
	data = ((data >> 0) & MAC_PPS_TTNS3_TTSL0_MASK);\
} while (0)


#define MAC_PPS_TTNS3_TRGTBUSY0_MASK (ULONG)(0x1)


#define MAC_PPS_TTNS3_TRGTBUSY0_WR_MASK (ULONG)(0x7fffffff)

#define MAC_PPS_TTNS3_TRGTBUSY0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS3_RD(v);\
	v = ((v & MAC_PPS_TTNS3_TRGTBUSY0_WR_MASK)\
	|((data & MAC_PPS_TTNS3_TRGTBUSY0_MASK)<<31));\
	MAC_PPS_TTNS3_WR(v);\
} while (0)

#define MAC_PPS_TTNS3_TRGTBUSY0_RD(data) do {\
	MAC_PPS_TTNS3_RD(data);\
	data = ((data >> 31) & MAC_PPS_TTNS3_TRGTBUSY0_MASK);\
} while (0)

#define MAC_PPS_TTNS2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xba4))

#define MAC_PPS_TTNS2_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTNS2_OFFSET);\
} while (0)

#define MAC_PPS_TTNS2_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTNS2_OFFSET);\
} while (0)


#define MAC_PPS_TTNS2_TTSL0_MASK (ULONG)(0x7fffffff)


#define MAC_PPS_TTNS2_TTSL0_WR_MASK (ULONG)(0x80000000)

#define MAC_PPS_TTNS2_TTSL0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS2_RD(v);\
	v = ((v & MAC_PPS_TTNS2_TTSL0_WR_MASK)\
	|((data & MAC_PPS_TTNS2_TTSL0_MASK)<<0));\
	MAC_PPS_TTNS2_WR(v);\
} while (0)

#define MAC_PPS_TTNS2_TTSL0_RD(data) do {\
	MAC_PPS_TTNS2_RD(data);\
	data = ((data >> 0) & MAC_PPS_TTNS2_TTSL0_MASK);\
} while (0)


#define MAC_PPS_TTNS2_TRGTBUSY0_MASK (ULONG)(0x1)


#define MAC_PPS_TTNS2_TRGTBUSY0_WR_MASK (ULONG)(0x7fffffff)

#define MAC_PPS_TTNS2_TRGTBUSY0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS2_RD(v);\
	v = ((v & MAC_PPS_TTNS2_TRGTBUSY0_WR_MASK)\
	|((data & MAC_PPS_TTNS2_TRGTBUSY0_MASK)<<31));\
	MAC_PPS_TTNS2_WR(v);\
} while (0)

#define MAC_PPS_TTNS2_TRGTBUSY0_RD(data) do {\
	MAC_PPS_TTNS2_RD(data);\
	data = ((data >> 31) & MAC_PPS_TTNS2_TRGTBUSY0_MASK);\
} while (0)

#define MAC_LMIR_OFFSET ((volatile unsigned int *)(BASE_ADDRESS + 0xbd0))

#define MAC_LMIR_WR(data) do {\
	iowrite32(data, (void *)MAC_LMIR_OFFSET);\
} while (0)

#define MAC_LMIR_RD(data) do {\
	(data) = ioread32((void *)MAC_LMIR_OFFSET);\
} while (0)

#define MAC_SPI2R_OFFSET ((volatile unsigned int *)(BASE_ADDRESS + 0xbcc))

#define MAC_SPI2R_WR(data) do {\
	iowrite32(data, (void *)MAC_SPI2R_OFFSET);\
} while (0)

#define MAC_SPI2R_RD(data) do {\
	(data) = ioread32((void *)MAC_SPI2R_OFFSET);\
} while (0)


#define  MAC_SPI2R_MASK_16 (unsigned int)(0xffff)


#define MAC_SPI2R_RES_WR_MASK_16 (unsigned int)(0xffff)


#define MAC_SPI2R_SPIO_MASK (unsigned int)(0xffff)


#define MAC_SPI2R_SPIO_WR_MASK (unsigned int)(0xffff0000)

#define MAC_SPI2R_SPIO_WR(data) do {\
	unsigned int v = 0; \
	v = (v & (MAC_SPI2R_RES_WR_MASK_16))\
	|(((0) & (MAC_SPI2R_MASK_16))<<16);\
	(v) = ((v & MAC_SPI2R_SPIO_WR_MASK)\
	|((data & MAC_SPI2R_SPIO_MASK)<<0));\
	MAC_SPI2R_WR(v);\
} while (0)

#define MAC_SPI2R_SPIO_RD(data) do {\
	MAC_SPI2R_RD(data);\
	data = ((data >> 0) & MAC_SPI2R_SPIO_MASK);\
} while (0)

#define MAC_SPI1R_OFFSET ((volatile unsigned int *)(BASE_ADDRESS + 0xbc8))

#define MAC_SPI1R_WR(data) do {\
	iowrite32(data, (void *)MAC_SPI1R_OFFSET);\
} while (0)

#define MAC_SPI1R_RD(data) do {\
	(data) = ioread32((void *)MAC_SPI1R_OFFSET);\
} while (0)

#define MAC_SPI1R_SPIO_WR(data) do {\
	MAC_SPI1R_WR(data);\
} while (0)

#define MAC_SPI1R_SPIO_RD(data) do {\
	MAC_SPI1R_RD(data);\
} while (0)

#define MAC_SPI0R_OFFSET ((volatile unsigned int *)(BASE_ADDRESS + 0xbc4))

#define MAC_SPI0R_WR(data) do {\
	iowrite32(data, (void *)MAC_SPI0R_OFFSET);\
} while (0)

#define MAC_SPI0R_RD(data) do {\
	(data) = ioread32((void *)MAC_SPI0R_OFFSET);\
} while (0)

#define MAC_SPI0R_SPIO_WR(data) do {\
	MAC_SPI0R_WR(data);\
} while (0)

#define MAC_SPI0R_SPIO_RD(data) do {\
	MAC_SPI0R_RD(data);\
} while (0)

#define MAC_PTO_CR_OFFSET ((volatile unsigned int *)(BASE_ADDRESS + 0xbc0))

#define MAC_PTO_CR_WR(data) do {\
	iowrite32(data, (void *)MAC_PTO_CR_OFFSET);\
} while (0)

#define MAC_PTO_CR_RD(data) do {\
	(data) = ioread32((void *)MAC_PTO_CR_OFFSET);\
} while (0)


#define  MAC_PTO_CR_MASK_16 (unsigned int)(0xffff)


#define MAC_PTO_CR_RES_WR_MASK_16 (unsigned int)(0xffff)


#define  MAC_PTO_CR_MASK_6 (unsigned int)(0x3)


#define MAC_PTO_CR_RES_WR_MASK_6 (unsigned int)(0xffffff3f)


#define  MAC_PTO_CR_MASK_3 (unsigned int)(0x1)


#define MAC_PTO_CR_RES_WR_MASK_3 (unsigned int)(0xfffffff7)


#define MAC_PTO_CR_DN_MASK (unsigned int)(0xff)


#define MAC_PTO_CR_DN_WR_MASK (unsigned int)(0xffff00ff)

#define MAC_PTO_CR_DN_WR(data) do {\
	unsigned int v;\
	MAC_PTO_CR_RD(v);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_16))\
	|(((0) & (MAC_PTO_CR_MASK_16))<<16);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_6))\
	|(((0) & (MAC_PTO_CR_MASK_6))<<6);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_3))\
	|(((0) & (MAC_PTO_CR_MASK_3))<<3);\
	v = ((v & MAC_PTO_CR_DN_WR_MASK)\
	|((data & MAC_PTO_CR_DN_MASK)<<8));\
	MAC_PTO_CR_WR(v);\
} while (0)

#define MAC_PTO_CR_DN_RD(data) do {\
	MAC_PTO_CR_RD(data);\
	data = ((data >> 8) & MAC_PTO_CR_DN_MASK);\
} while (0)


#define MAC_PTO_CR_APDREQTRIG_MASK (unsigned int)(0x1)


#define MAC_PTO_CR_APDREQTRIG_WR_MASK (unsigned int)(0xffffffdf)

#define MAC_PTO_CR_APDREQTRIG_WR(data) do {\
	unsigned int v;\
	MAC_PTO_CR_RD(v);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_16))\
	|(((0) & (MAC_PTO_CR_MASK_16))<<16);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_6))\
	|(((0) & (MAC_PTO_CR_MASK_6))<<6);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_3))\
	|(((0) & (MAC_PTO_CR_MASK_3))<<3);\
	v = ((v & MAC_PTO_CR_APDREQTRIG_WR_MASK)\
	|((data & MAC_PTO_CR_APDREQTRIG_MASK)<<5));\
	MAC_PTO_CR_WR(v);\
} while (0)

#define MAC_PTO_CR_APDREQTRIG_RD(data) do {\
	MAC_PTO_CR_RD(data);\
	data = ((data >> 5) & MAC_PTO_CR_APDREQTRIG_MASK);\
} while (0)


#define MAC_PTO_CR_ASYNCTRIG_MASK (unsigned int)(0x1)


#define MAC_PTO_CR_ASYNCTRIG_WR_MASK (unsigned int)(0xffffffef)

#define MAC_PTO_CR_ASYNCTRIG_WR(data) do {\
	unsigned int v;\
	MAC_PTO_CR_RD(v);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_16))\
	|(((0) & (MAC_PTO_CR_MASK_16))<<16);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_6))\
	|(((0) & (MAC_PTO_CR_MASK_6))<<6);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_3))\
	|(((0) & (MAC_PTO_CR_MASK_3))<<3);\
	v = ((v & MAC_PTO_CR_ASYNCTRIG_WR_MASK)\
	|((data & MAC_PTO_CR_ASYNCTRIG_MASK)<<4));\
	MAC_PTO_CR_WR(v);\
} while (0)

#define MAC_PTO_CR_ASYNCTRIG_RD(data) do {\
	MAC_PTO_CR_RD(data);\
	data = ((data >> 4) & MAC_PTO_CR_ASYNCTRIG_MASK);\
} while (0)


#define MAC_PTO_CR_APDREQEN_MASK (unsigned int)(0x1)


#define MAC_PTO_CR_APDREQEN_WR_MASK (unsigned int)(0xfffffffb)

#define MAC_PTO_CR_APDREQEN_WR(data) do {\
	unsigned int v;\
	MAC_PTO_CR_RD(v);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_16))\
	|(((0) & (MAC_PTO_CR_MASK_16))<<16);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_6))\
	|(((0) & (MAC_PTO_CR_MASK_6))<<6);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_3))\
	|(((0) & (MAC_PTO_CR_MASK_3))<<3);\
	v = ((v & MAC_PTO_CR_APDREQEN_WR_MASK)\
	|((data & MAC_PTO_CR_APDREQEN_MASK)<<2));\
	MAC_PTO_CR_WR(v);\
} while (0)

#define MAC_PTO_CR_APDREQEN_RD(data) do {\
	MAC_PTO_CR_RD(data);\
	data = ((data >> 2) & MAC_PTO_CR_APDREQEN_MASK);\
} while (0)


#define MAC_PTO_CR_ASYNCEN_MASK (unsigned int)(0x1)


#define MAC_PTO_CR_ASYNCEN_WR_MASK (unsigned int)(0xfffffffd)

#define MAC_PTO_CR_ASYNCEN_WR(data) do {\
	unsigned int v;\
	MAC_PTO_CR_RD(v);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_16))\
	|(((0) & (MAC_PTO_CR_MASK_16))<<16);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_6))\
	|(((0) & (MAC_PTO_CR_MASK_6))<<6);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_3))\
	|(((0) & (MAC_PTO_CR_MASK_3))<<3);\
	v = ((v & MAC_PTO_CR_ASYNCEN_WR_MASK)\
	|((data & MAC_PTO_CR_ASYNCEN_MASK)<<1));\
	MAC_PTO_CR_WR(v);\
} while (0)

#define MAC_PTO_CR_ASYNCEN_RD(data) do {\
	MAC_PTO_CR_RD(data);\
	data = ((data >> 1) & MAC_PTO_CR_ASYNCEN_MASK);\
} while (0)


#define MAC_PTO_CR_PTOEN_MASK (unsigned int)(0x1)


#define MAC_PTO_CR_PTOEN_WR_MASK (unsigned int)(0xfffffffe)

#define MAC_PTO_CR_PTOEN_WR(data) do {\
	unsigned int v;\
	MAC_PTO_CR_RD(v);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_16))\
	|(((0) & (MAC_PTO_CR_MASK_16))<<16);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_6))\
	|(((0) & (MAC_PTO_CR_MASK_6))<<6);\
	v = (v & (MAC_PTO_CR_RES_WR_MASK_3))\
	|(((0) & (MAC_PTO_CR_MASK_3))<<3);\
	v = ((v & MAC_PTO_CR_PTOEN_WR_MASK)\
	|((data & MAC_PTO_CR_PTOEN_MASK)<<0));\
	MAC_PTO_CR_WR(v);\
} while (0)

#define MAC_PTO_CR_PTOEN_RD(data) do {\
	MAC_PTO_CR_RD(data);\
	data = ((data >> 0) & MAC_PTO_CR_PTOEN_MASK);\
} while (0)

#define MAC_PPS_TTNS1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb94))

#define MAC_PPS_TTNS1_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTNS1_OFFSET);\
} while (0)

#define MAC_PPS_TTNS1_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTNS1_OFFSET);\
} while (0)


#define MAC_PPS_TTNS1_TTSL0_MASK (ULONG)(0x7fffffff)


#define MAC_PPS_TTNS1_TTSL0_WR_MASK (ULONG)(0x80000000)

#define MAC_PPS_TTNS1_TTSL0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS1_RD(v);\
	v = ((v & MAC_PPS_TTNS1_TTSL0_WR_MASK)\
	|((data & MAC_PPS_TTNS1_TTSL0_MASK)<<0));\
	MAC_PPS_TTNS1_WR(v);\
} while (0)

#define MAC_PPS_TTNS1_TTSL0_RD(data) do {\
	MAC_PPS_TTNS1_RD(data);\
	data = ((data >> 0) & MAC_PPS_TTNS1_TTSL0_MASK);\
} while (0)


#define MAC_PPS_TTNS1_TRGTBUSY0_MASK (ULONG)(0x1)


#define MAC_PPS_TTNS1_TRGTBUSY0_WR_MASK (ULONG)(0x7fffffff)

#define MAC_PPS_TTNS1_TRGTBUSY0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS1_RD(v);\
	v = ((v & MAC_PPS_TTNS1_TRGTBUSY0_WR_MASK)\
	|((data & MAC_PPS_TTNS1_TRGTBUSY0_MASK)<<31));\
	MAC_PPS_TTNS1_WR(v);\
} while (0)

#define MAC_PPS_TTNS1_TRGTBUSY0_RD(data) do {\
	MAC_PPS_TTNS1_RD(data);\
	data = ((data >> 31) & MAC_PPS_TTNS1_TRGTBUSY0_MASK);\
} while (0)

#define MAC_PPS_TTNS0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb84))

#define MAC_PPS_TTNS0_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTNS0_OFFSET);\
} while (0)

#define MAC_PPS_TTNS0_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTNS0_OFFSET);\
} while (0)


#define MAC_PPS_TTNS0_TTSL0_MASK (ULONG)(0x7fffffff)


#define MAC_PPS_TTNS0_TTSL0_WR_MASK (ULONG)(0x80000000)

#define MAC_PPS_TTNS0_TTSL0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS0_RD(v);\
	v = ((v & MAC_PPS_TTNS0_TTSL0_WR_MASK)\
	|((data & MAC_PPS_TTNS0_TTSL0_MASK)<<0));\
	MAC_PPS_TTNS0_WR(v);\
} while (0)

#define MAC_PPS_TTNS0_TTSL0_RD(data) do {\
	MAC_PPS_TTNS0_RD(data);\
	data = ((data >> 0) & MAC_PPS_TTNS0_TTSL0_MASK);\
} while (0)


#define MAC_PPS_TTNS0_TRGTBUSY0_MASK (ULONG)(0x1)


#define MAC_PPS_TTNS0_TRGTBUSY0_WR_MASK (ULONG)(0x7fffffff)

#define MAC_PPS_TTNS0_TRGTBUSY0_WR(data) do {\
	ULONG v;\
	MAC_PPS_TTNS0_RD(v);\
	v = ((v & MAC_PPS_TTNS0_TRGTBUSY0_WR_MASK)\
	|((data & MAC_PPS_TTNS0_TRGTBUSY0_MASK)<<31));\
	MAC_PPS_TTNS0_WR(v);\
} while (0)

#define MAC_PPS_TTNS0_TRGTBUSY0_RD(data) do {\
	MAC_PPS_TTNS0_RD(data);\
	data = ((data >> 31) & MAC_PPS_TTNS0_TRGTBUSY0_MASK);\
} while (0)

#define MAC_PPS_TTS3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xbb0))

#define MAC_PPS_TTS3_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTS3_OFFSET);\
} while (0)

#define MAC_PPS_TTS3_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTS3_OFFSET);\
} while (0)

#define MAC_PPS_TTS3_TSTRH0_WR(data) do {\
	MAC_PPS_TTS3_WR(data);\
} while (0)

#define MAC_PPS_TTS3_TSTRH0_RD(data) do {\
	MAC_PPS_TTS3_RD(data);\
} while (0)

#define MAC_PPS_TTS2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xba0))

#define MAC_PPS_TTS2_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTS2_OFFSET);\
} while (0)

#define MAC_PPS_TTS2_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTS2_OFFSET);\
} while (0)

#define MAC_PPS_TTS2_TSTRH0_WR(data) do {\
	MAC_PPS_TTS2_WR(data);\
} while (0)

#define MAC_PPS_TTS2_TSTRH0_RD(data) do {\
	MAC_PPS_TTS2_RD(data);\
} while (0)

#define MAC_PPS_TTS1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb90))

#define MAC_PPS_TTS1_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTS1_OFFSET);\
} while (0)

#define MAC_PPS_TTS1_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTS1_OFFSET);\
} while (0)

#define MAC_PPS_TTS1_TSTRH0_WR(data) do {\
	MAC_PPS_TTS1_WR(data);\
} while (0)

#define MAC_PPS_TTS1_TSTRH0_RD(data) do {\
	MAC_PPS_TTS1_RD(data);\
} while (0)

#define MAC_PPS_TTS0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb80))

#define MAC_PPS_TTS0_WR(data) do {\
	iowrite32(data, (void *)MAC_PPS_TTS0_OFFSET);\
} while (0)

#define MAC_PPS_TTS0_RD(data) do {\
	(data) = ioread32((void *)MAC_PPS_TTS0_OFFSET);\
} while (0)

#define MAC_PPS_TTS0_TSTRH0_WR(data) do {\
	MAC_PPS_TTS0_WR(data);\
} while (0)

#define MAC_PPS_TTS0_TSTRH0_RD(data) do {\
	MAC_PPS_TTS0_RD(data);\
} while (0)

#define MAC_PPSC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb70))

#define MAC_PPSC_WR(data) do {\
	iowrite32(data, (void *)MAC_PPSC_OFFSET);\
} while (0)

#define MAC_PPSC_RD(data) do {\
	(data) = ioread32((void *)MAC_PPSC_OFFSET);\
} while (0)


#define  MAC_PPSC_MASK_31 (ULONG)(0x1)


#define MAC_PPSC_RES_WR_MASK_31 (ULONG)(0x7fffffff)


#define  MAC_PPSC_MASK_27 (ULONG)(0x3)


#define MAC_PPSC_RES_WR_MASK_27 (ULONG)(0xe7ffffff)


#define  MAC_PPSC_MASK_23 (ULONG)(0x1)


#define MAC_PPSC_RES_WR_MASK_23 (ULONG)(0xff7fffff)


#define  MAC_PPSC_MASK_19 (ULONG)(0x3)


#define MAC_PPSC_RES_WR_MASK_19 (ULONG)(0xffe7ffff)


#define  MAC_PPSC_MASK_15 (ULONG)(0x1)


#define MAC_PPSC_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  MAC_PPSC_MASK_11 (ULONG)(0x3)


#define MAC_PPSC_RES_WR_MASK_11 (ULONG)(0xffffe7ff)


#define  MAC_PPSC_MASK_7 (ULONG)(0x1)


#define MAC_PPSC_RES_WR_MASK_7 (ULONG)(0xffffff7f)


#define MAC_PPSC_TRGTMODSEL3_MASK (ULONG)(0x3)


#define MAC_PPSC_TRGTMODSEL3_WR_MASK (ULONG)(0x9fffffff)

#define MAC_PPSC_TRGTMODSEL3_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_TRGTMODSEL3_WR_MASK)\
	|((data & MAC_PPSC_TRGTMODSEL3_MASK)<<29));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_TRGTMODSEL3_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 29) & MAC_PPSC_TRGTMODSEL3_MASK);\
} while (0)


#define MAC_PPSC_PPSCMD3_MASK (ULONG)(0x7)


#define MAC_PPSC_PPSCMD3_WR_MASK (ULONG)(0xf8ffffff)

#define MAC_PPSC_PPSCMD3_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_PPSCMD3_WR_MASK)\
	|((data & MAC_PPSC_PPSCMD3_MASK)<<24));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_PPSCMD3_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 24) & MAC_PPSC_PPSCMD3_MASK);\
} while (0)


#define MAC_PPSC_TRGTMODSEL2_MASK (ULONG)(0x3)


#define MAC_PPSC_TRGTMODSEL2_WR_MASK (ULONG)(0xff9fffff)

#define MAC_PPSC_TRGTMODSEL2_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_TRGTMODSEL2_WR_MASK)\
	|((data & MAC_PPSC_TRGTMODSEL2_MASK)<<21));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_TRGTMODSEL2_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 21) & MAC_PPSC_TRGTMODSEL2_MASK);\
} while (0)


#define MAC_PPSC_PPSCMD2_MASK (ULONG)(0x7)


#define MAC_PPSC_PPSCMD2_WR_MASK (ULONG)(0xfff8ffff)

#define MAC_PPSC_PPSCMD2_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_PPSCMD2_WR_MASK)\
	|((data & MAC_PPSC_PPSCMD2_MASK)<<16));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_PPSCMD2_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 16) & MAC_PPSC_PPSCMD2_MASK);\
} while (0)


#define MAC_PPSC_TRGTMODSEL1_MASK (ULONG)(0x3)


#define MAC_PPSC_TRGTMODSEL1_WR_MASK (ULONG)(0xffff9fff)

#define MAC_PPSC_TRGTMODSEL1_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_TRGTMODSEL1_WR_MASK)\
	|((data & MAC_PPSC_TRGTMODSEL1_MASK)<<13));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_TRGTMODSEL1_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 13) & MAC_PPSC_TRGTMODSEL1_MASK);\
} while (0)


#define MAC_PPSC_PPSCMD1_MASK (ULONG)(0x7)


#define MAC_PPSC_PPSCMD1_WR_MASK (ULONG)(0xfffff8ff)

#define MAC_PPSC_PPSCMD1_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_PPSCMD1_WR_MASK)\
	|((data & MAC_PPSC_PPSCMD1_MASK)<<8));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_PPSCMD1_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 8) & MAC_PPSC_PPSCMD1_MASK);\
} while (0)


#define MAC_PPSC_TRGTMODSEL0_MASK (ULONG)(0x3)


#define MAC_PPSC_TRGTMODSEL0_WR_MASK (ULONG)(0xffffff9f)

#define MAC_PPSC_TRGTMODSEL0_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_TRGTMODSEL0_WR_MASK)\
	|((data & MAC_PPSC_TRGTMODSEL0_MASK)<<5));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_TRGTMODSEL0_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 5) & MAC_PPSC_TRGTMODSEL0_MASK);\
} while (0)


#define MAC_PPSC_PPSEN0_MASK (ULONG)(0x1)


#define MAC_PPSC_PPSEN0_WR_MASK (ULONG)(0xffffffef)

#define MAC_PPSC_PPSEN0_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_PPSEN0_WR_MASK)\
	|((data & MAC_PPSC_PPSEN0_MASK)<<4));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_PPSEN0_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 4) & MAC_PPSC_PPSEN0_MASK);\
} while (0)


#define MAC_PPSC_PPSCTRL0_MASK (ULONG)(0xf)


#define MAC_PPSC_PPSCTRL0_WR_MASK (ULONG)(0xfffffff0)

#define MAC_PPSC_PPSCTRL0_WR(data) do {\
	ULONG v;\
	MAC_PPSC_RD(v);\
	v = (v & (MAC_PPSC_RES_WR_MASK_31))\
	|(((0) & (MAC_PPSC_MASK_31))<<31);\
	v = (v & (MAC_PPSC_RES_WR_MASK_27))\
	|(((0) & (MAC_PPSC_MASK_27))<<27);\
	v = (v & (MAC_PPSC_RES_WR_MASK_23))\
	|(((0) & (MAC_PPSC_MASK_23))<<23);\
	v = (v & (MAC_PPSC_RES_WR_MASK_19))\
	|(((0) & (MAC_PPSC_MASK_19))<<19);\
	v = (v & (MAC_PPSC_RES_WR_MASK_15))\
	|(((0) & (MAC_PPSC_MASK_15))<<15);\
	v = (v & (MAC_PPSC_RES_WR_MASK_11))\
	|(((0) & (MAC_PPSC_MASK_11))<<11);\
	v = (v & (MAC_PPSC_RES_WR_MASK_7))\
	|(((0) & (MAC_PPSC_MASK_7))<<7);\
	v = ((v & MAC_PPSC_PPSCTRL0_WR_MASK)\
	|((data & MAC_PPSC_PPSCTRL0_MASK)<<0));\
	MAC_PPSC_WR(v);\
} while (0)

#define MAC_PPSC_PPSCTRL0_RD(data) do {\
	MAC_PPSC_RD(data);\
	data = ((data >> 0) & MAC_PPSC_PPSCTRL0_MASK);\
} while (0)

#define MAC_TEAC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb54))

#define MAC_TEAC_WR(data) do {\
	iowrite32(data, (void *)MAC_TEAC_OFFSET);\
} while (0)

#define MAC_TEAC_RD(data) do {\
	(data) = ioread32((void *)MAC_TEAC_OFFSET);\
} while (0)


#define  MAC_TEAC_MASK_31 (ULONG)(0x1)


#define MAC_TEAC_RES_WR_MASK_31 (ULONG)(0x7fffffff)


#define MAC_TEAC_OSTIAC_MASK (ULONG)(0x7fffffff)


#define MAC_TEAC_OSTIAC_WR_MASK (ULONG)(0x80000000)

#define MAC_TEAC_OSTIAC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MAC_TEAC_RES_WR_MASK_31))\
	|(((0) & (MAC_TEAC_MASK_31))<<31);\
	(v) = ((v & MAC_TEAC_OSTIAC_WR_MASK)\
	|((data & MAC_TEAC_OSTIAC_MASK)<<0));\
	MAC_TEAC_WR(v);\
} while (0)

#define MAC_TEAC_OSTIAC_RD(data) do {\
	MAC_TEAC_RD(data);\
	data = ((data >> 0) & MAC_TEAC_OSTIAC_MASK);\
} while (0)

#define MAC_TIAC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb50))

#define MAC_TIAC_WR(data) do {\
	iowrite32(data, (void *)MAC_TIAC_OFFSET);\
} while (0)

#define MAC_TIAC_RD(data) do {\
	(data) = ioread32((void *)MAC_TIAC_OFFSET);\
} while (0)

#define MAC_TIAC_OSTIAC_WR(data) do {\
	MAC_TIAC_WR(data);\
} while (0)

#define MAC_TIAC_OSTIAC_RD(data) do {\
	MAC_TIAC_RD(data);\
} while (0)

#define MAC_ATS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb4c))

#define MAC_ATS_RD(data) do {\
	(data) = ioread32((void *)MAC_ATS_OFFSET);\
} while (0)

#define MAC_ATS_AUXTSHI_RD(data) do {\
	MAC_ATS_RD(data);\
} while (0)

#define MAC_ATN_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb48))

#define MAC_ATN_RD(data) do {\
	(data) = ioread32((void *)MAC_ATN_OFFSET);\
} while (0)


#define MAC_ATN_AUXTSLO_MASK (ULONG)(0x7fffffff)

#define MAC_ATN_AUXTSLO_RD(data) do {\
	MAC_ATN_RD(data);\
	data = ((data >> 0) & MAC_ATN_AUXTSLO_MASK);\
} while (0)

#define MAC_AC_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb40))

#define MAC_AC_WR(data) do {\
	iowrite32(data, (void *)MAC_AC_OFFSET);\
} while (0)

#define MAC_AC_RD(data) do {\
	(data) = ioread32((void *)MAC_AC_OFFSET);\
} while (0)


#define  MAC_AC_MASK_8 (ULONG)(0xffffff)


#define MAC_AC_RES_WR_MASK_8 (ULONG)(0xff)


#define  MAC_AC_MASK_1 (ULONG)(0x7)


#define MAC_AC_RES_WR_MASK_1 (ULONG)(0xfffffff1)


#define MAC_AC_ATSEN3_MASK (ULONG)(0x1)


#define MAC_AC_ATSEN3_WR_MASK (ULONG)(0xffffff7f)

#define MAC_AC_ATSEN3_WR(data) do {\
	ULONG v;\
	MAC_AC_RD(v);\
	v = (v & (MAC_AC_RES_WR_MASK_8))\
	|(((0) & (MAC_AC_MASK_8))<<8);\
	v = (v & (MAC_AC_RES_WR_MASK_1))\
	|(((0) & (MAC_AC_MASK_1))<<1);\
	v = ((v & MAC_AC_ATSEN3_WR_MASK)\
	|((data & MAC_AC_ATSEN3_MASK)<<7));\
	MAC_AC_WR(v);\
} while (0)

#define MAC_AC_ATSEN3_RD(data) do {\
	MAC_AC_RD(data);\
	data = ((data >> 7) & MAC_AC_ATSEN3_MASK);\
} while (0)


#define MAC_AC_ATSEN2_MASK (ULONG)(0x1)


#define MAC_AC_ATSEN2_WR_MASK (ULONG)(0xffffffbf)

#define MAC_AC_ATSEN2_WR(data) do {\
	ULONG v;\
	MAC_AC_RD(v);\
	v = (v & (MAC_AC_RES_WR_MASK_8))\
	|(((0) & (MAC_AC_MASK_8))<<8);\
	v = (v & (MAC_AC_RES_WR_MASK_1))\
	|(((0) & (MAC_AC_MASK_1))<<1);\
	v = ((v & MAC_AC_ATSEN2_WR_MASK)\
	|((data & MAC_AC_ATSEN2_MASK)<<6));\
	MAC_AC_WR(v);\
} while (0)

#define MAC_AC_ATSEN2_RD(data) do {\
	MAC_AC_RD(data);\
	data = ((data >> 6) & MAC_AC_ATSEN2_MASK);\
} while (0)


#define MAC_AC_ATSEN1_MASK (ULONG)(0x1)


#define MAC_AC_ATSEN1_WR_MASK (ULONG)(0xffffffdf)

#define MAC_AC_ATSEN1_WR(data) do {\
	ULONG v;\
	MAC_AC_RD(v);\
	v = (v & (MAC_AC_RES_WR_MASK_8))\
	|(((0) & (MAC_AC_MASK_8))<<8);\
	v = (v & (MAC_AC_RES_WR_MASK_1))\
	|(((0) & (MAC_AC_MASK_1))<<1);\
	v = ((v & MAC_AC_ATSEN1_WR_MASK)\
	|((data & MAC_AC_ATSEN1_MASK)<<5));\
	MAC_AC_WR(v);\
} while (0)

#define MAC_AC_ATSEN1_RD(data) do {\
	MAC_AC_RD(data);\
	data = ((data >> 5) & MAC_AC_ATSEN1_MASK);\
} while (0)


#define MAC_AC_ATSEN0_MASK (ULONG)(0x1)


#define MAC_AC_ATSEN0_WR_MASK (ULONG)(0xffffffef)

#define MAC_AC_ATSEN0_WR(data) do {\
	ULONG v;\
	MAC_AC_RD(v);\
	v = (v & (MAC_AC_RES_WR_MASK_8))\
	|(((0) & (MAC_AC_MASK_8))<<8);\
	v = (v & (MAC_AC_RES_WR_MASK_1))\
	|(((0) & (MAC_AC_MASK_1))<<1);\
	v = ((v & MAC_AC_ATSEN0_WR_MASK)\
	|((data & MAC_AC_ATSEN0_MASK)<<4));\
	MAC_AC_WR(v);\
} while (0)

#define MAC_AC_ATSEN0_RD(data) do {\
	MAC_AC_RD(data);\
	data = ((data >> 4) & MAC_AC_ATSEN0_MASK);\
} while (0)


#define MAC_AC_ATSFC_MASK (ULONG)(0x1)


#define MAC_AC_ATSFC_WR_MASK (ULONG)(0xfffffffe)

#define MAC_AC_ATSFC_WR(data) do {\
	ULONG v;\
	MAC_AC_RD(v);\
	v = (v & (MAC_AC_RES_WR_MASK_8))\
	|(((0) & (MAC_AC_MASK_8))<<8);\
	v = (v & (MAC_AC_RES_WR_MASK_1))\
	|(((0) & (MAC_AC_MASK_1))<<1);\
	v = ((v & MAC_AC_ATSFC_WR_MASK)\
	|((data & MAC_AC_ATSFC_MASK)<<0));\
	MAC_AC_WR(v);\
} while (0)

#define MAC_AC_ATSFC_RD(data) do {\
	MAC_AC_RD(data);\
	data = ((data >> 0) & MAC_AC_ATSFC_MASK);\
} while (0)

#define MAC_TTN_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb34))

#define MAC_TTN_RD(data) do {\
	(data) = ioread32((void *)MAC_TTN_OFFSET);\
} while (0)

#define MAC_TTN_TXTSSTSHI_RD(data) do {\
	MAC_TTN_RD(data);\
} while (0)

#define MAC_TTSN_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb30))

#define MAC_TTSN_RD(data) do {\
	(data) = ioread32((void *)MAC_TTSN_OFFSET);\
} while (0)


#define MAC_TTSN_TXTSSTSMIS_MASK (ULONG)(0x1)

#define MAC_TTSN_TXTSSTSMIS_RD(data) do {\
	MAC_TTSN_RD(data);\
	data = ((data >> 31) & MAC_TTSN_TXTSSTSMIS_MASK);\
} while (0)


#define MAC_TTSN_TXTSSTSLO_MASK (ULONG)(0x7fffffff)

#define MAC_TTSN_TXTSSTSLO_RD(data) do {\
	MAC_TTSN_RD(data);\
	data = ((data >> 0) & MAC_TTSN_TXTSSTSLO_MASK);\
} while (0)

#define MAC_TSR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb20))

#define MAC_TSR_RD(data) do {\
	(data) = ioread32((void *)MAC_TSR_OFFSET);\
} while (0)


#define MAC_TSR_ATSNS_MASK (ULONG)(0x1f)

#define MAC_TSR_ATSNS_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 25) & MAC_TSR_ATSNS_MASK);\
} while (0)


#define MAC_TSR_ATSSTM_MASK (ULONG)(0x1)

#define MAC_TSR_ATSSTM_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 24) & MAC_TSR_ATSSTM_MASK);\
} while (0)


#define MAC_TSR_ATSSTN_MASK (ULONG)(0xf)

#define MAC_TSR_ATSSTN_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 16) & MAC_TSR_ATSSTN_MASK);\
} while (0)


#define MAC_TSR_TSTRGTERR3_MASK (ULONG)(0x1)

#define MAC_TSR_TSTRGTERR3_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 9) & MAC_TSR_TSTRGTERR3_MASK);\
} while (0)


#define MAC_TSR_TSTARGT3_MASK (ULONG)(0x1)

#define MAC_TSR_TSTARGT3_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 8) & MAC_TSR_TSTARGT3_MASK);\
} while (0)


#define MAC_TSR_TSTRGTERR2_MASK (ULONG)(0x1)

#define MAC_TSR_TSTRGTERR2_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 7) & MAC_TSR_TSTRGTERR2_MASK);\
} while (0)


#define MAC_TSR_TSTARGT2_MASK (ULONG)(0x1)

#define MAC_TSR_TSTARGT2_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 6) & MAC_TSR_TSTARGT2_MASK);\
} while (0)


#define MAC_TSR_TSTRGTERR1_MASK (ULONG)(0x1)

#define MAC_TSR_TSTRGTERR1_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 5) & MAC_TSR_TSTRGTERR1_MASK);\
} while (0)


#define MAC_TSR_TSTARGT1_MASK (ULONG)(0x1)

#define MAC_TSR_TSTARGT1_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 4) & MAC_TSR_TSTARGT1_MASK);\
} while (0)


#define MAC_TSR_TSTRGTERR0_MASK (ULONG)(0x1)

#define MAC_TSR_TSTRGTERR0_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 3) & MAC_TSR_TSTRGTERR0_MASK);\
} while (0)


#define MAC_TSR_AUXTSTRIG_MASK (ULONG)(0x1)

#define MAC_TSR_AUXTSTRIG_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 2) & MAC_TSR_AUXTSTRIG_MASK);\
} while (0)


#define MAC_TSR_TSTARGT0_MASK (ULONG)(0x1)

#define MAC_TSR_TSTARGT0_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 1) & MAC_TSR_TSTARGT0_MASK);\
} while (0)


#define MAC_TSR_TSSOVF_MASK (ULONG)(0x1)

#define MAC_TSR_TSSOVF_RD(data) do {\
	MAC_TSR_RD(data);\
	data = ((data >> 0) & MAC_TSR_TSSOVF_MASK);\
} while (0)

#define MAC_STHWR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb1c))

#define MAC_STHWR_WR(data) do {\
	iowrite32(data, (void *)MAC_STHWR_OFFSET);\
} while (0)

#define MAC_STHWR_RD(data) do {\
	(data) = ioread32((void *)MAC_STHWR_OFFSET);\
} while (0)


#define  MAC_STHWR_MASK_16 (ULONG)(0xffff)


#define MAC_STHWR_RES_WR_MASK_16 (ULONG)(0xffff)


#define MAC_STHWR_TSHWR_MASK (ULONG)(0xffff)


#define MAC_STHWR_TSHWR_WR_MASK (ULONG)(0xffff0000)

#define MAC_STHWR_TSHWR_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MAC_STHWR_RES_WR_MASK_16))\
	|(((0) & (MAC_STHWR_MASK_16))<<16);\
	(v) = ((v & MAC_STHWR_TSHWR_WR_MASK)\
	|((data & MAC_STHWR_TSHWR_MASK)<<0));\
	MAC_STHWR_WR(v);\
} while (0)

#define MAC_STHWR_TSHWR_RD(data) do {\
	MAC_STHWR_RD(data);\
	data = ((data >> 0) & MAC_STHWR_TSHWR_MASK);\
} while (0)

#define MAC_TAR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb18))

#define MAC_TAR_WR(data) do {\
	iowrite32(data, (void *)MAC_TAR_OFFSET);\
} while (0)

#define MAC_TAR_RD(data) do {\
	(data) = ioread32((void *)MAC_TAR_OFFSET);\
} while (0)

#define MAC_TAR_TSAR_WR(data) do {\
	MAC_TAR_WR(data);\
} while (0)

#define MAC_TAR_TSAR_RD(data) do {\
	MAC_TAR_RD(data);\
} while (0)

#define MAC_STNSUR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb14))

#define MAC_STNSUR_WR(data) do {\
	iowrite32(data, (void *)MAC_STNSUR_OFFSET);\
} while (0)

#define MAC_STNSUR_RD(data) do {\
	(data) = ioread32((void *)MAC_STNSUR_OFFSET);\
} while (0)


#define MAC_STNSUR_ADDSUB_MASK (ULONG)(0x1)


#define MAC_STNSUR_ADDSUB_WR_MASK (ULONG)(0x7fffffff)

#define MAC_STNSUR_ADDSUB_WR(data) do {\
	ULONG v;\
	MAC_STNSUR_RD(v);\
	v = ((v & MAC_STNSUR_ADDSUB_WR_MASK)\
	|((data & MAC_STNSUR_ADDSUB_MASK)<<31));\
	MAC_STNSUR_WR(v);\
} while (0)

#define MAC_STNSUR_ADDSUB_RD(data) do {\
	MAC_STNSUR_RD(data);\
	data = ((data >> 31) & MAC_STNSUR_ADDSUB_MASK);\
} while (0)


#define MAC_STNSUR_TSSS_MASK (ULONG)(0x7fffffff)


#define MAC_STNSUR_TSSS_WR_MASK (ULONG)(0x80000000)

#define MAC_STNSUR_TSSS_WR(data) do {\
	ULONG v;\
	MAC_STNSUR_RD(v);\
	v = ((v & MAC_STNSUR_TSSS_WR_MASK)\
	|((data & MAC_STNSUR_TSSS_MASK)<<0));\
	MAC_STNSUR_WR(v);\
} while (0)

#define MAC_STNSUR_TSSS_RD(data) do {\
	MAC_STNSUR_RD(data);\
	data = ((data >> 0) & MAC_STNSUR_TSSS_MASK);\
} while (0)

#define MAC_STSUR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb10))

#define MAC_STSUR_WR(data) do {\
	iowrite32(data, (void *)MAC_STSUR_OFFSET);\
} while (0)

#define MAC_STSUR_RD(data) do {\
	(data) = ioread32((void *)MAC_STSUR_OFFSET);\
} while (0)

#define MAC_STSUR_TSS_WR(data) do {\
	MAC_STSUR_WR(data);\
} while (0)

#define MAC_STSUR_TSS_RD(data) do {\
	MAC_STSUR_RD(data);\
} while (0)

#define MAC_STNSR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb0c))

#define MAC_STNSR_RD(data) do {\
	(data) = ioread32((void *)MAC_STNSR_OFFSET);\
} while (0)


#define MAC_STNSR_TSSS_MASK (ULONG)(0x7fffffff)

#define MAC_STNSR_TSSS_RD(data) do {\
	MAC_STNSR_RD(data);\
	data = ((data >> 0) & MAC_STNSR_TSSS_MASK);\
} while (0)

#define MAC_STSR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb08))

#define MAC_STSR_RD(data) do {\
	(data) = ioread32((void *)MAC_STSR_OFFSET);\
} while (0)

#define MAC_STSR_TSS_RD(data) do {\
	MAC_STSR_RD(data);\
} while (0)

#define MAC_SSIR_OFFSET ((volatile unsigned int *)(BASE_ADDRESS + 0xb04))

#define MAC_SSIR_WR(data) do {\
	iowrite32(data, (void *)MAC_SSIR_OFFSET);\
} while (0)

#define MAC_SSIR_RD(data) do {\
	(data) = ioread32((void *)MAC_SSIR_OFFSET);\
} while (0)


#define  MAC_SSIR_MASK_24 (unsigned int)(0xff)


#define MAC_SSIR_RES_WR_MASK_24 (unsigned int)(0xffffff)


#define  MAC_SSIR_MASK_0 (unsigned int)(0xff)


#define MAC_SSIR_RES_WR_MASK_0 (unsigned int)(0xffffff00)


#define MAC_SSIR_SSINC_MASK (unsigned int)(0xff)


#define MAC_SSIR_SSINC_WR_MASK (unsigned int)(0xff00ffff)

#define MAC_SSIR_SSINC_WR(data) do {\
	unsigned int v;\
	MAC_SSIR_RD(v);\
	v = (v & (MAC_SSIR_RES_WR_MASK_24))\
	|(((0) & (MAC_SSIR_MASK_24))<<24);\
	v = (v & (MAC_SSIR_RES_WR_MASK_0))\
	|(((0) & (MAC_SSIR_MASK_0))<<0);\
	v = ((v & MAC_SSIR_SSINC_WR_MASK)\
	|((data & MAC_SSIR_SSINC_MASK)<<16));\
	MAC_SSIR_WR(v);\
} while (0)

#define MAC_SSIR_SSINC_RD(data) do {\
	MAC_SSIR_RD(data);\
	data = ((data >> 16) & MAC_SSIR_SSINC_MASK);\
} while (0)


#define MAC_SSIR_SNSINC_MASK (unsigned int)(0xff)


#define MAC_SSIR_SNSINC_WR_MASK (unsigned int)(0xffff00ff)

#define MAC_SSIR_SNSINC_WR(data) do {\
	unsigned int v;\
	MAC_SSIR_RD(v);\
	v = (v & (MAC_SSIR_RES_WR_MASK_24))\
	|(((0) & (MAC_SSIR_MASK_24))<<24);\
	v = (v & (MAC_SSIR_RES_WR_MASK_0))\
	|(((0) & (MAC_SSIR_MASK_0))<<0);\
	v = ((v & MAC_SSIR_SNSINC_WR_MASK)\
	|((data & MAC_SSIR_SNSINC_MASK)<<8));\
	MAC_SSIR_WR(v);\
} while (0)

#define MAC_SSIR_SNSINC_RD(data) do {\
	MAC_SSIR_RD(data);\
	data = ((data >> 8) & MAC_SSIR_SNSINC_MASK);\
} while (0)

#define MAC_TCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb00))

#define MAC_TCR_WR(data) do {\
	iowrite32(data, (void *)MAC_TCR_OFFSET);\
} while (0)

#define MAC_TCR_RD(data) do {\
	(data) = ioread32((void *)MAC_TCR_OFFSET);\
} while (0)


#define  MAC_TCR_MASK_29 (ULONG)(0x7)


#define MAC_TCR_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define  MAC_TCR_MASK_25 (ULONG)(0x7)


#define MAC_TCR_RES_WR_MASK_25 (ULONG)(0xf1ffffff)


#define  MAC_TCR_MASK_21 (ULONG)(0x7)


#define MAC_TCR_RES_WR_MASK_21 (ULONG)(0xff1fffff)


#define  MAC_TCR_MASK_19 (ULONG)(0x1)


#define MAC_TCR_RES_WR_MASK_19 (ULONG)(0xfff7ffff)


#define  MAC_TCR_MASK_6 (ULONG)(0x3)


#define MAC_TCR_RES_WR_MASK_6 (ULONG)(0xffffff3f)


#define MAC_TCR_AV8021ASMEN_MASK (ULONG)(0x1)


#define MAC_TCR_AV8021ASMEN_WR_MASK (ULONG)(0xefffffff)

#define MAC_TCR_AV8021ASMEN_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_AV8021ASMEN_WR_MASK)\
	|((data & MAC_TCR_AV8021ASMEN_MASK)<<28));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_AV8021ASMEN_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 28) & MAC_TCR_AV8021ASMEN_MASK);\
} while (0)


#define MAC_TCR_TXTSSTSM_MASK (ULONG)(0x1)


#define MAC_TCR_TXTSSTSM_WR_MASK (ULONG)(0xfeffffff)

#define MAC_TCR_TXTSSTSM_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TXTSSTSM_WR_MASK)\
	|((data & MAC_TCR_TXTSSTSM_MASK)<<24));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TXTSSTSM_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 24) & MAC_TCR_TXTSSTSM_MASK);\
} while (0)


#define MAC_TCR_ESTI_MASK (ULONG)(0x1)


#define MAC_TCR_ESTI_WR_MASK (ULONG)(0xffefffff)

#define MAC_TCR_ESTI_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_ESTI_WR_MASK)\
	|((data & MAC_TCR_ESTI_MASK)<<20));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_ESTI_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 20) & MAC_TCR_ESTI_MASK);\
} while (0)


#define MAC_TCR_TSENMACADDR_MASK (ULONG)(0x1)


#define MAC_TCR_TSENMACADDR_WR_MASK (ULONG)(0xfffbffff)

#define MAC_TCR_TSENMACADDR_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSENMACADDR_WR_MASK)\
	|((data & MAC_TCR_TSENMACADDR_MASK)<<18));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSENMACADDR_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 18) & MAC_TCR_TSENMACADDR_MASK);\
} while (0)


#define MAC_TCR_SNAPTYPSEL_MASK (ULONG)(0x3)


#define MAC_TCR_SNAPTYPSEL_WR_MASK (ULONG)(0xfffcffff)

#define MAC_TCR_SNAPTYPSEL_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_SNAPTYPSEL_WR_MASK)\
	|((data & MAC_TCR_SNAPTYPSEL_MASK)<<16));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_SNAPTYPSEL_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 16) & MAC_TCR_SNAPTYPSEL_MASK);\
} while (0)


#define MAC_TCR_TSMSTRENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSMSTRENA_WR_MASK (ULONG)(0xffff7fff)

#define MAC_TCR_TSMSTRENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSMSTRENA_WR_MASK)\
	|((data & MAC_TCR_TSMSTRENA_MASK)<<15));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSMSTRENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 15) & MAC_TCR_TSMSTRENA_MASK);\
} while (0)


#define MAC_TCR_TSEVNTENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSEVNTENA_WR_MASK (ULONG)(0xffffbfff)

#define MAC_TCR_TSEVNTENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSEVNTENA_WR_MASK)\
	|((data & MAC_TCR_TSEVNTENA_MASK)<<14));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSEVNTENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 14) & MAC_TCR_TSEVNTENA_MASK);\
} while (0)


#define MAC_TCR_TSIPV4ENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSIPV4ENA_WR_MASK (ULONG)(0xffffdfff)

#define MAC_TCR_TSIPV4ENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSIPV4ENA_WR_MASK)\
	|((data & MAC_TCR_TSIPV4ENA_MASK)<<13));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSIPV4ENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 13) & MAC_TCR_TSIPV4ENA_MASK);\
} while (0)


#define MAC_TCR_TSIPV6ENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSIPV6ENA_WR_MASK (ULONG)(0xffffefff)

#define MAC_TCR_TSIPV6ENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSIPV6ENA_WR_MASK)\
	|((data & MAC_TCR_TSIPV6ENA_MASK)<<12));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSIPV6ENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 12) & MAC_TCR_TSIPV6ENA_MASK);\
} while (0)


#define MAC_TCR_TSIPENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSIPENA_WR_MASK (ULONG)(0xfffff7ff)

#define MAC_TCR_TSIPENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSIPENA_WR_MASK)\
	|((data & MAC_TCR_TSIPENA_MASK)<<11));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSIPENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 11) & MAC_TCR_TSIPENA_MASK);\
} while (0)


#define MAC_TCR_TSVER2ENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSVER2ENA_WR_MASK (ULONG)(0xfffffbff)

#define MAC_TCR_TSVER2ENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSVER2ENA_WR_MASK)\
	|((data & MAC_TCR_TSVER2ENA_MASK)<<10));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSVER2ENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 10) & MAC_TCR_TSVER2ENA_MASK);\
} while (0)


#define MAC_TCR_TSCTRLSSR_MASK (ULONG)(0x1)


#define MAC_TCR_TSCTRLSSR_WR_MASK (ULONG)(0xfffffdff)

#define MAC_TCR_TSCTRLSSR_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSCTRLSSR_WR_MASK)\
	|((data & MAC_TCR_TSCTRLSSR_MASK)<<9));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSCTRLSSR_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 9) & MAC_TCR_TSCTRLSSR_MASK);\
} while (0)


#define MAC_TCR_TSENALL_MASK (ULONG)(0x1)


#define MAC_TCR_TSENALL_WR_MASK (ULONG)(0xfffffeff)

#define MAC_TCR_TSENALL_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSENALL_WR_MASK)\
	|((data & MAC_TCR_TSENALL_MASK)<<8));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSENALL_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 8) & MAC_TCR_TSENALL_MASK);\
} while (0)


#define MAC_TCR_TSADDREG_MASK (ULONG)(0x1)


#define MAC_TCR_TSADDREG_WR_MASK (ULONG)(0xffffffdf)

#define MAC_TCR_TSADDREG_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSADDREG_WR_MASK)\
	|((data & MAC_TCR_TSADDREG_MASK)<<5));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSADDREG_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 5) & MAC_TCR_TSADDREG_MASK);\
} while (0)


#define MAC_TCR_TSTRIG_MASK (ULONG)(0x1)


#define MAC_TCR_TSTRIG_WR_MASK (ULONG)(0xffffffef)

#define MAC_TCR_TSTRIG_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSTRIG_WR_MASK)\
	|((data & MAC_TCR_TSTRIG_MASK)<<4));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSTRIG_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 4) & MAC_TCR_TSTRIG_MASK);\
} while (0)


#define MAC_TCR_TSUPDT_MASK (ULONG)(0x1)


#define MAC_TCR_TSUPDT_WR_MASK (ULONG)(0xfffffff7)

#define MAC_TCR_TSUPDT_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSUPDT_WR_MASK)\
	|((data & MAC_TCR_TSUPDT_MASK)<<3));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSUPDT_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 3) & MAC_TCR_TSUPDT_MASK);\
} while (0)


#define MAC_TCR_TSINIT_MASK (ULONG)(0x1)


#define MAC_TCR_TSINIT_WR_MASK (ULONG)(0xfffffffb)

#define MAC_TCR_TSINIT_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSINIT_WR_MASK)\
	|((data & MAC_TCR_TSINIT_MASK)<<2));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSINIT_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 2) & MAC_TCR_TSINIT_MASK);\
} while (0)


#define MAC_TCR_TSCFUPDT_MASK (ULONG)(0x1)


#define MAC_TCR_TSCFUPDT_WR_MASK (ULONG)(0xfffffffd)

#define MAC_TCR_TSCFUPDT_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSCFUPDT_WR_MASK)\
	|((data & MAC_TCR_TSCFUPDT_MASK)<<1));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSCFUPDT_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 1) & MAC_TCR_TSCFUPDT_MASK);\
} while (0)


#define MAC_TCR_TSENA_MASK (ULONG)(0x1)


#define MAC_TCR_TSENA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_TCR_TSENA_WR(data) do {\
	ULONG v;\
	MAC_TCR_RD(v);\
	v = (v & (MAC_TCR_RES_WR_MASK_29))\
	|(((0) & (MAC_TCR_MASK_29))<<29);\
	v = (v & (MAC_TCR_RES_WR_MASK_25))\
	|(((0) & (MAC_TCR_MASK_25))<<25);\
	v = (v & (MAC_TCR_RES_WR_MASK_21))\
	|(((0) & (MAC_TCR_MASK_21))<<21);\
	v = (v & (MAC_TCR_RES_WR_MASK_19))\
	|(((0) & (MAC_TCR_MASK_19))<<19);\
	v = (v & (MAC_TCR_RES_WR_MASK_6))\
	|(((0) & (MAC_TCR_MASK_6))<<6);\
	v = ((v & MAC_TCR_TSENA_WR_MASK)\
	|((data & MAC_TCR_TSENA_MASK)<<0));\
	MAC_TCR_WR(v);\
} while (0)

#define MAC_TCR_TSENA_RD(data) do {\
	MAC_TCR_RD(data);\
	data = ((data >> 0) & MAC_TCR_TSENA_MASK);\
} while (0)

#define MTL_DSR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc0c))

#define MTL_DSR_WR(data) do {\
	iowrite32(data, (void *)MTL_DSR_OFFSET);\
} while (0)

#define MTL_DSR_RD(data) do {\
	(data) = ioread32((void *)MTL_DSR_OFFSET);\
} while (0)


#define  MTL_DSR_MASK_10 (ULONG)(0x3f)


#define MTL_DSR_RES_WR_MASK_10 (ULONG)(0xffff03ff)


#define  MTL_DSR_MASK_5 (ULONG)(0x7)


#define MTL_DSR_RES_WR_MASK_5 (ULONG)(0xffffff1f)


#define MTL_DSR_LOCR_MASK (ULONG)(0xffff)

#define MTL_DSR_LOCR_RD(data) do {\
	MTL_DSR_RD(data);\
	data = ((data >> 16) & MTL_DSR_LOCR_MASK);\
} while (0)


#define MTL_DSR_STSI_MASK (ULONG)(0x1)

#define MTL_DSR_STSI_RD(data) do {\
	MTL_DSR_RD(data);\
	data = ((data >> 9) & MTL_DSR_STSI_MASK);\
} while (0)


#define MTL_DSR_PKTI_MASK (ULONG)(0x1)

#define MTL_DSR_PKTI_RD(data) do {\
	MTL_DSR_RD(data);\
	data = ((data >> 8) & MTL_DSR_PKTI_MASK);\
} while (0)


#define MTL_DSR_BYTEEN_MASK (ULONG)(0x3)


#define MTL_DSR_BYTEEN_WR_MASK (ULONG)(0xffffffe7)

#define MTL_DSR_BYTEEN_WR(data) do {\
	ULONG v;\
	MTL_DSR_RD(v);\
	v = (v & (MTL_DSR_RES_WR_MASK_10))\
	|(((0) & (MTL_DSR_MASK_10))<<10);\
	v = (v & (MTL_DSR_RES_WR_MASK_5))\
	|(((0) & (MTL_DSR_MASK_5))<<5);\
	v = ((v & MTL_DSR_BYTEEN_WR_MASK)\
	|((data & MTL_DSR_BYTEEN_MASK)<<3));\
	MTL_DSR_WR(v);\
} while (0)

#define MTL_DSR_BYTEEN_RD(data) do {\
	MTL_DSR_RD(data);\
	data = ((data >> 3) & MTL_DSR_BYTEEN_MASK);\
} while (0)


#define MTL_DSR_PKTSTATE_MASK (ULONG)(0x3)

#define MTL_DSR_PKTSTATE_RD(data) do {\
	MTL_DSR_RD(data);\
	data = ((data >> 1) & MTL_DSR_PKTSTATE_MASK);\
} while (0)


#define MTL_DSR_FIFOBUSY_MASK (ULONG)(0x1)

#define MTL_DSR_FIFOBUSY_RD(data) do {\
	MTL_DSR_RD(data);\
	data = ((data >> 0) & MTL_DSR_FIFOBUSY_MASK);\
} while (0)

#define MAC_RWPFFR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc4))

#define MAC_RWPFFR_WR(data) do {\
	iowrite32(data, (void *)MAC_RWPFFR_OFFSET);\
} while (0)

#define MAC_RWPFFR_RD(data) do {\
	(data) = ioread32((void *)MAC_RWPFFR_OFFSET);\
} while (0)

#define MAC_RWPFFR_MAC_RWPFF_WR(data) do {\
	MAC_RWPFFR_WR(data);\
} while (0)

#define MAC_RWPFFR_MAC_RWPFF_RD(data) do {\
	MAC_RWPFFR_RD(data);\
} while (0)

#define MAC_RTSR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb8))

#define MAC_RTSR_RD(data) do {\
	(data) = ioread32((void *)MAC_RTSR_OFFSET);\
} while (0)


#define MAC_RTSR_RWT_MASK (ULONG)(0x1)

#define MAC_RTSR_RWT_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 8) & MAC_RTSR_RWT_MASK);\
} while (0)


#define MAC_RTSR_EXCOL_MASK (ULONG)(0x1)

#define MAC_RTSR_EXCOL_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 5) & MAC_RTSR_EXCOL_MASK);\
} while (0)


#define MAC_RTSR_LCOL_MASK (ULONG)(0x1)

#define MAC_RTSR_LCOL_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 4) & MAC_RTSR_LCOL_MASK);\
} while (0)


#define MAC_RTSR_EXDEF_MASK (ULONG)(0x1)

#define MAC_RTSR_EXDEF_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 3) & MAC_RTSR_EXDEF_MASK);\
} while (0)


#define MAC_RTSR_LCARR_MASK (ULONG)(0x1)

#define MAC_RTSR_LCARR_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 2) & MAC_RTSR_LCARR_MASK);\
} while (0)


#define MAC_RTSR_NCARR_MASK (ULONG)(0x1)

#define MAC_RTSR_NCARR_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 1) & MAC_RTSR_NCARR_MASK);\
} while (0)


#define MAC_RTSR_TJT_MASK (ULONG)(0x1)

#define MAC_RTSR_TJT_RD(data) do {\
	MAC_RTSR_RD(data);\
	data = ((data >> 0) & MAC_RTSR_TJT_MASK);\
} while (0)

#define MTL_IER_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc1c))

#define MTL_IER_WR(data) do {\
	iowrite32(data, (void *)MTL_IER_OFFSET);\
} while (0)

#define MTL_IER_RD(data) do {\
	(data) = ioread32((void *)MTL_IER_OFFSET);\
} while (0)


#define  MTL_IER_MASK_17 (ULONG)(0x7fff)


#define MTL_IER_RES_WR_MASK_17 (ULONG)(0x1ffff)


#define MTL_IER_MACIE_MASK (ULONG)(0x1)


#define MTL_IER_MACIE_WR_MASK (ULONG)(0xfffeffff)

#define MTL_IER_MACIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_MACIE_WR_MASK)\
	|((data & MTL_IER_MACIE_MASK)<<16));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_MACIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 16) & MTL_IER_MACIE_MASK);\
} while (0)


#define MTL_IER_Q7RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q7RXOIE_WR_MASK (ULONG)(0xffff7fff)

#define MTL_IER_Q7RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q7RXOIE_WR_MASK)\
	|((data & MTL_IER_Q7RXOIE_MASK)<<15));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q7RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 15) & MTL_IER_Q7RXOIE_MASK);\
} while (0)


#define MTL_IER_Q7TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q7TXUIE_WR_MASK (ULONG)(0xffffbfff)

#define MTL_IER_Q7TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q7TXUIE_WR_MASK)\
	|((data & MTL_IER_Q7TXUIE_MASK)<<14));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q7TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 14) & MTL_IER_Q7TXUIE_MASK);\
} while (0)


#define MTL_IER_Q6RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q6RXOIE_WR_MASK (ULONG)(0xffffdfff)

#define MTL_IER_Q6RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q6RXOIE_WR_MASK)\
	|((data & MTL_IER_Q6RXOIE_MASK)<<13));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q6RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 13) & MTL_IER_Q6RXOIE_MASK);\
} while (0)


#define MTL_IER_Q6TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q6TXUIE_WR_MASK (ULONG)(0xffffefff)

#define MTL_IER_Q6TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q6TXUIE_WR_MASK)\
	|((data & MTL_IER_Q6TXUIE_MASK)<<12));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q6TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 12) & MTL_IER_Q6TXUIE_MASK);\
} while (0)


#define MTL_IER_Q5RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q5RXOIE_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_IER_Q5RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q5RXOIE_WR_MASK)\
	|((data & MTL_IER_Q5RXOIE_MASK)<<11));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q5RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 11) & MTL_IER_Q5RXOIE_MASK);\
} while (0)


#define MTL_IER_Q5TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q5TXUIE_WR_MASK (ULONG)(0xfffffbff)

#define MTL_IER_Q5TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q5TXUIE_WR_MASK)\
	|((data & MTL_IER_Q5TXUIE_MASK)<<10));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q5TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 10) & MTL_IER_Q5TXUIE_MASK);\
} while (0)


#define MTL_IER_Q4RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q4RXOIE_WR_MASK (ULONG)(0xfffffdff)

#define MTL_IER_Q4RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q4RXOIE_WR_MASK)\
	|((data & MTL_IER_Q4RXOIE_MASK)<<9));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q4RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 9) & MTL_IER_Q4RXOIE_MASK);\
} while (0)


#define MTL_IER_Q4TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q4TXUIE_WR_MASK (ULONG)(0xfffffeff)

#define MTL_IER_Q4TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q4TXUIE_WR_MASK)\
	|((data & MTL_IER_Q4TXUIE_MASK)<<8));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q4TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 8) & MTL_IER_Q4TXUIE_MASK);\
} while (0)


#define MTL_IER_Q3RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q3RXOIE_WR_MASK (ULONG)(0xffffff7f)

#define MTL_IER_Q3RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q3RXOIE_WR_MASK)\
	|((data & MTL_IER_Q3RXOIE_MASK)<<7));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q3RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 7) & MTL_IER_Q3RXOIE_MASK);\
} while (0)


#define MTL_IER_Q3TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q3TXUIE_WR_MASK (ULONG)(0xffffffbf)

#define MTL_IER_Q3TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q3TXUIE_WR_MASK)\
	|((data & MTL_IER_Q3TXUIE_MASK)<<6));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q3TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 6) & MTL_IER_Q3TXUIE_MASK);\
} while (0)


#define MTL_IER_Q2RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q2RXOIE_WR_MASK (ULONG)(0xffffffdf)

#define MTL_IER_Q2RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q2RXOIE_WR_MASK)\
	|((data & MTL_IER_Q2RXOIE_MASK)<<5));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q2RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 5) & MTL_IER_Q2RXOIE_MASK);\
} while (0)


#define MTL_IER_Q2TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q2TXUIE_WR_MASK (ULONG)(0xffffffef)

#define MTL_IER_Q2TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q2TXUIE_WR_MASK)\
	|((data & MTL_IER_Q2TXUIE_MASK)<<4));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q2TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 4) & MTL_IER_Q2TXUIE_MASK);\
} while (0)


#define MTL_IER_Q1RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q1RXOIE_WR_MASK (ULONG)(0xfffffff7)

#define MTL_IER_Q1RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q1RXOIE_WR_MASK)\
	|((data & MTL_IER_Q1RXOIE_MASK)<<3));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q1RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 3) & MTL_IER_Q1RXOIE_MASK);\
} while (0)


#define MTL_IER_Q1TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q1TXUIE_WR_MASK (ULONG)(0xfffffffb)

#define MTL_IER_Q1TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q1TXUIE_WR_MASK)\
	|((data & MTL_IER_Q1TXUIE_MASK)<<2));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q1TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 2) & MTL_IER_Q1TXUIE_MASK);\
} while (0)


#define MTL_IER_Q0RXOIE_MASK (ULONG)(0x1)


#define MTL_IER_Q0RXOIE_WR_MASK (ULONG)(0xfffffffd)

#define MTL_IER_Q0RXOIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q0RXOIE_WR_MASK)\
	|((data & MTL_IER_Q0RXOIE_MASK)<<1));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q0RXOIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 1) & MTL_IER_Q0RXOIE_MASK);\
} while (0)


#define MTL_IER_Q0TXUIE_MASK (ULONG)(0x1)


#define MTL_IER_Q0TXUIE_WR_MASK (ULONG)(0xfffffffe)

#define MTL_IER_Q0TXUIE_WR(data) do {\
	ULONG v;\
	MTL_IER_RD(v);\
	v = (v & (MTL_IER_RES_WR_MASK_17))\
	|(((0) & (MTL_IER_MASK_17))<<17);\
	v = ((v & MTL_IER_Q0TXUIE_WR_MASK)\
	|((data & MTL_IER_Q0TXUIE_MASK)<<0));\
	MTL_IER_WR(v);\
} while (0)

#define MTL_IER_Q0TXUIE_RD(data) do {\
	MTL_IER_RD(data);\
	data = ((data >> 0) & MTL_IER_Q0TXUIE_MASK);\
} while (0)

#define MTL_QRCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xefc))

#define MTL_QRCR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR7_OFFSET);\
} while (0)

#define MTL_QRCR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR7_OFFSET);\
} while (0)


#define  MTL_QRCR7_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR7_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR7_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR7_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR7_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR7_RD(v);\
	v = (v & (MTL_QRCR7_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR7_MASK_4))<<4);\
	v = ((v & MTL_QRCR7_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR7_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR7_WR(v);\
} while (0)

#define MTL_QRCR7_RXQ_WEGT_RD(data) do {\
	MTL_QRCR7_RD(data);\
	data = ((data >> 0) & MTL_QRCR7_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR7_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR7_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR7_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR7_RD(v);\
	v = (v & (MTL_QRCR7_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR7_MASK_4))<<4);\
	v = ((v & MTL_QRCR7_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR7_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR7_WR(v);\
} while (0)

#define MTL_QRCR7_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR7_RD(data);\
	data = ((data >> 3) & MTL_QRCR7_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xebc))

#define MTL_QRCR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR6_OFFSET);\
} while (0)

#define MTL_QRCR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR6_OFFSET);\
} while (0)


#define  MTL_QRCR6_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR6_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR6_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR6_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR6_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR6_RD(v);\
	v = (v & (MTL_QRCR6_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR6_MASK_4))<<4);\
	v = ((v & MTL_QRCR6_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR6_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR6_WR(v);\
} while (0)

#define MTL_QRCR6_RXQ_WEGT_RD(data) do {\
	MTL_QRCR6_RD(data);\
	data = ((data >> 0) & MTL_QRCR6_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR6_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR6_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR6_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR6_RD(v);\
	v = (v & (MTL_QRCR6_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR6_MASK_4))<<4);\
	v = ((v & MTL_QRCR6_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR6_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR6_WR(v);\
} while (0)

#define MTL_QRCR6_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR6_RD(data);\
	data = ((data >> 3) & MTL_QRCR6_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe7c))

#define MTL_QRCR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR5_OFFSET);\
} while (0)

#define MTL_QRCR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR5_OFFSET);\
} while (0)


#define  MTL_QRCR5_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR5_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR5_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR5_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR5_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR5_RD(v);\
	v = (v & (MTL_QRCR5_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR5_MASK_4))<<4);\
	v = ((v & MTL_QRCR5_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR5_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR5_WR(v);\
} while (0)

#define MTL_QRCR5_RXQ_WEGT_RD(data) do {\
	MTL_QRCR5_RD(data);\
	data = ((data >> 0) & MTL_QRCR5_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR5_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR5_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR5_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR5_RD(v);\
	v = (v & (MTL_QRCR5_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR5_MASK_4))<<4);\
	v = ((v & MTL_QRCR5_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR5_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR5_WR(v);\
} while (0)

#define MTL_QRCR5_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR5_RD(data);\
	data = ((data >> 3) & MTL_QRCR5_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe3c))

#define MTL_QRCR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR4_OFFSET);\
} while (0)

#define MTL_QRCR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR4_OFFSET);\
} while (0)


#define  MTL_QRCR4_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR4_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR4_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR4_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR4_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR4_RD(v);\
	v = (v & (MTL_QRCR4_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR4_MASK_4))<<4);\
	v = ((v & MTL_QRCR4_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR4_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR4_WR(v);\
} while (0)

#define MTL_QRCR4_RXQ_WEGT_RD(data) do {\
	MTL_QRCR4_RD(data);\
	data = ((data >> 0) & MTL_QRCR4_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR4_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR4_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR4_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR4_RD(v);\
	v = (v & (MTL_QRCR4_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR4_MASK_4))<<4);\
	v = ((v & MTL_QRCR4_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR4_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR4_WR(v);\
} while (0)

#define MTL_QRCR4_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR4_RD(data);\
	data = ((data >> 3) & MTL_QRCR4_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdfc))

#define MTL_QRCR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR3_OFFSET);\
} while (0)

#define MTL_QRCR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR3_OFFSET);\
} while (0)


#define  MTL_QRCR3_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR3_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR3_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR3_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR3_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR3_RD(v);\
	v = (v & (MTL_QRCR3_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR3_MASK_4))<<4);\
	v = ((v & MTL_QRCR3_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR3_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR3_WR(v);\
} while (0)

#define MTL_QRCR3_RXQ_WEGT_RD(data) do {\
	MTL_QRCR3_RD(data);\
	data = ((data >> 0) & MTL_QRCR3_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR3_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR3_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR3_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR3_RD(v);\
	v = (v & (MTL_QRCR3_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR3_MASK_4))<<4);\
	v = ((v & MTL_QRCR3_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR3_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR3_WR(v);\
} while (0)

#define MTL_QRCR3_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR3_RD(data);\
	data = ((data >> 3) & MTL_QRCR3_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdbc))

#define MTL_QRCR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR2_OFFSET);\
} while (0)

#define MTL_QRCR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR2_OFFSET);\
} while (0)


#define  MTL_QRCR2_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR2_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR2_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR2_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR2_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR2_RD(v);\
	v = (v & (MTL_QRCR2_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR2_MASK_4))<<4);\
	v = ((v & MTL_QRCR2_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR2_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR2_WR(v);\
} while (0)

#define MTL_QRCR2_RXQ_WEGT_RD(data) do {\
	MTL_QRCR2_RD(data);\
	data = ((data >> 0) & MTL_QRCR2_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR2_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR2_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR2_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR2_RD(v);\
	v = (v & (MTL_QRCR2_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR2_MASK_4))<<4);\
	v = ((v & MTL_QRCR2_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR2_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR2_WR(v);\
} while (0)

#define MTL_QRCR2_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR2_RD(data);\
	data = ((data >> 3) & MTL_QRCR2_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd7c))

#define MTL_QRCR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QRCR1_OFFSET);\
} while (0)

#define MTL_QRCR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QRCR1_OFFSET);\
} while (0)


#define  MTL_QRCR1_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR1_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR1_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR1_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR1_RXQ_WEGT_WR(data) do {\
	ULONG v;\
	MTL_QRCR1_RD(v);\
	v = (v & (MTL_QRCR1_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR1_MASK_4))<<4);\
	v = ((v & MTL_QRCR1_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR1_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR1_WR(v);\
} while (0)

#define MTL_QRCR1_RXQ_WEGT_RD(data) do {\
	MTL_QRCR1_RD(data);\
	data = ((data >> 0) & MTL_QRCR1_RXQ_WEGT_MASK);\
} while (0)


#define MTL_QRCR1_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR1_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR1_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_QRCR1_RD(v);\
	v = (v & (MTL_QRCR1_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR1_MASK_4))<<4);\
	v = ((v & MTL_QRCR1_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR1_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR1_WR(v);\
} while (0)

#define MTL_QRCR1_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_QRCR1_RD(data);\
	data = ((data >> 3) & MTL_QRCR1_RXQ_PKT_ARBIT_MASK);\
} while (0)

#define MTL_QRDR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xef8))

#define MTL_QRDR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR7_OFFSET);\
} while (0)


#define MTL_QRDR7_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR7_RWCSTS_RD(data) do {\
	MTL_QRDR7_RD(data);\
	data = ((data >> 0) & MTL_QRDR7_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR7_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR7_RRCSTS_RD(data) do {\
	MTL_QRDR7_RD(data);\
	data = ((data >> 1) & MTL_QRDR7_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR7_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR7_RXQSTS_RD(data) do {\
	MTL_QRDR7_RD(data);\
	data = ((data >> 4) & MTL_QRDR7_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR7_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR7_PRXQ_RD(data) do {\
	MTL_QRDR7_RD(data);\
	data = ((data >> 16) & MTL_QRDR7_PRXQ_MASK);\
} while (0)

#define MTL_QRDR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xeb8))

#define MTL_QRDR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR6_OFFSET);\
} while (0)


#define MTL_QRDR6_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR6_RWCSTS_RD(data) do {\
	MTL_QRDR6_RD(data);\
	data = ((data >> 0) & MTL_QRDR6_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR6_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR6_RRCSTS_RD(data) do {\
	MTL_QRDR6_RD(data);\
	data = ((data >> 1) & MTL_QRDR6_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR6_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR6_RXQSTS_RD(data) do {\
	MTL_QRDR6_RD(data);\
	data = ((data >> 4) & MTL_QRDR6_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR6_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR6_PRXQ_RD(data) do {\
	MTL_QRDR6_RD(data);\
	data = ((data >> 16) & MTL_QRDR6_PRXQ_MASK);\
} while (0)

#define MTL_QRDR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe78))

#define MTL_QRDR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR5_OFFSET);\
} while (0)


#define MTL_QRDR5_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR5_RWCSTS_RD(data) do {\
	MTL_QRDR5_RD(data);\
	data = ((data >> 0) & MTL_QRDR5_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR5_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR5_RRCSTS_RD(data) do {\
	MTL_QRDR5_RD(data);\
	data = ((data >> 1) & MTL_QRDR5_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR5_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR5_RXQSTS_RD(data) do {\
	MTL_QRDR5_RD(data);\
	data = ((data >> 4) & MTL_QRDR5_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR5_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR5_PRXQ_RD(data) do {\
	MTL_QRDR5_RD(data);\
	data = ((data >> 16) & MTL_QRDR5_PRXQ_MASK);\
} while (0)

#define MTL_QRDR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe38))

#define MTL_QRDR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR4_OFFSET);\
} while (0)


#define MTL_QRDR4_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR4_RWCSTS_RD(data) do {\
	MTL_QRDR4_RD(data);\
	data = ((data >> 0) & MTL_QRDR4_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR4_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR4_RRCSTS_RD(data) do {\
	MTL_QRDR4_RD(data);\
	data = ((data >> 1) & MTL_QRDR4_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR4_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR4_RXQSTS_RD(data) do {\
	MTL_QRDR4_RD(data);\
	data = ((data >> 4) & MTL_QRDR4_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR4_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR4_PRXQ_RD(data) do {\
	MTL_QRDR4_RD(data);\
	data = ((data >> 16) & MTL_QRDR4_PRXQ_MASK);\
} while (0)

#define MTL_QRDR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdf8))

#define MTL_QRDR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR3_OFFSET);\
} while (0)


#define MTL_QRDR3_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR3_RWCSTS_RD(data) do {\
	MTL_QRDR3_RD(data);\
	data = ((data >> 0) & MTL_QRDR3_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR3_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR3_RRCSTS_RD(data) do {\
	MTL_QRDR3_RD(data);\
	data = ((data >> 1) & MTL_QRDR3_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR3_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR3_RXQSTS_RD(data) do {\
	MTL_QRDR3_RD(data);\
	data = ((data >> 4) & MTL_QRDR3_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR3_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR3_PRXQ_RD(data) do {\
	MTL_QRDR3_RD(data);\
	data = ((data >> 16) & MTL_QRDR3_PRXQ_MASK);\
} while (0)

#define MTL_QRDR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdb8))

#define MTL_QRDR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR2_OFFSET);\
} while (0)


#define MTL_QRDR2_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR2_RWCSTS_RD(data) do {\
	MTL_QRDR2_RD(data);\
	data = ((data >> 0) & MTL_QRDR2_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR2_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR2_RRCSTS_RD(data) do {\
	MTL_QRDR2_RD(data);\
	data = ((data >> 1) & MTL_QRDR2_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR2_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR2_RXQSTS_RD(data) do {\
	MTL_QRDR2_RD(data);\
	data = ((data >> 4) & MTL_QRDR2_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR2_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR2_PRXQ_RD(data) do {\
	MTL_QRDR2_RD(data);\
	data = ((data >> 16) & MTL_QRDR2_PRXQ_MASK);\
} while (0)

#define MTL_QRDR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd78))

#define MTL_QRDR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QRDR1_OFFSET);\
} while (0)


#define MTL_QRDR1_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR1_RWCSTS_RD(data) do {\
	MTL_QRDR1_RD(data);\
	data = ((data >> 0) & MTL_QRDR1_RWCSTS_MASK);\
} while (0)


#define MTL_QRDR1_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR1_RRCSTS_RD(data) do {\
	MTL_QRDR1_RD(data);\
	data = ((data >> 1) & MTL_QRDR1_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR1_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR1_RXQSTS_RD(data) do {\
	MTL_QRDR1_RD(data);\
	data = ((data >> 4) & MTL_QRDR1_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR1_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR1_PRXQ_RD(data) do {\
	MTL_QRDR1_RD(data);\
	data = ((data >> 16) & MTL_QRDR1_PRXQ_MASK);\
} while (0)

#define MTL_QOCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xef4))

#define MTL_QOCR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR7_OFFSET);\
} while (0)

#define MTL_QOCR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR7_OFFSET);\
} while (0)


#define  MTL_QOCR7_MASK_12 (ULONG)(0xf)


#define MTL_QOCR7_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR7_MASK_28 (ULONG)(0xf)


#define MTL_QOCR7_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR7_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR7_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR7_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR7_RD(v);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR7_MASK_12))<<12);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR7_MASK_28))<<28);\
	v = ((v & MTL_QOCR7_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR7_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR7_WR(v);\
} while (0)

#define MTL_QOCR7_OVFPKTCNT_RD(data) do {\
	MTL_QOCR7_RD(data);\
	data = ((data >> 0) & MTL_QOCR7_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR7_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR7_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR7_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR7_RD(v);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR7_MASK_12))<<12);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR7_MASK_28))<<28);\
	v = ((v & MTL_QOCR7_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR7_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR7_WR(v);\
} while (0)

#define MTL_QOCR7_OVFCNTOVF_RD(data) do {\
	MTL_QOCR7_RD(data);\
	data = ((data >> 11) & MTL_QOCR7_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR7_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR7_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR7_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR7_RD(v);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR7_MASK_12))<<12);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR7_MASK_28))<<28);\
	v = ((v & MTL_QOCR7_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR7_MISPKTCNT_MASK)<<16));\
	MTL_QOCR7_WR(v);\
} while (0)

#define MTL_QOCR7_MISPKTCNT_RD(data) do {\
	MTL_QOCR7_RD(data);\
	data = ((data >> 16) & MTL_QOCR7_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR7_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR7_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR7_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR7_RD(v);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR7_MASK_12))<<12);\
	v = (v & (MTL_QOCR7_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR7_MASK_28))<<28);\
	v = ((v & MTL_QOCR7_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR7_MISCNTOVF_MASK)<<27));\
	MTL_QOCR7_WR(v);\
} while (0)

#define MTL_QOCR7_MISCNTOVF_RD(data) do {\
	MTL_QOCR7_RD(data);\
	data = ((data >> 27) & MTL_QOCR7_MISCNTOVF_MASK);\
} while (0)

#define MTL_QOCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xeb4))

#define MTL_QOCR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR6_OFFSET);\
} while (0)

#define MTL_QOCR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR6_OFFSET);\
} while (0)


#define  MTL_QOCR6_MASK_12 (ULONG)(0xf)


#define MTL_QOCR6_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR6_MASK_28 (ULONG)(0xf)


#define MTL_QOCR6_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR6_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR6_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR6_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR6_RD(v);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR6_MASK_12))<<12);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR6_MASK_28))<<28);\
	v = ((v & MTL_QOCR6_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR6_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR6_WR(v);\
} while (0)

#define MTL_QOCR6_OVFPKTCNT_RD(data) do {\
	MTL_QOCR6_RD(data);\
	data = ((data >> 0) & MTL_QOCR6_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR6_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR6_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR6_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR6_RD(v);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR6_MASK_12))<<12);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR6_MASK_28))<<28);\
	v = ((v & MTL_QOCR6_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR6_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR6_WR(v);\
} while (0)

#define MTL_QOCR6_OVFCNTOVF_RD(data) do {\
	MTL_QOCR6_RD(data);\
	data = ((data >> 11) & MTL_QOCR6_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR6_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR6_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR6_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR6_RD(v);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR6_MASK_12))<<12);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR6_MASK_28))<<28);\
	v = ((v & MTL_QOCR6_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR6_MISPKTCNT_MASK)<<16));\
	MTL_QOCR6_WR(v);\
} while (0)

#define MTL_QOCR6_MISPKTCNT_RD(data) do {\
	MTL_QOCR6_RD(data);\
	data = ((data >> 16) & MTL_QOCR6_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR6_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR6_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR6_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR6_RD(v);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR6_MASK_12))<<12);\
	v = (v & (MTL_QOCR6_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR6_MASK_28))<<28);\
	v = ((v & MTL_QOCR6_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR6_MISCNTOVF_MASK)<<27));\
	MTL_QOCR6_WR(v);\
} while (0)

#define MTL_QOCR6_MISCNTOVF_RD(data) do {\
	MTL_QOCR6_RD(data);\
	data = ((data >> 27) & MTL_QOCR6_MISCNTOVF_MASK);\
} while (0)

#define MTL_QOCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe74))

#define MTL_QOCR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR5_OFFSET);\
} while (0)

#define MTL_QOCR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR5_OFFSET);\
} while (0)


#define  MTL_QOCR5_MASK_12 (ULONG)(0xf)


#define MTL_QOCR5_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR5_MASK_28 (ULONG)(0xf)


#define MTL_QOCR5_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR5_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR5_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR5_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR5_RD(v);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR5_MASK_12))<<12);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR5_MASK_28))<<28);\
	v = ((v & MTL_QOCR5_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR5_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR5_WR(v);\
} while (0)

#define MTL_QOCR5_OVFPKTCNT_RD(data) do {\
	MTL_QOCR5_RD(data);\
	data = ((data >> 0) & MTL_QOCR5_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR5_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR5_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR5_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR5_RD(v);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR5_MASK_12))<<12);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR5_MASK_28))<<28);\
	v = ((v & MTL_QOCR5_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR5_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR5_WR(v);\
} while (0)

#define MTL_QOCR5_OVFCNTOVF_RD(data) do {\
	MTL_QOCR5_RD(data);\
	data = ((data >> 11) & MTL_QOCR5_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR5_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR5_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR5_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR5_RD(v);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR5_MASK_12))<<12);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR5_MASK_28))<<28);\
	v = ((v & MTL_QOCR5_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR5_MISPKTCNT_MASK)<<16));\
	MTL_QOCR5_WR(v);\
} while (0)

#define MTL_QOCR5_MISPKTCNT_RD(data) do {\
	MTL_QOCR5_RD(data);\
	data = ((data >> 16) & MTL_QOCR5_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR5_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR5_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR5_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR5_RD(v);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR5_MASK_12))<<12);\
	v = (v & (MTL_QOCR5_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR5_MASK_28))<<28);\
	v = ((v & MTL_QOCR5_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR5_MISCNTOVF_MASK)<<27));\
	MTL_QOCR5_WR(v);\
} while (0)

#define MTL_QOCR5_MISCNTOVF_RD(data) do {\
	MTL_QOCR5_RD(data);\
	data = ((data >> 27) & MTL_QOCR5_MISCNTOVF_MASK);\
} while (0)

#define MTL_QOCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe34))

#define MTL_QOCR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR4_OFFSET);\
} while (0)

#define MTL_QOCR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR4_OFFSET);\
} while (0)


#define  MTL_QOCR4_MASK_12 (ULONG)(0xf)


#define MTL_QOCR4_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR4_MASK_28 (ULONG)(0xf)


#define MTL_QOCR4_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR4_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR4_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR4_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR4_RD(v);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR4_MASK_12))<<12);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR4_MASK_28))<<28);\
	v = ((v & MTL_QOCR4_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR4_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR4_WR(v);\
} while (0)

#define MTL_QOCR4_OVFPKTCNT_RD(data) do {\
	MTL_QOCR4_RD(data);\
	data = ((data >> 0) & MTL_QOCR4_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR4_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR4_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR4_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR4_RD(v);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR4_MASK_12))<<12);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR4_MASK_28))<<28);\
	v = ((v & MTL_QOCR4_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR4_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR4_WR(v);\
} while (0)

#define MTL_QOCR4_OVFCNTOVF_RD(data) do {\
	MTL_QOCR4_RD(data);\
	data = ((data >> 11) & MTL_QOCR4_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR4_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR4_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR4_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR4_RD(v);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR4_MASK_12))<<12);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR4_MASK_28))<<28);\
	v = ((v & MTL_QOCR4_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR4_MISPKTCNT_MASK)<<16));\
	MTL_QOCR4_WR(v);\
} while (0)

#define MTL_QOCR4_MISPKTCNT_RD(data) do {\
	MTL_QOCR4_RD(data);\
	data = ((data >> 16) & MTL_QOCR4_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR4_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR4_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR4_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR4_RD(v);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR4_MASK_12))<<12);\
	v = (v & (MTL_QOCR4_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR4_MASK_28))<<28);\
	v = ((v & MTL_QOCR4_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR4_MISCNTOVF_MASK)<<27));\
	MTL_QOCR4_WR(v);\
} while (0)

#define MTL_QOCR4_MISCNTOVF_RD(data) do {\
	MTL_QOCR4_RD(data);\
	data = ((data >> 27) & MTL_QOCR4_MISCNTOVF_MASK);\
} while (0)

#define MTL_QOCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdf4))

#define MTL_QOCR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR3_OFFSET);\
} while (0)

#define MTL_QOCR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR3_OFFSET);\
} while (0)


#define  MTL_QOCR3_MASK_12 (ULONG)(0xf)


#define MTL_QOCR3_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR3_MASK_28 (ULONG)(0xf)


#define MTL_QOCR3_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR3_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR3_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR3_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR3_RD(v);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR3_MASK_12))<<12);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR3_MASK_28))<<28);\
	v = ((v & MTL_QOCR3_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR3_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR3_WR(v);\
} while (0)

#define MTL_QOCR3_OVFPKTCNT_RD(data) do {\
	MTL_QOCR3_RD(data);\
	data = ((data >> 0) & MTL_QOCR3_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR3_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR3_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR3_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR3_RD(v);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR3_MASK_12))<<12);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR3_MASK_28))<<28);\
	v = ((v & MTL_QOCR3_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR3_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR3_WR(v);\
} while (0)

#define MTL_QOCR3_OVFCNTOVF_RD(data) do {\
	MTL_QOCR3_RD(data);\
	data = ((data >> 11) & MTL_QOCR3_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR3_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR3_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR3_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR3_RD(v);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR3_MASK_12))<<12);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR3_MASK_28))<<28);\
	v = ((v & MTL_QOCR3_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR3_MISPKTCNT_MASK)<<16));\
	MTL_QOCR3_WR(v);\
} while (0)

#define MTL_QOCR3_MISPKTCNT_RD(data) do {\
	MTL_QOCR3_RD(data);\
	data = ((data >> 16) & MTL_QOCR3_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR3_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR3_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR3_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR3_RD(v);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR3_MASK_12))<<12);\
	v = (v & (MTL_QOCR3_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR3_MASK_28))<<28);\
	v = ((v & MTL_QOCR3_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR3_MISCNTOVF_MASK)<<27));\
	MTL_QOCR3_WR(v);\
} while (0)

#define MTL_QOCR3_MISCNTOVF_RD(data) do {\
	MTL_QOCR3_RD(data);\
	data = ((data >> 27) & MTL_QOCR3_MISCNTOVF_MASK);\
} while (0)

#define MTL_QOCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdb4))

#define MTL_QOCR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR2_OFFSET);\
} while (0)

#define MTL_QOCR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR2_OFFSET);\
} while (0)


#define  MTL_QOCR2_MASK_12 (ULONG)(0xf)


#define MTL_QOCR2_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR2_MASK_28 (ULONG)(0xf)


#define MTL_QOCR2_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR2_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR2_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR2_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR2_RD(v);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR2_MASK_12))<<12);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR2_MASK_28))<<28);\
	v = ((v & MTL_QOCR2_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR2_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR2_WR(v);\
} while (0)

#define MTL_QOCR2_OVFPKTCNT_RD(data) do {\
	MTL_QOCR2_RD(data);\
	data = ((data >> 0) & MTL_QOCR2_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR2_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR2_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR2_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR2_RD(v);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR2_MASK_12))<<12);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR2_MASK_28))<<28);\
	v = ((v & MTL_QOCR2_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR2_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR2_WR(v);\
} while (0)

#define MTL_QOCR2_OVFCNTOVF_RD(data) do {\
	MTL_QOCR2_RD(data);\
	data = ((data >> 11) & MTL_QOCR2_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR2_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR2_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR2_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR2_RD(v);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR2_MASK_12))<<12);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR2_MASK_28))<<28);\
	v = ((v & MTL_QOCR2_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR2_MISPKTCNT_MASK)<<16));\
	MTL_QOCR2_WR(v);\
} while (0)

#define MTL_QOCR2_MISPKTCNT_RD(data) do {\
	MTL_QOCR2_RD(data);\
	data = ((data >> 16) & MTL_QOCR2_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR2_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR2_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR2_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR2_RD(v);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR2_MASK_12))<<12);\
	v = (v & (MTL_QOCR2_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR2_MASK_28))<<28);\
	v = ((v & MTL_QOCR2_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR2_MISCNTOVF_MASK)<<27));\
	MTL_QOCR2_WR(v);\
} while (0)

#define MTL_QOCR2_MISCNTOVF_RD(data) do {\
	MTL_QOCR2_RD(data);\
	data = ((data >> 27) & MTL_QOCR2_MISCNTOVF_MASK);\
} while (0)

#define MTL_QOCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd74))

#define MTL_QOCR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QOCR1_OFFSET);\
} while (0)

#define MTL_QOCR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QOCR1_OFFSET);\
} while (0)


#define  MTL_QOCR1_MASK_12 (ULONG)(0xf)


#define MTL_QOCR1_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MTL_QOCR1_MASK_28 (ULONG)(0xf)


#define MTL_QOCR1_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define MTL_QOCR1_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR1_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR1_OVFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR1_RD(v);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR1_MASK_12))<<12);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR1_MASK_28))<<28);\
	v = ((v & MTL_QOCR1_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR1_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR1_WR(v);\
} while (0)

#define MTL_QOCR1_OVFPKTCNT_RD(data) do {\
	MTL_QOCR1_RD(data);\
	data = ((data >> 0) & MTL_QOCR1_OVFPKTCNT_MASK);\
} while (0)


#define MTL_QOCR1_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR1_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR1_OVFCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR1_RD(v);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR1_MASK_12))<<12);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR1_MASK_28))<<28);\
	v = ((v & MTL_QOCR1_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR1_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR1_WR(v);\
} while (0)

#define MTL_QOCR1_OVFCNTOVF_RD(data) do {\
	MTL_QOCR1_RD(data);\
	data = ((data >> 11) & MTL_QOCR1_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR1_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR1_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR1_MISPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QOCR1_RD(v);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR1_MASK_12))<<12);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR1_MASK_28))<<28);\
	v = ((v & MTL_QOCR1_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR1_MISPKTCNT_MASK)<<16));\
	MTL_QOCR1_WR(v);\
} while (0)

#define MTL_QOCR1_MISPKTCNT_RD(data) do {\
	MTL_QOCR1_RD(data);\
	data = ((data >> 16) & MTL_QOCR1_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR1_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR1_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR1_MISCNTOVF_WR(data) do {\
	ULONG v;\
	MTL_QOCR1_RD(v);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR1_MASK_12))<<12);\
	v = (v & (MTL_QOCR1_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR1_MASK_28))<<28);\
	v = ((v & MTL_QOCR1_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR1_MISCNTOVF_MASK)<<27));\
	MTL_QOCR1_WR(v);\
} while (0)

#define MTL_QOCR1_MISCNTOVF_RD(data) do {\
	MTL_QOCR1_RD(data);\
	data = ((data >> 27) & MTL_QOCR1_MISCNTOVF_MASK);\
} while (0)

#define MTL_QLCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xee4))

#define MTL_QLCR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR7_OFFSET);\
} while (0)

#define MTL_QLCR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR7_OFFSET);\
} while (0)


#define  MTL_QLCR7_MASK_29 (ULONG)(0x7)


#define MTL_QLCR7_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR7_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR7_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR7_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR7_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR7_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR7_LC_WR_MASK)\
	|((data & MTL_QLCR7_LC_MASK)<<0));\
	MTL_QLCR7_WR(v);\
} while (0)

#define MTL_QLCR7_LC_RD(data) do {\
	MTL_QLCR7_RD(data);\
	data = ((data >> 0) & MTL_QLCR7_LC_MASK);\
} while (0)

#define MTL_QLCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xea4))

#define MTL_QLCR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR6_OFFSET);\
} while (0)

#define MTL_QLCR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR6_OFFSET);\
} while (0)


#define  MTL_QLCR6_MASK_29 (ULONG)(0x7)


#define MTL_QLCR6_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR6_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR6_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR6_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR6_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR6_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR6_LC_WR_MASK)\
	|((data & MTL_QLCR6_LC_MASK)<<0));\
	MTL_QLCR6_WR(v);\
} while (0)

#define MTL_QLCR6_LC_RD(data) do {\
	MTL_QLCR6_RD(data);\
	data = ((data >> 0) & MTL_QLCR6_LC_MASK);\
} while (0)

#define MTL_QLCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe64))

#define MTL_QLCR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR5_OFFSET);\
} while (0)

#define MTL_QLCR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR5_OFFSET);\
} while (0)


#define  MTL_QLCR5_MASK_29 (ULONG)(0x7)


#define MTL_QLCR5_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR5_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR5_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR5_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR5_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR5_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR5_LC_WR_MASK)\
	|((data & MTL_QLCR5_LC_MASK)<<0));\
	MTL_QLCR5_WR(v);\
} while (0)

#define MTL_QLCR5_LC_RD(data) do {\
	MTL_QLCR5_RD(data);\
	data = ((data >> 0) & MTL_QLCR5_LC_MASK);\
} while (0)

#define MTL_QLCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe24))

#define MTL_QLCR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR4_OFFSET);\
} while (0)

#define MTL_QLCR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR4_OFFSET);\
} while (0)


#define  MTL_QLCR4_MASK_29 (ULONG)(0x7)


#define MTL_QLCR4_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR4_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR4_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR4_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR4_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR4_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR4_LC_WR_MASK)\
	|((data & MTL_QLCR4_LC_MASK)<<0));\
	MTL_QLCR4_WR(v);\
} while (0)

#define MTL_QLCR4_LC_RD(data) do {\
	MTL_QLCR4_RD(data);\
	data = ((data >> 0) & MTL_QLCR4_LC_MASK);\
} while (0)

#define MTL_QLCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xde4))

#define MTL_QLCR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR3_OFFSET);\
} while (0)

#define MTL_QLCR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR3_OFFSET);\
} while (0)


#define  MTL_QLCR3_MASK_29 (ULONG)(0x7)


#define MTL_QLCR3_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR3_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR3_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR3_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR3_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR3_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR3_LC_WR_MASK)\
	|((data & MTL_QLCR3_LC_MASK)<<0));\
	MTL_QLCR3_WR(v);\
} while (0)

#define MTL_QLCR3_LC_RD(data) do {\
	MTL_QLCR3_RD(data);\
	data = ((data >> 0) & MTL_QLCR3_LC_MASK);\
} while (0)

#define MTL_QLCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xda4))

#define MTL_QLCR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR2_OFFSET);\
} while (0)

#define MTL_QLCR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR2_OFFSET);\
} while (0)


#define  MTL_QLCR2_MASK_29 (ULONG)(0x7)


#define MTL_QLCR2_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR2_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR2_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR2_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR2_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR2_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR2_LC_WR_MASK)\
	|((data & MTL_QLCR2_LC_MASK)<<0));\
	MTL_QLCR2_WR(v);\
} while (0)

#define MTL_QLCR2_LC_RD(data) do {\
	MTL_QLCR2_RD(data);\
	data = ((data >> 0) & MTL_QLCR2_LC_MASK);\
} while (0)

#define MTL_QLCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd64))

#define MTL_QLCR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QLCR1_OFFSET);\
} while (0)

#define MTL_QLCR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QLCR1_OFFSET);\
} while (0)


#define  MTL_QLCR1_MASK_29 (ULONG)(0x7)


#define MTL_QLCR1_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR1_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR1_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR1_LC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR1_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR1_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR1_LC_WR_MASK)\
	|((data & MTL_QLCR1_LC_MASK)<<0));\
	MTL_QLCR1_WR(v);\
} while (0)

#define MTL_QLCR1_LC_RD(data) do {\
	MTL_QLCR1_RD(data);\
	data = ((data >> 0) & MTL_QLCR1_LC_MASK);\
} while (0)

#define MTL_QHCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xee0))

#define MTL_QHCR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR7_OFFSET);\
} while (0)

#define MTL_QHCR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR7_OFFSET);\
} while (0)


#define  MTL_QHCR7_MASK_29 (ULONG)(0x7)


#define MTL_QHCR7_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR7_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR7_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR7_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR7_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR7_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR7_HC_WR_MASK)\
	|((data & MTL_QHCR7_HC_MASK)<<0));\
	MTL_QHCR7_WR(v);\
} while (0)

#define MTL_QHCR7_HC_RD(data) do {\
	MTL_QHCR7_RD(data);\
	data = ((data >> 0) & MTL_QHCR7_HC_MASK);\
} while (0)

#define MTL_QHCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xea0))

#define MTL_QHCR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR6_OFFSET);\
} while (0)

#define MTL_QHCR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR6_OFFSET);\
} while (0)


#define  MTL_QHCR6_MASK_29 (ULONG)(0x7)


#define MTL_QHCR6_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR6_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR6_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR6_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR6_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR6_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR6_HC_WR_MASK)\
	|((data & MTL_QHCR6_HC_MASK)<<0));\
	MTL_QHCR6_WR(v);\
} while (0)

#define MTL_QHCR6_HC_RD(data) do {\
	MTL_QHCR6_RD(data);\
	data = ((data >> 0) & MTL_QHCR6_HC_MASK);\
} while (0)

#define MTL_QHCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe60))

#define MTL_QHCR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR5_OFFSET);\
} while (0)

#define MTL_QHCR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR5_OFFSET);\
} while (0)


#define  MTL_QHCR5_MASK_29 (ULONG)(0x7)


#define MTL_QHCR5_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR5_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR5_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR5_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR5_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR5_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR5_HC_WR_MASK)\
	|((data & MTL_QHCR5_HC_MASK)<<0));\
	MTL_QHCR5_WR(v);\
} while (0)

#define MTL_QHCR5_HC_RD(data) do {\
	MTL_QHCR5_RD(data);\
	data = ((data >> 0) & MTL_QHCR5_HC_MASK);\
} while (0)

#define MTL_QHCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe20))

#define MTL_QHCR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR4_OFFSET);\
} while (0)

#define MTL_QHCR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR4_OFFSET);\
} while (0)


#define  MTL_QHCR4_MASK_29 (ULONG)(0x7)


#define MTL_QHCR4_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR4_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR4_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR4_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR4_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR4_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR4_HC_WR_MASK)\
	|((data & MTL_QHCR4_HC_MASK)<<0));\
	MTL_QHCR4_WR(v);\
} while (0)

#define MTL_QHCR4_HC_RD(data) do {\
	MTL_QHCR4_RD(data);\
	data = ((data >> 0) & MTL_QHCR4_HC_MASK);\
} while (0)

#define MTL_QHCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xde0))

#define MTL_QHCR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR3_OFFSET);\
} while (0)

#define MTL_QHCR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR3_OFFSET);\
} while (0)


#define  MTL_QHCR3_MASK_29 (ULONG)(0x7)


#define MTL_QHCR3_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR3_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR3_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR3_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR3_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR3_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR3_HC_WR_MASK)\
	|((data & MTL_QHCR3_HC_MASK)<<0));\
	MTL_QHCR3_WR(v);\
} while (0)

#define MTL_QHCR3_HC_RD(data) do {\
	MTL_QHCR3_RD(data);\
	data = ((data >> 0) & MTL_QHCR3_HC_MASK);\
} while (0)

#define MTL_QHCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xda0))

#define MTL_QHCR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR2_OFFSET);\
} while (0)

#define MTL_QHCR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR2_OFFSET);\
} while (0)


#define  MTL_QHCR2_MASK_29 (ULONG)(0x7)


#define MTL_QHCR2_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR2_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR2_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR2_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR2_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR2_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR2_HC_WR_MASK)\
	|((data & MTL_QHCR2_HC_MASK)<<0));\
	MTL_QHCR2_WR(v);\
} while (0)

#define MTL_QHCR2_HC_RD(data) do {\
	MTL_QHCR2_RD(data);\
	data = ((data >> 0) & MTL_QHCR2_HC_MASK);\
} while (0)

#define MTL_QHCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd60))

#define MTL_QHCR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QHCR1_OFFSET);\
} while (0)

#define MTL_QHCR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QHCR1_OFFSET);\
} while (0)


#define  MTL_QHCR1_MASK_29 (ULONG)(0x7)


#define MTL_QHCR1_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR1_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR1_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR1_HC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR1_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR1_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR1_HC_WR_MASK)\
	|((data & MTL_QHCR1_HC_MASK)<<0));\
	MTL_QHCR1_WR(v);\
} while (0)

#define MTL_QHCR1_HC_RD(data) do {\
	MTL_QHCR1_RD(data);\
	data = ((data >> 0) & MTL_QHCR1_HC_MASK);\
} while (0)

#define MTL_QSSCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xedc))

#define MTL_QSSCR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR7_OFFSET);\
} while (0)

#define MTL_QSSCR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR7_OFFSET);\
} while (0)


#define  MTL_QSSCR7_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR7_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR7_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR7_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR7_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR7_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR7_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR7_SSC_WR_MASK)\
	|((data & MTL_QSSCR7_SSC_MASK)<<0));\
	MTL_QSSCR7_WR(v);\
} while (0)

#define MTL_QSSCR7_SSC_RD(data) do {\
	MTL_QSSCR7_RD(data);\
	data = ((data >> 0) & MTL_QSSCR7_SSC_MASK);\
} while (0)

#define MTL_QSSCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe9c))

#define MTL_QSSCR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR6_OFFSET);\
} while (0)

#define MTL_QSSCR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR6_OFFSET);\
} while (0)


#define  MTL_QSSCR6_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR6_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR6_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR6_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR6_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR6_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR6_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR6_SSC_WR_MASK)\
	|((data & MTL_QSSCR6_SSC_MASK)<<0));\
	MTL_QSSCR6_WR(v);\
} while (0)

#define MTL_QSSCR6_SSC_RD(data) do {\
	MTL_QSSCR6_RD(data);\
	data = ((data >> 0) & MTL_QSSCR6_SSC_MASK);\
} while (0)

#define MTL_QSSCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe5c))

#define MTL_QSSCR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR5_OFFSET);\
} while (0)

#define MTL_QSSCR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR5_OFFSET);\
} while (0)


#define  MTL_QSSCR5_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR5_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR5_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR5_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR5_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR5_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR5_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR5_SSC_WR_MASK)\
	|((data & MTL_QSSCR5_SSC_MASK)<<0));\
	MTL_QSSCR5_WR(v);\
} while (0)

#define MTL_QSSCR5_SSC_RD(data) do {\
	MTL_QSSCR5_RD(data);\
	data = ((data >> 0) & MTL_QSSCR5_SSC_MASK);\
} while (0)

#define MTL_QSSCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe1c))

#define MTL_QSSCR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR4_OFFSET);\
} while (0)

#define MTL_QSSCR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR4_OFFSET);\
} while (0)


#define  MTL_QSSCR4_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR4_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR4_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR4_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR4_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR4_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR4_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR4_SSC_WR_MASK)\
	|((data & MTL_QSSCR4_SSC_MASK)<<0));\
	MTL_QSSCR4_WR(v);\
} while (0)

#define MTL_QSSCR4_SSC_RD(data) do {\
	MTL_QSSCR4_RD(data);\
	data = ((data >> 0) & MTL_QSSCR4_SSC_MASK);\
} while (0)

#define MTL_QSSCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xddc))

#define MTL_QSSCR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR3_OFFSET);\
} while (0)

#define MTL_QSSCR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR3_OFFSET);\
} while (0)


#define  MTL_QSSCR3_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR3_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR3_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR3_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR3_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR3_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR3_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR3_SSC_WR_MASK)\
	|((data & MTL_QSSCR3_SSC_MASK)<<0));\
	MTL_QSSCR3_WR(v);\
} while (0)

#define MTL_QSSCR3_SSC_RD(data) do {\
	MTL_QSSCR3_RD(data);\
	data = ((data >> 0) & MTL_QSSCR3_SSC_MASK);\
} while (0)

#define MTL_QSSCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd9c))

#define MTL_QSSCR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR2_OFFSET);\
} while (0)

#define MTL_QSSCR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR2_OFFSET);\
} while (0)


#define  MTL_QSSCR2_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR2_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR2_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR2_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR2_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR2_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR2_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR2_SSC_WR_MASK)\
	|((data & MTL_QSSCR2_SSC_MASK)<<0));\
	MTL_QSSCR2_WR(v);\
} while (0)

#define MTL_QSSCR2_SSC_RD(data) do {\
	MTL_QSSCR2_RD(data);\
	data = ((data >> 0) & MTL_QSSCR2_SSC_MASK);\
} while (0)

#define MTL_QSSCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd5c))

#define MTL_QSSCR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QSSCR1_OFFSET);\
} while (0)

#define MTL_QSSCR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QSSCR1_OFFSET);\
} while (0)


#define  MTL_QSSCR1_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR1_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR1_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR1_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR1_SSC_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR1_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR1_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR1_SSC_WR_MASK)\
	|((data & MTL_QSSCR1_SSC_MASK)<<0));\
	MTL_QSSCR1_WR(v);\
} while (0)

#define MTL_QSSCR1_SSC_RD(data) do {\
	MTL_QSSCR1_RD(data);\
	data = ((data >> 0) & MTL_QSSCR1_SSC_MASK);\
} while (0)

#define MTL_QW7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xed8))

#define MTL_QW7_WR(data) do {\
	iowrite32(data, (void *)MTL_QW7_OFFSET);\
} while (0)

#define MTL_QW7_RD(data) do {\
	(data) = ioread32((void *)MTL_QW7_OFFSET);\
} while (0)


#define  MTL_QW7_MASK_21 (ULONG)(0x7ff)


#define MTL_QW7_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW7_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW7_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW7_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW7_RES_WR_MASK_21))\
	|(((0) & (MTL_QW7_MASK_21))<<21);\
	(v) = ((v & MTL_QW7_ISCQW_WR_MASK)\
	|((data & MTL_QW7_ISCQW_MASK)<<0));\
	MTL_QW7_WR(v);\
} while (0)

#define MTL_QW7_ISCQW_RD(data) do {\
	MTL_QW7_RD(data);\
	data = ((data >> 0) & MTL_QW7_ISCQW_MASK);\
} while (0)

#define MTL_QW6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe98))

#define MTL_QW6_WR(data) do {\
	iowrite32(data, (void *)MTL_QW6_OFFSET);\
} while (0)

#define MTL_QW6_RD(data) do {\
	(data) = ioread32((void *)MTL_QW6_OFFSET);\
} while (0)


#define  MTL_QW6_MASK_21 (ULONG)(0x7ff)


#define MTL_QW6_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW6_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW6_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW6_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW6_RES_WR_MASK_21))\
	|(((0) & (MTL_QW6_MASK_21))<<21);\
	(v) = ((v & MTL_QW6_ISCQW_WR_MASK)\
	|((data & MTL_QW6_ISCQW_MASK)<<0));\
	MTL_QW6_WR(v);\
} while (0)

#define MTL_QW6_ISCQW_RD(data) do {\
	MTL_QW6_RD(data);\
	data = ((data >> 0) & MTL_QW6_ISCQW_MASK);\
} while (0)

#define MTL_QW5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe58))

#define MTL_QW5_WR(data) do {\
	iowrite32(data, (void *)MTL_QW5_OFFSET);\
} while (0)

#define MTL_QW5_RD(data) do {\
	(data) = ioread32((void *)MTL_QW5_OFFSET);\
} while (0)


#define  MTL_QW5_MASK_21 (ULONG)(0x7ff)


#define MTL_QW5_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW5_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW5_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW5_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW5_RES_WR_MASK_21))\
	|(((0) & (MTL_QW5_MASK_21))<<21);\
	(v) = ((v & MTL_QW5_ISCQW_WR_MASK)\
	|((data & MTL_QW5_ISCQW_MASK)<<0));\
	MTL_QW5_WR(v);\
} while (0)

#define MTL_QW5_ISCQW_RD(data) do {\
	MTL_QW5_RD(data);\
	data = ((data >> 0) & MTL_QW5_ISCQW_MASK);\
} while (0)

#define MTL_QW4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe18))

#define MTL_QW4_WR(data) do {\
	iowrite32(data, (void *)MTL_QW4_OFFSET);\
} while (0)

#define MTL_QW4_RD(data) do {\
	(data) = ioread32((void *)MTL_QW4_OFFSET);\
} while (0)


#define  MTL_QW4_MASK_21 (ULONG)(0x7ff)


#define MTL_QW4_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW4_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW4_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW4_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW4_RES_WR_MASK_21))\
	|(((0) & (MTL_QW4_MASK_21))<<21);\
	(v) = ((v & MTL_QW4_ISCQW_WR_MASK)\
	|((data & MTL_QW4_ISCQW_MASK)<<0));\
	MTL_QW4_WR(v);\
} while (0)

#define MTL_QW4_ISCQW_RD(data) do {\
	MTL_QW4_RD(data);\
	data = ((data >> 0) & MTL_QW4_ISCQW_MASK);\
} while (0)

#define MTL_QW3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdd8))

#define MTL_QW3_WR(data) do {\
	iowrite32(data, (void *)MTL_QW3_OFFSET);\
} while (0)

#define MTL_QW3_RD(data) do {\
	(data) = ioread32((void *)MTL_QW3_OFFSET);\
} while (0)


#define  MTL_QW3_MASK_21 (ULONG)(0x7ff)


#define MTL_QW3_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW3_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW3_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW3_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW3_RES_WR_MASK_21))\
	|(((0) & (MTL_QW3_MASK_21))<<21);\
	(v) = ((v & MTL_QW3_ISCQW_WR_MASK)\
	|((data & MTL_QW3_ISCQW_MASK)<<0));\
	MTL_QW3_WR(v);\
} while (0)

#define MTL_QW3_ISCQW_RD(data) do {\
	MTL_QW3_RD(data);\
	data = ((data >> 0) & MTL_QW3_ISCQW_MASK);\
} while (0)

#define MTL_QW2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd98))

#define MTL_QW2_WR(data) do {\
	iowrite32(data, (void *)MTL_QW2_OFFSET);\
} while (0)

#define MTL_QW2_RD(data) do {\
	(data) = ioread32((void *)MTL_QW2_OFFSET);\
} while (0)


#define  MTL_QW2_MASK_21 (ULONG)(0x7ff)


#define MTL_QW2_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW2_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW2_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW2_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW2_RES_WR_MASK_21))\
	|(((0) & (MTL_QW2_MASK_21))<<21);\
	(v) = ((v & MTL_QW2_ISCQW_WR_MASK)\
	|((data & MTL_QW2_ISCQW_MASK)<<0));\
	MTL_QW2_WR(v);\
} while (0)

#define MTL_QW2_ISCQW_RD(data) do {\
	MTL_QW2_RD(data);\
	data = ((data >> 0) & MTL_QW2_ISCQW_MASK);\
} while (0)

#define MTL_QW1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd58))

#define MTL_QW1_WR(data) do {\
	iowrite32(data, (void *)MTL_QW1_OFFSET);\
} while (0)

#define MTL_QW1_RD(data) do {\
	(data) = ioread32((void *)MTL_QW1_OFFSET);\
} while (0)


#define  MTL_QW1_MASK_21 (ULONG)(0x7ff)


#define MTL_QW1_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW1_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW1_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW1_ISCQW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW1_RES_WR_MASK_21))\
	|(((0) & (MTL_QW1_MASK_21))<<21);\
	(v) = ((v & MTL_QW1_ISCQW_WR_MASK)\
	|((data & MTL_QW1_ISCQW_MASK)<<0));\
	MTL_QW1_WR(v);\
} while (0)

#define MTL_QW1_ISCQW_RD(data) do {\
	MTL_QW1_RD(data);\
	data = ((data >> 0) & MTL_QW1_ISCQW_MASK);\
} while (0)

#define MTL_QESR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xed4))

#define MTL_QESR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR7_OFFSET);\
} while (0)


#define MTL_QESR7_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR7_ABS_RD(data) do {\
	MTL_QESR7_RD(data);\
	data = ((data >> 0) & MTL_QESR7_ABS_MASK);\
} while (0)


#define MTL_QESR7_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR7_ABSU_RD(data) do {\
	MTL_QESR7_RD(data);\
	data = ((data >> 24) & MTL_QESR7_ABSU_MASK);\
} while (0)

#define MTL_QESR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe94))

#define MTL_QESR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR6_OFFSET);\
} while (0)


#define MTL_QESR6_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR6_ABS_RD(data) do {\
	MTL_QESR6_RD(data);\
	data = ((data >> 0) & MTL_QESR6_ABS_MASK);\
} while (0)


#define MTL_QESR6_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR6_ABSU_RD(data) do {\
	MTL_QESR6_RD(data);\
	data = ((data >> 24) & MTL_QESR6_ABSU_MASK);\
} while (0)

#define MTL_QESR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe54))

#define MTL_QESR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR5_OFFSET);\
} while (0)


#define MTL_QESR5_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR5_ABS_RD(data) do {\
	MTL_QESR5_RD(data);\
	data = ((data >> 0) & MTL_QESR5_ABS_MASK);\
} while (0)


#define MTL_QESR5_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR5_ABSU_RD(data) do {\
	MTL_QESR5_RD(data);\
	data = ((data >> 24) & MTL_QESR5_ABSU_MASK);\
} while (0)

#define MTL_QESR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe14))

#define MTL_QESR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR4_OFFSET);\
} while (0)


#define MTL_QESR4_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR4_ABS_RD(data) do {\
	MTL_QESR4_RD(data);\
	data = ((data >> 0) & MTL_QESR4_ABS_MASK);\
} while (0)


#define MTL_QESR4_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR4_ABSU_RD(data) do {\
	MTL_QESR4_RD(data);\
	data = ((data >> 24) & MTL_QESR4_ABSU_MASK);\
} while (0)

#define MTL_QESR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdd4))

#define MTL_QESR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR3_OFFSET);\
} while (0)


#define MTL_QESR3_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR3_ABS_RD(data) do {\
	MTL_QESR3_RD(data);\
	data = ((data >> 0) & MTL_QESR3_ABS_MASK);\
} while (0)


#define MTL_QESR3_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR3_ABSU_RD(data) do {\
	MTL_QESR3_RD(data);\
	data = ((data >> 24) & MTL_QESR3_ABSU_MASK);\
} while (0)

#define MTL_QESR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd94))

#define MTL_QESR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR2_OFFSET);\
} while (0)


#define MTL_QESR2_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR2_ABS_RD(data) do {\
	MTL_QESR2_RD(data);\
	data = ((data >> 0) & MTL_QESR2_ABS_MASK);\
} while (0)


#define MTL_QESR2_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR2_ABSU_RD(data) do {\
	MTL_QESR2_RD(data);\
	data = ((data >> 24) & MTL_QESR2_ABSU_MASK);\
} while (0)

#define MTL_QESR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd54))

#define MTL_QESR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QESR1_OFFSET);\
} while (0)


#define MTL_QESR1_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR1_ABS_RD(data) do {\
	MTL_QESR1_RD(data);\
	data = ((data >> 0) & MTL_QESR1_ABS_MASK);\
} while (0)


#define MTL_QESR1_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR1_ABSU_RD(data) do {\
	MTL_QESR1_RD(data);\
	data = ((data >> 24) & MTL_QESR1_ABSU_MASK);\
} while (0)

#define MTL_QECR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xed0))

#define MTL_QECR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR7_OFFSET);\
} while (0)

#define MTL_QECR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR7_OFFSET);\
} while (0)


#define  MTL_QECR7_MASK_0 (ULONG)(0x3)


#define MTL_QECR7_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR7_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR7_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR7_MASK_25 (ULONG)(0x7f)


#define MTL_QECR7_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR7_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR7_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR7_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR7_RD(v);\
	v = (v & (MTL_QECR7_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR7_MASK_0))<<0);\
	v = (v & (MTL_QECR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR7_MASK_7))<<7);\
	v = (v & (MTL_QECR7_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR7_MASK_25))<<25);\
	v = ((v & MTL_QECR7_AVALG_WR_MASK)\
	|((data & MTL_QECR7_AVALG_MASK)<<2));\
	MTL_QECR7_WR(v);\
} while (0)

#define MTL_QECR7_AVALG_RD(data) do {\
	MTL_QECR7_RD(data);\
	data = ((data >> 2) & MTL_QECR7_AVALG_MASK);\
} while (0)


#define MTL_QECR7_CC_MASK (ULONG)(0x1)


#define MTL_QECR7_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR7_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR7_RD(v);\
	v = (v & (MTL_QECR7_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR7_MASK_0))<<0);\
	v = (v & (MTL_QECR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR7_MASK_7))<<7);\
	v = (v & (MTL_QECR7_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR7_MASK_25))<<25);\
	v = ((v & MTL_QECR7_CC_WR_MASK)\
	|((data & MTL_QECR7_CC_MASK)<<3));\
	MTL_QECR7_WR(v);\
} while (0)

#define MTL_QECR7_CC_RD(data) do {\
	MTL_QECR7_RD(data);\
	data = ((data >> 3) & MTL_QECR7_CC_MASK);\
} while (0)


#define MTL_QECR7_SLC_MASK (ULONG)(0x7)


#define MTL_QECR7_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR7_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR7_RD(v);\
	v = (v & (MTL_QECR7_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR7_MASK_0))<<0);\
	v = (v & (MTL_QECR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR7_MASK_7))<<7);\
	v = (v & (MTL_QECR7_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR7_MASK_25))<<25);\
	v = ((v & MTL_QECR7_SLC_WR_MASK)\
	|((data & MTL_QECR7_SLC_MASK)<<4));\
	MTL_QECR7_WR(v);\
} while (0)

#define MTL_QECR7_SLC_RD(data) do {\
	MTL_QECR7_RD(data);\
	data = ((data >> 4) & MTL_QECR7_SLC_MASK);\
} while (0)


#define MTL_QECR7_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR7_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR7_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR7_RD(v);\
	v = (v & (MTL_QECR7_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR7_MASK_0))<<0);\
	v = (v & (MTL_QECR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR7_MASK_7))<<7);\
	v = (v & (MTL_QECR7_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR7_MASK_25))<<25);\
	v = ((v & MTL_QECR7_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR7_ABPSSIE_MASK)<<24));\
	MTL_QECR7_WR(v);\
} while (0)

#define MTL_QECR7_ABPSSIE_RD(data) do {\
	MTL_QECR7_RD(data);\
	data = ((data >> 24) & MTL_QECR7_ABPSSIE_MASK);\
} while (0)

#define MTL_QECR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe90))

#define MTL_QECR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR6_OFFSET);\
} while (0)

#define MTL_QECR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR6_OFFSET);\
} while (0)


#define  MTL_QECR6_MASK_0 (ULONG)(0x3)


#define MTL_QECR6_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR6_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR6_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR6_MASK_25 (ULONG)(0x7f)


#define MTL_QECR6_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR6_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR6_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR6_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR6_RD(v);\
	v = (v & (MTL_QECR6_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR6_MASK_0))<<0);\
	v = (v & (MTL_QECR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR6_MASK_7))<<7);\
	v = (v & (MTL_QECR6_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR6_MASK_25))<<25);\
	v = ((v & MTL_QECR6_AVALG_WR_MASK)\
	|((data & MTL_QECR6_AVALG_MASK)<<2));\
	MTL_QECR6_WR(v);\
} while (0)

#define MTL_QECR6_AVALG_RD(data) do {\
	MTL_QECR6_RD(data);\
	data = ((data >> 2) & MTL_QECR6_AVALG_MASK);\
} while (0)


#define MTL_QECR6_CC_MASK (ULONG)(0x1)


#define MTL_QECR6_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR6_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR6_RD(v);\
	v = (v & (MTL_QECR6_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR6_MASK_0))<<0);\
	v = (v & (MTL_QECR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR6_MASK_7))<<7);\
	v = (v & (MTL_QECR6_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR6_MASK_25))<<25);\
	v = ((v & MTL_QECR6_CC_WR_MASK)\
	|((data & MTL_QECR6_CC_MASK)<<3));\
	MTL_QECR6_WR(v);\
} while (0)

#define MTL_QECR6_CC_RD(data) do {\
	MTL_QECR6_RD(data);\
	data = ((data >> 3) & MTL_QECR6_CC_MASK);\
} while (0)


#define MTL_QECR6_SLC_MASK (ULONG)(0x7)


#define MTL_QECR6_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR6_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR6_RD(v);\
	v = (v & (MTL_QECR6_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR6_MASK_0))<<0);\
	v = (v & (MTL_QECR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR6_MASK_7))<<7);\
	v = (v & (MTL_QECR6_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR6_MASK_25))<<25);\
	v = ((v & MTL_QECR6_SLC_WR_MASK)\
	|((data & MTL_QECR6_SLC_MASK)<<4));\
	MTL_QECR6_WR(v);\
} while (0)

#define MTL_QECR6_SLC_RD(data) do {\
	MTL_QECR6_RD(data);\
	data = ((data >> 4) & MTL_QECR6_SLC_MASK);\
} while (0)


#define MTL_QECR6_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR6_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR6_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR6_RD(v);\
	v = (v & (MTL_QECR6_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR6_MASK_0))<<0);\
	v = (v & (MTL_QECR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR6_MASK_7))<<7);\
	v = (v & (MTL_QECR6_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR6_MASK_25))<<25);\
	v = ((v & MTL_QECR6_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR6_ABPSSIE_MASK)<<24));\
	MTL_QECR6_WR(v);\
} while (0)

#define MTL_QECR6_ABPSSIE_RD(data) do {\
	MTL_QECR6_RD(data);\
	data = ((data >> 24) & MTL_QECR6_ABPSSIE_MASK);\
} while (0)

#define MTL_QECR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe50))

#define MTL_QECR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR5_OFFSET);\
} while (0)

#define MTL_QECR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR5_OFFSET);\
} while (0)


#define  MTL_QECR5_MASK_0 (ULONG)(0x3)


#define MTL_QECR5_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR5_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR5_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR5_MASK_25 (ULONG)(0x7f)


#define MTL_QECR5_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR5_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR5_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR5_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR5_RD(v);\
	v = (v & (MTL_QECR5_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR5_MASK_0))<<0);\
	v = (v & (MTL_QECR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR5_MASK_7))<<7);\
	v = (v & (MTL_QECR5_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR5_MASK_25))<<25);\
	v = ((v & MTL_QECR5_AVALG_WR_MASK)\
	|((data & MTL_QECR5_AVALG_MASK)<<2));\
	MTL_QECR5_WR(v);\
} while (0)

#define MTL_QECR5_AVALG_RD(data) do {\
	MTL_QECR5_RD(data);\
	data = ((data >> 2) & MTL_QECR5_AVALG_MASK);\
} while (0)


#define MTL_QECR5_CC_MASK (ULONG)(0x1)


#define MTL_QECR5_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR5_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR5_RD(v);\
	v = (v & (MTL_QECR5_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR5_MASK_0))<<0);\
	v = (v & (MTL_QECR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR5_MASK_7))<<7);\
	v = (v & (MTL_QECR5_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR5_MASK_25))<<25);\
	v = ((v & MTL_QECR5_CC_WR_MASK)\
	|((data & MTL_QECR5_CC_MASK)<<3));\
	MTL_QECR5_WR(v);\
} while (0)

#define MTL_QECR5_CC_RD(data) do {\
	MTL_QECR5_RD(data);\
	data = ((data >> 3) & MTL_QECR5_CC_MASK);\
} while (0)


#define MTL_QECR5_SLC_MASK (ULONG)(0x7)


#define MTL_QECR5_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR5_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR5_RD(v);\
	v = (v & (MTL_QECR5_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR5_MASK_0))<<0);\
	v = (v & (MTL_QECR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR5_MASK_7))<<7);\
	v = (v & (MTL_QECR5_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR5_MASK_25))<<25);\
	v = ((v & MTL_QECR5_SLC_WR_MASK)\
	|((data & MTL_QECR5_SLC_MASK)<<4));\
	MTL_QECR5_WR(v);\
} while (0)

#define MTL_QECR5_SLC_RD(data) do {\
	MTL_QECR5_RD(data);\
	data = ((data >> 4) & MTL_QECR5_SLC_MASK);\
} while (0)


#define MTL_QECR5_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR5_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR5_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR5_RD(v);\
	v = (v & (MTL_QECR5_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR5_MASK_0))<<0);\
	v = (v & (MTL_QECR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR5_MASK_7))<<7);\
	v = (v & (MTL_QECR5_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR5_MASK_25))<<25);\
	v = ((v & MTL_QECR5_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR5_ABPSSIE_MASK)<<24));\
	MTL_QECR5_WR(v);\
} while (0)

#define MTL_QECR5_ABPSSIE_RD(data) do {\
	MTL_QECR5_RD(data);\
	data = ((data >> 24) & MTL_QECR5_ABPSSIE_MASK);\
} while (0)

#define MTL_QECR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe10))

#define MTL_QECR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR4_OFFSET);\
} while (0)

#define MTL_QECR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR4_OFFSET);\
} while (0)


#define  MTL_QECR4_MASK_0 (ULONG)(0x3)


#define MTL_QECR4_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR4_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR4_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR4_MASK_25 (ULONG)(0x7f)


#define MTL_QECR4_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR4_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR4_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR4_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR4_RD(v);\
	v = (v & (MTL_QECR4_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR4_MASK_0))<<0);\
	v = (v & (MTL_QECR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR4_MASK_7))<<7);\
	v = (v & (MTL_QECR4_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR4_MASK_25))<<25);\
	v = ((v & MTL_QECR4_AVALG_WR_MASK)\
	|((data & MTL_QECR4_AVALG_MASK)<<2));\
	MTL_QECR4_WR(v);\
} while (0)

#define MTL_QECR4_AVALG_RD(data) do {\
	MTL_QECR4_RD(data);\
	data = ((data >> 2) & MTL_QECR4_AVALG_MASK);\
} while (0)


#define MTL_QECR4_CC_MASK (ULONG)(0x1)


#define MTL_QECR4_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR4_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR4_RD(v);\
	v = (v & (MTL_QECR4_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR4_MASK_0))<<0);\
	v = (v & (MTL_QECR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR4_MASK_7))<<7);\
	v = (v & (MTL_QECR4_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR4_MASK_25))<<25);\
	v = ((v & MTL_QECR4_CC_WR_MASK)\
	|((data & MTL_QECR4_CC_MASK)<<3));\
	MTL_QECR4_WR(v);\
} while (0)

#define MTL_QECR4_CC_RD(data) do {\
	MTL_QECR4_RD(data);\
	data = ((data >> 3) & MTL_QECR4_CC_MASK);\
} while (0)


#define MTL_QECR4_SLC_MASK (ULONG)(0x7)


#define MTL_QECR4_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR4_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR4_RD(v);\
	v = (v & (MTL_QECR4_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR4_MASK_0))<<0);\
	v = (v & (MTL_QECR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR4_MASK_7))<<7);\
	v = (v & (MTL_QECR4_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR4_MASK_25))<<25);\
	v = ((v & MTL_QECR4_SLC_WR_MASK)\
	|((data & MTL_QECR4_SLC_MASK)<<4));\
	MTL_QECR4_WR(v);\
} while (0)

#define MTL_QECR4_SLC_RD(data) do {\
	MTL_QECR4_RD(data);\
	data = ((data >> 4) & MTL_QECR4_SLC_MASK);\
} while (0)


#define MTL_QECR4_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR4_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR4_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR4_RD(v);\
	v = (v & (MTL_QECR4_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR4_MASK_0))<<0);\
	v = (v & (MTL_QECR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR4_MASK_7))<<7);\
	v = (v & (MTL_QECR4_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR4_MASK_25))<<25);\
	v = ((v & MTL_QECR4_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR4_ABPSSIE_MASK)<<24));\
	MTL_QECR4_WR(v);\
} while (0)

#define MTL_QECR4_ABPSSIE_RD(data) do {\
	MTL_QECR4_RD(data);\
	data = ((data >> 24) & MTL_QECR4_ABPSSIE_MASK);\
} while (0)

#define MTL_QECR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdd0))

#define MTL_QECR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR3_OFFSET);\
} while (0)

#define MTL_QECR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR3_OFFSET);\
} while (0)


#define  MTL_QECR3_MASK_0 (ULONG)(0x3)


#define MTL_QECR3_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR3_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR3_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR3_MASK_25 (ULONG)(0x7f)


#define MTL_QECR3_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR3_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR3_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR3_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR3_RD(v);\
	v = (v & (MTL_QECR3_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR3_MASK_0))<<0);\
	v = (v & (MTL_QECR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR3_MASK_7))<<7);\
	v = (v & (MTL_QECR3_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR3_MASK_25))<<25);\
	v = ((v & MTL_QECR3_AVALG_WR_MASK)\
	|((data & MTL_QECR3_AVALG_MASK)<<2));\
	MTL_QECR3_WR(v);\
} while (0)

#define MTL_QECR3_AVALG_RD(data) do {\
	MTL_QECR3_RD(data);\
	data = ((data >> 2) & MTL_QECR3_AVALG_MASK);\
} while (0)


#define MTL_QECR3_CC_MASK (ULONG)(0x1)


#define MTL_QECR3_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR3_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR3_RD(v);\
	v = (v & (MTL_QECR3_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR3_MASK_0))<<0);\
	v = (v & (MTL_QECR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR3_MASK_7))<<7);\
	v = (v & (MTL_QECR3_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR3_MASK_25))<<25);\
	v = ((v & MTL_QECR3_CC_WR_MASK)\
	|((data & MTL_QECR3_CC_MASK)<<3));\
	MTL_QECR3_WR(v);\
} while (0)

#define MTL_QECR3_CC_RD(data) do {\
	MTL_QECR3_RD(data);\
	data = ((data >> 3) & MTL_QECR3_CC_MASK);\
} while (0)


#define MTL_QECR3_SLC_MASK (ULONG)(0x7)


#define MTL_QECR3_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR3_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR3_RD(v);\
	v = (v & (MTL_QECR3_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR3_MASK_0))<<0);\
	v = (v & (MTL_QECR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR3_MASK_7))<<7);\
	v = (v & (MTL_QECR3_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR3_MASK_25))<<25);\
	v = ((v & MTL_QECR3_SLC_WR_MASK)\
	|((data & MTL_QECR3_SLC_MASK)<<4));\
	MTL_QECR3_WR(v);\
} while (0)

#define MTL_QECR3_SLC_RD(data) do {\
	MTL_QECR3_RD(data);\
	data = ((data >> 4) & MTL_QECR3_SLC_MASK);\
} while (0)


#define MTL_QECR3_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR3_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR3_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR3_RD(v);\
	v = (v & (MTL_QECR3_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR3_MASK_0))<<0);\
	v = (v & (MTL_QECR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR3_MASK_7))<<7);\
	v = (v & (MTL_QECR3_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR3_MASK_25))<<25);\
	v = ((v & MTL_QECR3_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR3_ABPSSIE_MASK)<<24));\
	MTL_QECR3_WR(v);\
} while (0)

#define MTL_QECR3_ABPSSIE_RD(data) do {\
	MTL_QECR3_RD(data);\
	data = ((data >> 24) & MTL_QECR3_ABPSSIE_MASK);\
} while (0)

#define MTL_QECR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd90))

#define MTL_QECR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR2_OFFSET);\
} while (0)

#define MTL_QECR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR2_OFFSET);\
} while (0)


#define  MTL_QECR2_MASK_0 (ULONG)(0x3)


#define MTL_QECR2_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR2_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR2_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR2_MASK_25 (ULONG)(0x7f)


#define MTL_QECR2_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR2_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR2_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR2_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR2_RD(v);\
	v = (v & (MTL_QECR2_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR2_MASK_0))<<0);\
	v = (v & (MTL_QECR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR2_MASK_7))<<7);\
	v = (v & (MTL_QECR2_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR2_MASK_25))<<25);\
	v = ((v & MTL_QECR2_AVALG_WR_MASK)\
	|((data & MTL_QECR2_AVALG_MASK)<<2));\
	MTL_QECR2_WR(v);\
} while (0)

#define MTL_QECR2_AVALG_RD(data) do {\
	MTL_QECR2_RD(data);\
	data = ((data >> 2) & MTL_QECR2_AVALG_MASK);\
} while (0)


#define MTL_QECR2_CC_MASK (ULONG)(0x1)


#define MTL_QECR2_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR2_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR2_RD(v);\
	v = (v & (MTL_QECR2_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR2_MASK_0))<<0);\
	v = (v & (MTL_QECR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR2_MASK_7))<<7);\
	v = (v & (MTL_QECR2_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR2_MASK_25))<<25);\
	v = ((v & MTL_QECR2_CC_WR_MASK)\
	|((data & MTL_QECR2_CC_MASK)<<3));\
	MTL_QECR2_WR(v);\
} while (0)

#define MTL_QECR2_CC_RD(data) do {\
	MTL_QECR2_RD(data);\
	data = ((data >> 3) & MTL_QECR2_CC_MASK);\
} while (0)


#define MTL_QECR2_SLC_MASK (ULONG)(0x7)


#define MTL_QECR2_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR2_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR2_RD(v);\
	v = (v & (MTL_QECR2_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR2_MASK_0))<<0);\
	v = (v & (MTL_QECR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR2_MASK_7))<<7);\
	v = (v & (MTL_QECR2_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR2_MASK_25))<<25);\
	v = ((v & MTL_QECR2_SLC_WR_MASK)\
	|((data & MTL_QECR2_SLC_MASK)<<4));\
	MTL_QECR2_WR(v);\
} while (0)

#define MTL_QECR2_SLC_RD(data) do {\
	MTL_QECR2_RD(data);\
	data = ((data >> 4) & MTL_QECR2_SLC_MASK);\
} while (0)


#define MTL_QECR2_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR2_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR2_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR2_RD(v);\
	v = (v & (MTL_QECR2_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR2_MASK_0))<<0);\
	v = (v & (MTL_QECR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR2_MASK_7))<<7);\
	v = (v & (MTL_QECR2_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR2_MASK_25))<<25);\
	v = ((v & MTL_QECR2_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR2_ABPSSIE_MASK)<<24));\
	MTL_QECR2_WR(v);\
} while (0)

#define MTL_QECR2_ABPSSIE_RD(data) do {\
	MTL_QECR2_RD(data);\
	data = ((data >> 24) & MTL_QECR2_ABPSSIE_MASK);\
} while (0)

#define MTL_QECR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd50))

#define MTL_QECR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QECR1_OFFSET);\
} while (0)

#define MTL_QECR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QECR1_OFFSET);\
} while (0)


#define  MTL_QECR1_MASK_0 (ULONG)(0x3)


#define MTL_QECR1_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define  MTL_QECR1_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR1_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR1_MASK_25 (ULONG)(0x7f)


#define MTL_QECR1_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MTL_QECR1_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR1_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR1_AVALG_WR(data) do {\
	ULONG v;\
	MTL_QECR1_RD(v);\
	v = (v & (MTL_QECR1_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR1_MASK_0))<<0);\
	v = (v & (MTL_QECR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR1_MASK_7))<<7);\
	v = (v & (MTL_QECR1_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR1_MASK_25))<<25);\
	v = ((v & MTL_QECR1_AVALG_WR_MASK)\
	|((data & MTL_QECR1_AVALG_MASK)<<2));\
	MTL_QECR1_WR(v);\
} while (0)

#define MTL_QECR1_AVALG_RD(data) do {\
	MTL_QECR1_RD(data);\
	data = ((data >> 2) & MTL_QECR1_AVALG_MASK);\
} while (0)


#define MTL_QECR1_CC_MASK (ULONG)(0x1)


#define MTL_QECR1_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR1_CC_WR(data) do {\
	ULONG v;\
	MTL_QECR1_RD(v);\
	v = (v & (MTL_QECR1_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR1_MASK_0))<<0);\
	v = (v & (MTL_QECR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR1_MASK_7))<<7);\
	v = (v & (MTL_QECR1_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR1_MASK_25))<<25);\
	v = ((v & MTL_QECR1_CC_WR_MASK)\
	|((data & MTL_QECR1_CC_MASK)<<3));\
	MTL_QECR1_WR(v);\
} while (0)

#define MTL_QECR1_CC_RD(data) do {\
	MTL_QECR1_RD(data);\
	data = ((data >> 3) & MTL_QECR1_CC_MASK);\
} while (0)


#define MTL_QECR1_SLC_MASK (ULONG)(0x7)


#define MTL_QECR1_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR1_SLC_WR(data) do {\
	ULONG v;\
	MTL_QECR1_RD(v);\
	v = (v & (MTL_QECR1_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR1_MASK_0))<<0);\
	v = (v & (MTL_QECR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR1_MASK_7))<<7);\
	v = (v & (MTL_QECR1_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR1_MASK_25))<<25);\
	v = ((v & MTL_QECR1_SLC_WR_MASK)\
	|((data & MTL_QECR1_SLC_MASK)<<4));\
	MTL_QECR1_WR(v);\
} while (0)

#define MTL_QECR1_SLC_RD(data) do {\
	MTL_QECR1_RD(data);\
	data = ((data >> 4) & MTL_QECR1_SLC_MASK);\
} while (0)


#define MTL_QECR1_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR1_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR1_ABPSSIE_WR(data) do {\
	ULONG v;\
	MTL_QECR1_RD(v);\
	v = (v & (MTL_QECR1_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR1_MASK_0))<<0);\
	v = (v & (MTL_QECR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR1_MASK_7))<<7);\
	v = (v & (MTL_QECR1_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR1_MASK_25))<<25);\
	v = ((v & MTL_QECR1_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR1_ABPSSIE_MASK)<<24));\
	MTL_QECR1_WR(v);\
} while (0)

#define MTL_QECR1_ABPSSIE_RD(data) do {\
	MTL_QECR1_RD(data);\
	data = ((data >> 24) & MTL_QECR1_ABPSSIE_MASK);\
} while (0)

#define MTL_QTDR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xec8))

#define MTL_QTDR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR7_OFFSET);\
} while (0)


#define MTL_QTDR7_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR7_TXQPAUSED_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 0) & MTL_QTDR7_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR7_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR7_TRCSTS_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 1) & MTL_QTDR7_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR7_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR7_TWCSTS_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 3) & MTL_QTDR7_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR7_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR7_TXQSTS_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 4) & MTL_QTDR7_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR7_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR7_TXSTSFSTS_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 5) & MTL_QTDR7_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR7_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR7_PTXQ_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 16) & MTL_QTDR7_PTXQ_MASK);\
} while (0)


#define MTL_QTDR7_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR7_STXSTSF_RD(data) do {\
	MTL_QTDR7_RD(data);\
	data = ((data >> 20) & MTL_QTDR7_STXSTSF_MASK);\
} while (0)

#define MTL_QTDR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe88))

#define MTL_QTDR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR6_OFFSET);\
} while (0)


#define MTL_QTDR6_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR6_TXQPAUSED_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 0) & MTL_QTDR6_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR6_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR6_TRCSTS_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 1) & MTL_QTDR6_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR6_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR6_TWCSTS_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 3) & MTL_QTDR6_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR6_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR6_TXQSTS_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 4) & MTL_QTDR6_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR6_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR6_TXSTSFSTS_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 5) & MTL_QTDR6_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR6_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR6_PTXQ_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 16) & MTL_QTDR6_PTXQ_MASK);\
} while (0)


#define MTL_QTDR6_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR6_STXSTSF_RD(data) do {\
	MTL_QTDR6_RD(data);\
	data = ((data >> 20) & MTL_QTDR6_STXSTSF_MASK);\
} while (0)

#define MTL_QTDR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe48))

#define MTL_QTDR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR5_OFFSET);\
} while (0)


#define MTL_QTDR5_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR5_TXQPAUSED_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 0) & MTL_QTDR5_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR5_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR5_TRCSTS_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 1) & MTL_QTDR5_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR5_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR5_TWCSTS_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 3) & MTL_QTDR5_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR5_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR5_TXQSTS_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 4) & MTL_QTDR5_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR5_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR5_TXSTSFSTS_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 5) & MTL_QTDR5_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR5_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR5_PTXQ_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 16) & MTL_QTDR5_PTXQ_MASK);\
} while (0)


#define MTL_QTDR5_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR5_STXSTSF_RD(data) do {\
	MTL_QTDR5_RD(data);\
	data = ((data >> 20) & MTL_QTDR5_STXSTSF_MASK);\
} while (0)

#define MTL_QTDR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe08))

#define MTL_QTDR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR4_OFFSET);\
} while (0)


#define MTL_QTDR4_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR4_TXQPAUSED_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 0) & MTL_QTDR4_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR4_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR4_TRCSTS_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 1) & MTL_QTDR4_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR4_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR4_TWCSTS_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 3) & MTL_QTDR4_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR4_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR4_TXQSTS_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 4) & MTL_QTDR4_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR4_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR4_TXSTSFSTS_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 5) & MTL_QTDR4_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR4_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR4_PTXQ_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 16) & MTL_QTDR4_PTXQ_MASK);\
} while (0)


#define MTL_QTDR4_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR4_STXSTSF_RD(data) do {\
	MTL_QTDR4_RD(data);\
	data = ((data >> 20) & MTL_QTDR4_STXSTSF_MASK);\
} while (0)

#define MTL_QTDR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdc8))

#define MTL_QTDR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR3_OFFSET);\
} while (0)


#define MTL_QTDR3_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR3_TXQPAUSED_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 0) & MTL_QTDR3_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR3_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR3_TRCSTS_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 1) & MTL_QTDR3_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR3_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR3_TWCSTS_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 3) & MTL_QTDR3_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR3_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR3_TXQSTS_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 4) & MTL_QTDR3_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR3_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR3_TXSTSFSTS_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 5) & MTL_QTDR3_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR3_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR3_PTXQ_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 16) & MTL_QTDR3_PTXQ_MASK);\
} while (0)


#define MTL_QTDR3_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR3_STXSTSF_RD(data) do {\
	MTL_QTDR3_RD(data);\
	data = ((data >> 20) & MTL_QTDR3_STXSTSF_MASK);\
} while (0)

#define MTL_QTDR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd88))

#define MTL_QTDR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR2_OFFSET);\
} while (0)


#define MTL_QTDR2_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR2_TXQPAUSED_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 0) & MTL_QTDR2_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR2_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR2_TRCSTS_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 1) & MTL_QTDR2_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR2_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR2_TWCSTS_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 3) & MTL_QTDR2_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR2_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR2_TXQSTS_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 4) & MTL_QTDR2_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR2_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR2_TXSTSFSTS_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 5) & MTL_QTDR2_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR2_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR2_PTXQ_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 16) & MTL_QTDR2_PTXQ_MASK);\
} while (0)


#define MTL_QTDR2_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR2_STXSTSF_RD(data) do {\
	MTL_QTDR2_RD(data);\
	data = ((data >> 20) & MTL_QTDR2_STXSTSF_MASK);\
} while (0)

#define MTL_QTDR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd48))

#define MTL_QTDR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QTDR1_OFFSET);\
} while (0)


#define MTL_QTDR1_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR1_TXQPAUSED_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 0) & MTL_QTDR1_TXQPAUSED_MASK);\
} while (0)


#define MTL_QTDR1_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR1_TRCSTS_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 1) & MTL_QTDR1_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR1_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR1_TWCSTS_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 3) & MTL_QTDR1_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR1_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR1_TXQSTS_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 4) & MTL_QTDR1_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR1_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR1_TXSTSFSTS_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 5) & MTL_QTDR1_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR1_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR1_PTXQ_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 16) & MTL_QTDR1_PTXQ_MASK);\
} while (0)


#define MTL_QTDR1_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR1_STXSTSF_RD(data) do {\
	MTL_QTDR1_RD(data);\
	data = ((data >> 20) & MTL_QTDR1_STXSTSF_MASK);\
} while (0)

#define MTL_QUCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xec4))

#define MTL_QUCR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR7_OFFSET);\
} while (0)

#define MTL_QUCR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR7_OFFSET);\
} while (0)


#define  MTL_QUCR7_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR7_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR7_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR7_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR7_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR7_RD(v);\
	v = (v & (MTL_QUCR7_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR7_MASK_12))<<12);\
	v = ((v & MTL_QUCR7_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR7_UFPKTCNT_MASK)<<0));\
	MTL_QUCR7_WR(v);\
} while (0)

#define MTL_QUCR7_UFPKTCNT_RD(data) do {\
	MTL_QUCR7_RD(data);\
	data = ((data >> 0) & MTL_QUCR7_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR7_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR7_UFCNTOVF_RD(data) do {\
	MTL_QUCR7_RD(data);\
	data = ((data >> 11) & MTL_QUCR7_UFCNTOVF_MASK);\
} while (0)

#define MTL_QUCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe84))

#define MTL_QUCR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR6_OFFSET);\
} while (0)

#define MTL_QUCR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR6_OFFSET);\
} while (0)


#define  MTL_QUCR6_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR6_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR6_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR6_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR6_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR6_RD(v);\
	v = (v & (MTL_QUCR6_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR6_MASK_12))<<12);\
	v = ((v & MTL_QUCR6_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR6_UFPKTCNT_MASK)<<0));\
	MTL_QUCR6_WR(v);\
} while (0)

#define MTL_QUCR6_UFPKTCNT_RD(data) do {\
	MTL_QUCR6_RD(data);\
	data = ((data >> 0) & MTL_QUCR6_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR6_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR6_UFCNTOVF_RD(data) do {\
	MTL_QUCR6_RD(data);\
	data = ((data >> 11) & MTL_QUCR6_UFCNTOVF_MASK);\
} while (0)

#define MTL_QUCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe44))

#define MTL_QUCR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR5_OFFSET);\
} while (0)

#define MTL_QUCR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR5_OFFSET);\
} while (0)


#define  MTL_QUCR5_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR5_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR5_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR5_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR5_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR5_RD(v);\
	v = (v & (MTL_QUCR5_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR5_MASK_12))<<12);\
	v = ((v & MTL_QUCR5_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR5_UFPKTCNT_MASK)<<0));\
	MTL_QUCR5_WR(v);\
} while (0)

#define MTL_QUCR5_UFPKTCNT_RD(data) do {\
	MTL_QUCR5_RD(data);\
	data = ((data >> 0) & MTL_QUCR5_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR5_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR5_UFCNTOVF_RD(data) do {\
	MTL_QUCR5_RD(data);\
	data = ((data >> 11) & MTL_QUCR5_UFCNTOVF_MASK);\
} while (0)

#define MTL_QUCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe04))

#define MTL_QUCR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR4_OFFSET);\
} while (0)

#define MTL_QUCR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR4_OFFSET);\
} while (0)


#define  MTL_QUCR4_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR4_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR4_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR4_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR4_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR4_RD(v);\
	v = (v & (MTL_QUCR4_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR4_MASK_12))<<12);\
	v = ((v & MTL_QUCR4_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR4_UFPKTCNT_MASK)<<0));\
	MTL_QUCR4_WR(v);\
} while (0)

#define MTL_QUCR4_UFPKTCNT_RD(data) do {\
	MTL_QUCR4_RD(data);\
	data = ((data >> 0) & MTL_QUCR4_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR4_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR4_UFCNTOVF_RD(data) do {\
	MTL_QUCR4_RD(data);\
	data = ((data >> 11) & MTL_QUCR4_UFCNTOVF_MASK);\
} while (0)

#define MTL_QUCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdc4))

#define MTL_QUCR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR3_OFFSET);\
} while (0)

#define MTL_QUCR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR3_OFFSET);\
} while (0)


#define  MTL_QUCR3_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR3_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR3_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR3_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR3_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR3_RD(v);\
	v = (v & (MTL_QUCR3_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR3_MASK_12))<<12);\
	v = ((v & MTL_QUCR3_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR3_UFPKTCNT_MASK)<<0));\
	MTL_QUCR3_WR(v);\
} while (0)

#define MTL_QUCR3_UFPKTCNT_RD(data) do {\
	MTL_QUCR3_RD(data);\
	data = ((data >> 0) & MTL_QUCR3_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR3_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR3_UFCNTOVF_RD(data) do {\
	MTL_QUCR3_RD(data);\
	data = ((data >> 11) & MTL_QUCR3_UFCNTOVF_MASK);\
} while (0)

#define MTL_QUCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd84))

#define MTL_QUCR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR2_OFFSET);\
} while (0)

#define MTL_QUCR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR2_OFFSET);\
} while (0)


#define  MTL_QUCR2_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR2_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR2_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR2_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR2_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR2_RD(v);\
	v = (v & (MTL_QUCR2_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR2_MASK_12))<<12);\
	v = ((v & MTL_QUCR2_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR2_UFPKTCNT_MASK)<<0));\
	MTL_QUCR2_WR(v);\
} while (0)

#define MTL_QUCR2_UFPKTCNT_RD(data) do {\
	MTL_QUCR2_RD(data);\
	data = ((data >> 0) & MTL_QUCR2_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR2_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR2_UFCNTOVF_RD(data) do {\
	MTL_QUCR2_RD(data);\
	data = ((data >> 11) & MTL_QUCR2_UFCNTOVF_MASK);\
} while (0)

#define MTL_QUCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd44))

#define MTL_QUCR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QUCR1_OFFSET);\
} while (0)

#define MTL_QUCR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QUCR1_OFFSET);\
} while (0)


#define  MTL_QUCR1_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR1_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR1_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR1_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR1_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_QUCR1_RD(v);\
	v = (v & (MTL_QUCR1_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR1_MASK_12))<<12);\
	v = ((v & MTL_QUCR1_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR1_UFPKTCNT_MASK)<<0));\
	MTL_QUCR1_WR(v);\
} while (0)

#define MTL_QUCR1_UFPKTCNT_RD(data) do {\
	MTL_QUCR1_RD(data);\
	data = ((data >> 0) & MTL_QUCR1_UFPKTCNT_MASK);\
} while (0)


#define MTL_QUCR1_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR1_UFCNTOVF_RD(data) do {\
	MTL_QUCR1_RD(data);\
	data = ((data >> 11) & MTL_QUCR1_UFCNTOVF_MASK);\
} while (0)

#define MTL_QTOMR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xec0))

#define MTL_QTOMR7_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR7_OFFSET);\
} while (0)

#define MTL_QTOMR7_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR7_OFFSET);\
} while (0)


#define  MTL_QTOMR7_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR7_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR7_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR7_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR7_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR7_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR7_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR7_RD(v);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR7_MASK_7))<<7);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR7_MASK_26))<<26);\
	v = ((v & MTL_QTOMR7_FTQ_WR_MASK)\
	|((data & MTL_QTOMR7_FTQ_MASK)<<0));\
	MTL_QTOMR7_WR(v);\
} while (0)

#define MTL_QTOMR7_FTQ_RD(data) do {\
	MTL_QTOMR7_RD(data);\
	data = ((data >> 0) & MTL_QTOMR7_FTQ_MASK);\
} while (0)


#define MTL_QTOMR7_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR7_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR7_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR7_RD(v);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR7_MASK_7))<<7);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR7_MASK_26))<<26);\
	v = ((v & MTL_QTOMR7_TSF_WR_MASK)\
	|((data & MTL_QTOMR7_TSF_MASK)<<1));\
	MTL_QTOMR7_WR(v);\
} while (0)

#define MTL_QTOMR7_TSF_RD(data) do {\
	MTL_QTOMR7_RD(data);\
	data = ((data >> 1) & MTL_QTOMR7_TSF_MASK);\
} while (0)


#define MTL_QTOMR7_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR7_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR7_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR7_RD(v);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR7_MASK_7))<<7);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR7_MASK_26))<<26);\
	v = ((v & MTL_QTOMR7_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR7_TXQEN_MASK)<<2));\
	MTL_QTOMR7_WR(v);\
} while (0)

#define MTL_QTOMR7_TXQEN_RD(data) do {\
	MTL_QTOMR7_RD(data);\
	data = ((data >> 2) & MTL_QTOMR7_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR7_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR7_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR7_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR7_RD(v);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR7_MASK_7))<<7);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR7_MASK_26))<<26);\
	v = ((v & MTL_QTOMR7_TTC_WR_MASK)\
	|((data & MTL_QTOMR7_TTC_MASK)<<4));\
	MTL_QTOMR7_WR(v);\
} while (0)

#define MTL_QTOMR7_TTC_RD(data) do {\
	MTL_QTOMR7_RD(data);\
	data = ((data >> 4) & MTL_QTOMR7_TTC_MASK);\
} while (0)


#define MTL_QTOMR7_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR7_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR7_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR7_RD(v);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR7_MASK_7))<<7);\
	v = (v & (MTL_QTOMR7_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR7_MASK_26))<<26);\
	v = ((v & MTL_QTOMR7_TQS_WR_MASK)\
	|((data & MTL_QTOMR7_TQS_MASK)<<16));\
	MTL_QTOMR7_WR(v);\
} while (0)

#define MTL_QTOMR7_TQS_RD(data) do {\
	MTL_QTOMR7_RD(data);\
	data = ((data >> 16) & MTL_QTOMR7_TQS_MASK);\
} while (0)

#define MTL_QTOMR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe80))

#define MTL_QTOMR6_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR6_OFFSET);\
} while (0)

#define MTL_QTOMR6_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR6_OFFSET);\
} while (0)


#define  MTL_QTOMR6_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR6_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR6_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR6_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR6_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR6_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR6_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR6_RD(v);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR6_MASK_7))<<7);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR6_MASK_26))<<26);\
	v = ((v & MTL_QTOMR6_FTQ_WR_MASK)\
	|((data & MTL_QTOMR6_FTQ_MASK)<<0));\
	MTL_QTOMR6_WR(v);\
} while (0)

#define MTL_QTOMR6_FTQ_RD(data) do {\
	MTL_QTOMR6_RD(data);\
	data = ((data >> 0) & MTL_QTOMR6_FTQ_MASK);\
} while (0)


#define MTL_QTOMR6_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR6_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR6_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR6_RD(v);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR6_MASK_7))<<7);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR6_MASK_26))<<26);\
	v = ((v & MTL_QTOMR6_TSF_WR_MASK)\
	|((data & MTL_QTOMR6_TSF_MASK)<<1));\
	MTL_QTOMR6_WR(v);\
} while (0)

#define MTL_QTOMR6_TSF_RD(data) do {\
	MTL_QTOMR6_RD(data);\
	data = ((data >> 1) & MTL_QTOMR6_TSF_MASK);\
} while (0)


#define MTL_QTOMR6_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR6_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR6_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR6_RD(v);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR6_MASK_7))<<7);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR6_MASK_26))<<26);\
	v = ((v & MTL_QTOMR6_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR6_TXQEN_MASK)<<2));\
	MTL_QTOMR6_WR(v);\
} while (0)

#define MTL_QTOMR6_TXQEN_RD(data) do {\
	MTL_QTOMR6_RD(data);\
	data = ((data >> 2) & MTL_QTOMR6_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR6_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR6_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR6_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR6_RD(v);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR6_MASK_7))<<7);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR6_MASK_26))<<26);\
	v = ((v & MTL_QTOMR6_TTC_WR_MASK)\
	|((data & MTL_QTOMR6_TTC_MASK)<<4));\
	MTL_QTOMR6_WR(v);\
} while (0)

#define MTL_QTOMR6_TTC_RD(data) do {\
	MTL_QTOMR6_RD(data);\
	data = ((data >> 4) & MTL_QTOMR6_TTC_MASK);\
} while (0)


#define MTL_QTOMR6_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR6_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR6_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR6_RD(v);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR6_MASK_7))<<7);\
	v = (v & (MTL_QTOMR6_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR6_MASK_26))<<26);\
	v = ((v & MTL_QTOMR6_TQS_WR_MASK)\
	|((data & MTL_QTOMR6_TQS_MASK)<<16));\
	MTL_QTOMR6_WR(v);\
} while (0)

#define MTL_QTOMR6_TQS_RD(data) do {\
	MTL_QTOMR6_RD(data);\
	data = ((data >> 16) & MTL_QTOMR6_TQS_MASK);\
} while (0)

#define MTL_QTOMR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe40))

#define MTL_QTOMR5_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR5_OFFSET);\
} while (0)

#define MTL_QTOMR5_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR5_OFFSET);\
} while (0)


#define  MTL_QTOMR5_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR5_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR5_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR5_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR5_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR5_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR5_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR5_RD(v);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR5_MASK_7))<<7);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR5_MASK_26))<<26);\
	v = ((v & MTL_QTOMR5_FTQ_WR_MASK)\
	|((data & MTL_QTOMR5_FTQ_MASK)<<0));\
	MTL_QTOMR5_WR(v);\
} while (0)

#define MTL_QTOMR5_FTQ_RD(data) do {\
	MTL_QTOMR5_RD(data);\
	data = ((data >> 0) & MTL_QTOMR5_FTQ_MASK);\
} while (0)


#define MTL_QTOMR5_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR5_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR5_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR5_RD(v);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR5_MASK_7))<<7);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR5_MASK_26))<<26);\
	v = ((v & MTL_QTOMR5_TSF_WR_MASK)\
	|((data & MTL_QTOMR5_TSF_MASK)<<1));\
	MTL_QTOMR5_WR(v);\
} while (0)

#define MTL_QTOMR5_TSF_RD(data) do {\
	MTL_QTOMR5_RD(data);\
	data = ((data >> 1) & MTL_QTOMR5_TSF_MASK);\
} while (0)


#define MTL_QTOMR5_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR5_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR5_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR5_RD(v);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR5_MASK_7))<<7);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR5_MASK_26))<<26);\
	v = ((v & MTL_QTOMR5_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR5_TXQEN_MASK)<<2));\
	MTL_QTOMR5_WR(v);\
} while (0)

#define MTL_QTOMR5_TXQEN_RD(data) do {\
	MTL_QTOMR5_RD(data);\
	data = ((data >> 2) & MTL_QTOMR5_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR5_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR5_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR5_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR5_RD(v);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR5_MASK_7))<<7);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR5_MASK_26))<<26);\
	v = ((v & MTL_QTOMR5_TTC_WR_MASK)\
	|((data & MTL_QTOMR5_TTC_MASK)<<4));\
	MTL_QTOMR5_WR(v);\
} while (0)

#define MTL_QTOMR5_TTC_RD(data) do {\
	MTL_QTOMR5_RD(data);\
	data = ((data >> 4) & MTL_QTOMR5_TTC_MASK);\
} while (0)


#define MTL_QTOMR5_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR5_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR5_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR5_RD(v);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR5_MASK_7))<<7);\
	v = (v & (MTL_QTOMR5_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR5_MASK_26))<<26);\
	v = ((v & MTL_QTOMR5_TQS_WR_MASK)\
	|((data & MTL_QTOMR5_TQS_MASK)<<16));\
	MTL_QTOMR5_WR(v);\
} while (0)

#define MTL_QTOMR5_TQS_RD(data) do {\
	MTL_QTOMR5_RD(data);\
	data = ((data >> 16) & MTL_QTOMR5_TQS_MASK);\
} while (0)

#define MTL_QTOMR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xe00))

#define MTL_QTOMR4_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR4_OFFSET);\
} while (0)

#define MTL_QTOMR4_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR4_OFFSET);\
} while (0)


#define  MTL_QTOMR4_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR4_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR4_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR4_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR4_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR4_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR4_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR4_RD(v);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR4_MASK_7))<<7);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR4_MASK_26))<<26);\
	v = ((v & MTL_QTOMR4_FTQ_WR_MASK)\
	|((data & MTL_QTOMR4_FTQ_MASK)<<0));\
	MTL_QTOMR4_WR(v);\
} while (0)

#define MTL_QTOMR4_FTQ_RD(data) do {\
	MTL_QTOMR4_RD(data);\
	data = ((data >> 0) & MTL_QTOMR4_FTQ_MASK);\
} while (0)


#define MTL_QTOMR4_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR4_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR4_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR4_RD(v);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR4_MASK_7))<<7);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR4_MASK_26))<<26);\
	v = ((v & MTL_QTOMR4_TSF_WR_MASK)\
	|((data & MTL_QTOMR4_TSF_MASK)<<1));\
	MTL_QTOMR4_WR(v);\
} while (0)

#define MTL_QTOMR4_TSF_RD(data) do {\
	MTL_QTOMR4_RD(data);\
	data = ((data >> 1) & MTL_QTOMR4_TSF_MASK);\
} while (0)


#define MTL_QTOMR4_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR4_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR4_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR4_RD(v);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR4_MASK_7))<<7);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR4_MASK_26))<<26);\
	v = ((v & MTL_QTOMR4_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR4_TXQEN_MASK)<<2));\
	MTL_QTOMR4_WR(v);\
} while (0)

#define MTL_QTOMR4_TXQEN_RD(data) do {\
	MTL_QTOMR4_RD(data);\
	data = ((data >> 2) & MTL_QTOMR4_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR4_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR4_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR4_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR4_RD(v);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR4_MASK_7))<<7);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR4_MASK_26))<<26);\
	v = ((v & MTL_QTOMR4_TTC_WR_MASK)\
	|((data & MTL_QTOMR4_TTC_MASK)<<4));\
	MTL_QTOMR4_WR(v);\
} while (0)

#define MTL_QTOMR4_TTC_RD(data) do {\
	MTL_QTOMR4_RD(data);\
	data = ((data >> 4) & MTL_QTOMR4_TTC_MASK);\
} while (0)


#define MTL_QTOMR4_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR4_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR4_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR4_RD(v);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR4_MASK_7))<<7);\
	v = (v & (MTL_QTOMR4_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR4_MASK_26))<<26);\
	v = ((v & MTL_QTOMR4_TQS_WR_MASK)\
	|((data & MTL_QTOMR4_TQS_MASK)<<16));\
	MTL_QTOMR4_WR(v);\
} while (0)

#define MTL_QTOMR4_TQS_RD(data) do {\
	MTL_QTOMR4_RD(data);\
	data = ((data >> 16) & MTL_QTOMR4_TQS_MASK);\
} while (0)

#define MTL_QTOMR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xdc0))

#define MTL_QTOMR3_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR3_OFFSET);\
} while (0)

#define MTL_QTOMR3_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR3_OFFSET);\
} while (0)


#define  MTL_QTOMR3_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR3_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR3_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR3_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR3_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR3_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR3_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR3_RD(v);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR3_MASK_7))<<7);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR3_MASK_26))<<26);\
	v = ((v & MTL_QTOMR3_FTQ_WR_MASK)\
	|((data & MTL_QTOMR3_FTQ_MASK)<<0));\
	MTL_QTOMR3_WR(v);\
} while (0)

#define MTL_QTOMR3_FTQ_RD(data) do {\
	MTL_QTOMR3_RD(data);\
	data = ((data >> 0) & MTL_QTOMR3_FTQ_MASK);\
} while (0)


#define MTL_QTOMR3_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR3_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR3_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR3_RD(v);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR3_MASK_7))<<7);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR3_MASK_26))<<26);\
	v = ((v & MTL_QTOMR3_TSF_WR_MASK)\
	|((data & MTL_QTOMR3_TSF_MASK)<<1));\
	MTL_QTOMR3_WR(v);\
} while (0)

#define MTL_QTOMR3_TSF_RD(data) do {\
	MTL_QTOMR3_RD(data);\
	data = ((data >> 1) & MTL_QTOMR3_TSF_MASK);\
} while (0)


#define MTL_QTOMR3_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR3_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR3_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR3_RD(v);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR3_MASK_7))<<7);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR3_MASK_26))<<26);\
	v = ((v & MTL_QTOMR3_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR3_TXQEN_MASK)<<2));\
	MTL_QTOMR3_WR(v);\
} while (0)

#define MTL_QTOMR3_TXQEN_RD(data) do {\
	MTL_QTOMR3_RD(data);\
	data = ((data >> 2) & MTL_QTOMR3_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR3_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR3_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR3_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR3_RD(v);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR3_MASK_7))<<7);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR3_MASK_26))<<26);\
	v = ((v & MTL_QTOMR3_TTC_WR_MASK)\
	|((data & MTL_QTOMR3_TTC_MASK)<<4));\
	MTL_QTOMR3_WR(v);\
} while (0)

#define MTL_QTOMR3_TTC_RD(data) do {\
	MTL_QTOMR3_RD(data);\
	data = ((data >> 4) & MTL_QTOMR3_TTC_MASK);\
} while (0)


#define MTL_QTOMR3_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR3_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR3_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR3_RD(v);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR3_MASK_7))<<7);\
	v = (v & (MTL_QTOMR3_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR3_MASK_26))<<26);\
	v = ((v & MTL_QTOMR3_TQS_WR_MASK)\
	|((data & MTL_QTOMR3_TQS_MASK)<<16));\
	MTL_QTOMR3_WR(v);\
} while (0)

#define MTL_QTOMR3_TQS_RD(data) do {\
	MTL_QTOMR3_RD(data);\
	data = ((data >> 16) & MTL_QTOMR3_TQS_MASK);\
} while (0)

#define MTL_QTOMR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd80))

#define MTL_QTOMR2_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR2_OFFSET);\
} while (0)

#define MTL_QTOMR2_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR2_OFFSET);\
} while (0)


#define  MTL_QTOMR2_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR2_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR2_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR2_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR2_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR2_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR2_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR2_RD(v);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR2_MASK_7))<<7);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR2_MASK_26))<<26);\
	v = ((v & MTL_QTOMR2_FTQ_WR_MASK)\
	|((data & MTL_QTOMR2_FTQ_MASK)<<0));\
	MTL_QTOMR2_WR(v);\
} while (0)

#define MTL_QTOMR2_FTQ_RD(data) do {\
	MTL_QTOMR2_RD(data);\
	data = ((data >> 0) & MTL_QTOMR2_FTQ_MASK);\
} while (0)


#define MTL_QTOMR2_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR2_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR2_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR2_RD(v);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR2_MASK_7))<<7);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR2_MASK_26))<<26);\
	v = ((v & MTL_QTOMR2_TSF_WR_MASK)\
	|((data & MTL_QTOMR2_TSF_MASK)<<1));\
	MTL_QTOMR2_WR(v);\
} while (0)

#define MTL_QTOMR2_TSF_RD(data) do {\
	MTL_QTOMR2_RD(data);\
	data = ((data >> 1) & MTL_QTOMR2_TSF_MASK);\
} while (0)


#define MTL_QTOMR2_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR2_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR2_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR2_RD(v);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR2_MASK_7))<<7);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR2_MASK_26))<<26);\
	v = ((v & MTL_QTOMR2_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR2_TXQEN_MASK)<<2));\
	MTL_QTOMR2_WR(v);\
} while (0)

#define MTL_QTOMR2_TXQEN_RD(data) do {\
	MTL_QTOMR2_RD(data);\
	data = ((data >> 2) & MTL_QTOMR2_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR2_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR2_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR2_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR2_RD(v);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR2_MASK_7))<<7);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR2_MASK_26))<<26);\
	v = ((v & MTL_QTOMR2_TTC_WR_MASK)\
	|((data & MTL_QTOMR2_TTC_MASK)<<4));\
	MTL_QTOMR2_WR(v);\
} while (0)

#define MTL_QTOMR2_TTC_RD(data) do {\
	MTL_QTOMR2_RD(data);\
	data = ((data >> 4) & MTL_QTOMR2_TTC_MASK);\
} while (0)


#define MTL_QTOMR2_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR2_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR2_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR2_RD(v);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR2_MASK_7))<<7);\
	v = (v & (MTL_QTOMR2_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR2_MASK_26))<<26);\
	v = ((v & MTL_QTOMR2_TQS_WR_MASK)\
	|((data & MTL_QTOMR2_TQS_MASK)<<16));\
	MTL_QTOMR2_WR(v);\
} while (0)

#define MTL_QTOMR2_TQS_RD(data) do {\
	MTL_QTOMR2_RD(data);\
	data = ((data >> 16) & MTL_QTOMR2_TQS_MASK);\
} while (0)

#define MTL_QTOMR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd40))

#define MTL_QTOMR1_WR(data) do {\
	iowrite32(data, (void *)MTL_QTOMR1_OFFSET);\
} while (0)

#define MTL_QTOMR1_RD(data) do {\
	(data) = ioread32((void *)MTL_QTOMR1_OFFSET);\
} while (0)


#define  MTL_QTOMR1_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR1_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define  MTL_QTOMR1_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR1_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MTL_QTOMR1_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR1_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR1_FTQ_WR(data) do {\
	ULONG v;\
	MTL_QTOMR1_RD(v);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR1_MASK_7))<<7);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR1_MASK_26))<<26);\
	v = ((v & MTL_QTOMR1_FTQ_WR_MASK)\
	|((data & MTL_QTOMR1_FTQ_MASK)<<0));\
	MTL_QTOMR1_WR(v);\
} while (0)

#define MTL_QTOMR1_FTQ_RD(data) do {\
	MTL_QTOMR1_RD(data);\
	data = ((data >> 0) & MTL_QTOMR1_FTQ_MASK);\
} while (0)


#define MTL_QTOMR1_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR1_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR1_TSF_WR(data) do {\
	ULONG v;\
	MTL_QTOMR1_RD(v);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR1_MASK_7))<<7);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR1_MASK_26))<<26);\
	v = ((v & MTL_QTOMR1_TSF_WR_MASK)\
	|((data & MTL_QTOMR1_TSF_MASK)<<1));\
	MTL_QTOMR1_WR(v);\
} while (0)

#define MTL_QTOMR1_TSF_RD(data) do {\
	MTL_QTOMR1_RD(data);\
	data = ((data >> 1) & MTL_QTOMR1_TSF_MASK);\
} while (0)


#define MTL_QTOMR1_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR1_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR1_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_QTOMR1_RD(v);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR1_MASK_7))<<7);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR1_MASK_26))<<26);\
	v = ((v & MTL_QTOMR1_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR1_TXQEN_MASK)<<2));\
	MTL_QTOMR1_WR(v);\
} while (0)

#define MTL_QTOMR1_TXQEN_RD(data) do {\
	MTL_QTOMR1_RD(data);\
	data = ((data >> 2) & MTL_QTOMR1_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR1_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR1_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR1_TTC_WR(data) do {\
	ULONG v;\
	MTL_QTOMR1_RD(v);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR1_MASK_7))<<7);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR1_MASK_26))<<26);\
	v = ((v & MTL_QTOMR1_TTC_WR_MASK)\
	|((data & MTL_QTOMR1_TTC_MASK)<<4));\
	MTL_QTOMR1_WR(v);\
} while (0)

#define MTL_QTOMR1_TTC_RD(data) do {\
	MTL_QTOMR1_RD(data);\
	data = ((data >> 4) & MTL_QTOMR1_TTC_MASK);\
} while (0)


#define MTL_QTOMR1_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR1_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR1_TQS_WR(data) do {\
	ULONG v;\
	MTL_QTOMR1_RD(v);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR1_MASK_7))<<7);\
	v = (v & (MTL_QTOMR1_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR1_MASK_26))<<26);\
	v = ((v & MTL_QTOMR1_TQS_WR_MASK)\
	|((data & MTL_QTOMR1_TQS_MASK)<<16));\
	MTL_QTOMR1_WR(v);\
} while (0)

#define MTL_QTOMR1_TQS_RD(data) do {\
	MTL_QTOMR1_RD(data);\
	data = ((data >> 16) & MTL_QTOMR1_TQS_MASK);\
} while (0)

#define MAC_PMTCSR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc0))

#define MAC_PMTCSR_WR(data) do {\
	iowrite32(data, (void *)MAC_PMTCSR_OFFSET);\
} while (0)

#define MAC_PMTCSR_RD(data) do {\
	(data) = ioread32((void *)MAC_PMTCSR_OFFSET);\
} while (0)


#define  MAC_PMTCSR_MASK_27 (ULONG)(0xf)


#define MAC_PMTCSR_RES_WR_MASK_27 (ULONG)(0x87ffffff)


#define  MAC_PMTCSR_MASK_10 (ULONG)(0x3fff)


#define MAC_PMTCSR_RES_WR_MASK_10 (ULONG)(0xff0003ff)


#define  MAC_PMTCSR_MASK_7 (ULONG)(0x3)


#define MAC_PMTCSR_RES_WR_MASK_7 (ULONG)(0xfffffe7f)


#define  MAC_PMTCSR_MASK_3 (ULONG)(0x3)


#define MAC_PMTCSR_RES_WR_MASK_3 (ULONG)(0xffffffe7)


#define MAC_PMTCSR_RWKFILTRST_MASK (ULONG)(0x1)


#define MAC_PMTCSR_RWKFILTRST_WR_MASK (ULONG)(0x7fffffff)

#define MAC_PMTCSR_RWKFILTRST_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_RWKFILTRST_WR_MASK)\
	|((data & MAC_PMTCSR_RWKFILTRST_MASK)<<31));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_RWKFILTRST_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 31) & MAC_PMTCSR_RWKFILTRST_MASK);\
} while (0)


#define MAC_PMTCSR_RWKPTR_MASK (ULONG)(0x7)

#define MAC_PMTCSR_RWKPTR_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 24) & MAC_PMTCSR_RWKPTR_MASK);\
} while (0)


#define MAC_PMTCSR_GLBLUCAST_MASK (ULONG)(0x1)


#define MAC_PMTCSR_GLBLUCAST_WR_MASK (ULONG)(0xfffffdff)

#define MAC_PMTCSR_GLBLUCAST_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_GLBLUCAST_WR_MASK)\
	|((data & MAC_PMTCSR_GLBLUCAST_MASK)<<9));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_GLBLUCAST_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 9) & MAC_PMTCSR_GLBLUCAST_MASK);\
} while (0)


#define MAC_PMTCSR_RWKPRCVD_MASK (ULONG)(0x1)


#define MAC_PMTCSR_RWKPRCVD_WR_MASK (ULONG)(0xffffffbf)

#define MAC_PMTCSR_RWKPRCVD_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_RWKPRCVD_WR_MASK)\
	|((data & MAC_PMTCSR_RWKPRCVD_MASK)<<6));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_RWKPRCVD_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 6) & MAC_PMTCSR_RWKPRCVD_MASK);\
} while (0)


#define MAC_PMTCSR_MGKPRCVD_MASK (ULONG)(0x1)


#define MAC_PMTCSR_MGKPRCVD_WR_MASK (ULONG)(0xffffffdf)

#define MAC_PMTCSR_MGKPRCVD_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_MGKPRCVD_WR_MASK)\
	|((data & MAC_PMTCSR_MGKPRCVD_MASK)<<5));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_MGKPRCVD_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 5) & MAC_PMTCSR_MGKPRCVD_MASK);\
} while (0)


#define MAC_PMTCSR_RWKPKTEN_MASK (ULONG)(0x1)


#define MAC_PMTCSR_RWKPKTEN_WR_MASK (ULONG)(0xfffffffb)

#define MAC_PMTCSR_RWKPKTEN_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_RWKPKTEN_WR_MASK)\
	|((data & MAC_PMTCSR_RWKPKTEN_MASK)<<2));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_RWKPKTEN_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 2) & MAC_PMTCSR_RWKPKTEN_MASK);\
} while (0)


#define MAC_PMTCSR_MGKPKTEN_MASK (ULONG)(0x1)


#define MAC_PMTCSR_MGKPKTEN_WR_MASK (ULONG)(0xfffffffd)

#define MAC_PMTCSR_MGKPKTEN_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_MGKPKTEN_WR_MASK)\
	|((data & MAC_PMTCSR_MGKPKTEN_MASK)<<1));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_MGKPKTEN_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 1) & MAC_PMTCSR_MGKPKTEN_MASK);\
} while (0)


#define MAC_PMTCSR_PWRDWN_MASK (ULONG)(0x1)


#define MAC_PMTCSR_PWRDWN_WR_MASK (ULONG)(0xfffffffe)

#define MAC_PMTCSR_PWRDWN_WR(data) do {\
	ULONG v;\
	MAC_PMTCSR_RD(v);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_27))\
	|(((0) & (MAC_PMTCSR_MASK_27))<<27);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_10))\
	|(((0) & (MAC_PMTCSR_MASK_10))<<10);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_7))\
	|(((0) & (MAC_PMTCSR_MASK_7))<<7);\
	v = (v & (MAC_PMTCSR_RES_WR_MASK_3))\
	|(((0) & (MAC_PMTCSR_MASK_3))<<3);\
	v = ((v & MAC_PMTCSR_PWRDWN_WR_MASK)\
	|((data & MAC_PMTCSR_PWRDWN_MASK)<<0));\
	MAC_PMTCSR_WR(v);\
} while (0)

#define MAC_PMTCSR_PWRDWN_RD(data) do {\
	MAC_PMTCSR_RD(data);\
	data = ((data >> 0) & MAC_PMTCSR_PWRDWN_MASK);\
} while (0)

#define MMC_RXICMP_ERR_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x884))

#define MMC_RXICMP_ERR_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXICMP_ERR_OCTETS_OFFSET);\
} while (0)

#define MMC_RXICMP_ERR_OCTETS_RXICMP_ERR_OCTETS_RD(data) do {\
	MMC_RXICMP_ERR_OCTETS_RD(data);\
} while (0)

#define MMC_RXICMP_GD_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x880))

#define MMC_RXICMP_GD_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXICMP_GD_OCTETS_OFFSET);\
} while (0)

#define MMC_RXICMP_GD_OCTETS_RXICMP_GD_OCTETS_RD(data) do {\
	MMC_RXICMP_GD_OCTETS_RD(data);\
} while (0)

#define MMC_RXTCP_ERR_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x87c))

#define MMC_RXTCP_ERR_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXTCP_ERR_OCTETS_OFFSET);\
} while (0)

#define MMC_RXTCP_ERR_OCTETS_RXTCP_ERR_OCTETS_RD(data) do {\
	MMC_RXTCP_ERR_OCTETS_RD(data);\
} while (0)

#define MMC_RXTCP_GD_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x878))

#define MMC_RXTCP_GD_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXTCP_GD_OCTETS_OFFSET);\
} while (0)

#define MMC_RXTCP_GD_OCTETS_RXTCP_GD_OCTETS_RD(data) do {\
	MMC_RXTCP_GD_OCTETS_RD(data);\
} while (0)

#define MMC_RXUDP_ERR_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x874))

#define MMC_RXUDP_ERR_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXUDP_ERR_OCTETS_OFFSET);\
} while (0)

#define MMC_RXUDP_ERR_OCTETS_RXUDP_ERR_OCTETS_RD(data) do {\
	MMC_RXUDP_ERR_OCTETS_RD(data);\
} while (0)

#define MMC_RXUDP_GD_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x870))

#define MMC_RXUDP_GD_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXUDP_GD_OCTETS_OFFSET);\
} while (0)

#define MMC_RXUDP_GD_OCTETS_RXUDP_GD_OCTETS_RD(data) do {\
	MMC_RXUDP_GD_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV6_NOPAY_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x86c))

#define MMC_RXIPV6_NOPAY_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV6_NOPAY_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV6_NOPAY_OCTETS_RXIPV6_NOPAY_OCTETS_RD(data) do {\
	MMC_RXIPV6_NOPAY_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV6_HDRERR_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x868))

#define MMC_RXIPV6_HDRERR_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV6_HDRERR_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV6_HDRERR_OCTETS_RXIPV6_HDRERR_OCTETS_RD(data) do {\
	MMC_RXIPV6_HDRERR_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV6_GD_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x864))

#define MMC_RXIPV6_GD_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV6_GD_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV6_GD_OCTETS_RXIPV6_GD_OCTETS_RD(data) do {\
	MMC_RXIPV6_GD_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV4_UDSBL_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x860))

#define MMC_RXIPV4_UDSBL_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_UDSBL_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV4_UDSBL_OCTETS_RXIPV4_UDSBL_OCTETS_RD(data) do {\
	MMC_RXIPV4_UDSBL_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV4_FRAG_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x85c))

#define MMC_RXIPV4_FRAG_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_FRAG_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV4_FRAG_OCTETS_RXIPV4_FRAG_OCTETS_RD(data) do {\
	MMC_RXIPV4_FRAG_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV4_NOPAY_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x858))

#define MMC_RXIPV4_NOPAY_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_NOPAY_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV4_NOPAY_OCTETS_RXIPV4_NOPAY_OCTETS_RD(data) do {\
	MMC_RXIPV4_NOPAY_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV4_HDRERR_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x854))

#define MMC_RXIPV4_HDRERR_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_HDRERR_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV4_HDRERR_OCTETS_RXIPV4_HDRERR_OCTETS_RD(data) do {\
	MMC_RXIPV4_HDRERR_OCTETS_RD(data);\
} while (0)

#define MMC_RXIPV4_GD_OCTETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x850))

#define MMC_RXIPV4_GD_OCTETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_GD_OCTETS_OFFSET);\
} while (0)

#define MMC_RXIPV4_GD_OCTETS_RXIPV4_GD_OCTETS_RD(data) do {\
	MMC_RXIPV4_GD_OCTETS_RD(data);\
} while (0)

#define MMC_RXICMP_ERR_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x844))

#define MMC_RXICMP_ERR_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXICMP_ERR_PKTS_OFFSET);\
} while (0)

#define MMC_RXICMP_ERR_PKTS_RXICMP_ERR_PKTS_RD(data) do {\
	MMC_RXICMP_ERR_PKTS_RD(data);\
} while (0)

#define MMC_RXICMP_GD_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x840))

#define MMC_RXICMP_GD_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXICMP_GD_PKTS_OFFSET);\
} while (0)

#define MMC_RXICMP_GD_PKTS_RXICMP_GD_PKTS_RD(data) do {\
	MMC_RXICMP_GD_PKTS_RD(data);\
} while (0)

#define MMC_RXTCP_ERR_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x83c))

#define MMC_RXTCP_ERR_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXTCP_ERR_PKTS_OFFSET);\
} while (0)

#define MMC_RXTCP_ERR_PKTS_RXTCP_ERR_PKTS_RD(data) do {\
	MMC_RXTCP_ERR_PKTS_RD(data);\
} while (0)

#define MMC_RXTCP_GD_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x838))

#define MMC_RXTCP_GD_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXTCP_GD_PKTS_OFFSET);\
} while (0)

#define MMC_RXTCP_GD_PKTS_RXTCP_GD_PKTS_RD(data) do {\
	MMC_RXTCP_GD_PKTS_RD(data);\
} while (0)

#define MMC_RXUDP_ERR_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x834))

#define MMC_RXUDP_ERR_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXUDP_ERR_PKTS_OFFSET);\
} while (0)

#define MMC_RXUDP_ERR_PKTS_RXUDP_ERR_PKTS_RD(data) do {\
	MMC_RXUDP_ERR_PKTS_RD(data);\
} while (0)

#define MMC_RXUDP_GD_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x830))

#define MMC_RXUDP_GD_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXUDP_GD_PKTS_OFFSET);\
} while (0)

#define MMC_RXUDP_GD_PKTS_RXUDP_GD_PKTS_RD(data) do {\
	MMC_RXUDP_GD_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV6_NOPAY_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x82c))

#define MMC_RXIPV6_NOPAY_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV6_NOPAY_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV6_NOPAY_PKTS_RXIPV6_NOPAY_PKTS_RD(data) do {\
	MMC_RXIPV6_NOPAY_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV6_HDRERR_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x828))

#define MMC_RXIPV6_HDRERR_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV6_HDRERR_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV6_HDRERR_PKTS_RXIPV6_HDRERR_PKTS_RD(data) do {\
	MMC_RXIPV6_HDRERR_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV6_GD_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x824))

#define MMC_RXIPV6_GD_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV6_GD_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV6_GD_PKTS_RXIPV6_GD_PKTS_RD(data) do {\
	MMC_RXIPV6_GD_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV4_UBSBL_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x820))

#define MMC_RXIPV4_UBSBL_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_UBSBL_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV4_UBSBL_PKTS_RXIPV4_UBSBL_PKTS_RD(data) do {\
	MMC_RXIPV4_UBSBL_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV4_FRAG_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x81c))

#define MMC_RXIPV4_FRAG_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_FRAG_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV4_FRAG_PKTS_RXIPV4_FRAG_PKTS_RD(data) do {\
	MMC_RXIPV4_FRAG_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV4_NOPAY_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x818))

#define MMC_RXIPV4_NOPAY_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_NOPAY_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV4_NOPAY_PKTS_RXIPV4_NOPAY_PKTS_RD(data) do {\
	MMC_RXIPV4_NOPAY_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV4_HDRERR_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x814))

#define MMC_RXIPV4_HDRERR_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_HDRERR_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV4_HDRERR_PKTS_RXIPV4_HDRERR_PKTS_RD(data) do {\
	MMC_RXIPV4_HDRERR_PKTS_RD(data);\
} while (0)

#define MMC_RXIPV4_GD_PKTS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x810))

#define MMC_RXIPV4_GD_PKTS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXIPV4_GD_PKTS_OFFSET);\
} while (0)

#define MMC_RXIPV4_GD_PKTS_RXIPV4_GD_PKTS_RD(data) do {\
	MMC_RXIPV4_GD_PKTS_RD(data);\
} while (0)

#define MMC_RXCTRLPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7e4))

#define MMC_RXCTRLPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXCTRLPACKETS_G_OFFSET);\
} while (0)

#define MMC_RXCTRLPACKETS_G_RXCTRLPACKETS_G_RD(data) do {\
	MMC_RXCTRLPACKETS_G_RD(data);\
} while (0)

#define MMC_RXRCVERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7e0))

#define MMC_RXRCVERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXRCVERROR_OFFSET);\
} while (0)

#define MMC_RXRCVERROR_RXRCVERROR_RD(data) do {\
	MMC_RXRCVERROR_RD(data);\
} while (0)

#define MMC_RXWATCHDOGERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7dc))

#define MMC_RXWATCHDOGERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXWATCHDOGERROR_OFFSET);\
} while (0)

#define MMC_RXWATCHDOGERROR_RXWATCHDOGERROR_RD(data) do {\
	MMC_RXWATCHDOGERROR_RD(data);\
} while (0)

#define MMC_RXVLANPACKETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7d8))

#define MMC_RXVLANPACKETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RXVLANPACKETS_GB_OFFSET);\
} while (0)

#define MMC_RXVLANPACKETS_GB_RXVLANPACKETS_GB_RD(data) do {\
	MMC_RXVLANPACKETS_GB_RD(data);\
} while (0)

#define MMC_RXFIFOOVERFLOW_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7d4))

#define MMC_RXFIFOOVERFLOW_RD(data) do {\
	(data) = ioread32((void *)MMC_RXFIFOOVERFLOW_OFFSET);\
} while (0)

#define MMC_RXFIFOOVERFLOW_RXFIFOOVERFLOW_RD(data) do {\
	MMC_RXFIFOOVERFLOW_RD(data);\
} while (0)

#define MMC_RXPAUSEPACKETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7d0))

#define MMC_RXPAUSEPACKETS_RD(data) do {\
	(data) = ioread32((void *)MMC_RXPAUSEPACKETS_OFFSET);\
} while (0)

#define MMC_RXPAUSEPACKETS_RXPAUSEPACKETS_RD(data) do {\
	MMC_RXPAUSEPACKETS_RD(data);\
} while (0)

#define MMC_RXOUTOFRANGETYPE_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7cc))

#define MMC_RXOUTOFRANGETYPE_RD(data) do {\
	(data) = ioread32((void *)MMC_RXOUTOFRANGETYPE_OFFSET);\
} while (0)

#define MMC_RXOUTOFRANGETYPE_RXOUTOFRANGETYPE_RD(data) do {\
	MMC_RXOUTOFRANGETYPE_RD(data);\
} while (0)

#define MMC_RXLENGTHERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7c8))

#define MMC_RXLENGTHERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXLENGTHERROR_OFFSET);\
} while (0)

#define MMC_RXLENGTHERROR_RXLENGTHERROR_RD(data) do {\
	MMC_RXLENGTHERROR_RD(data);\
} while (0)

#define MMC_RXUNICASTPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7c4))

#define MMC_RXUNICASTPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXUNICASTPACKETS_G_OFFSET);\
} while (0)

#define MMC_RXUNICASTPACKETS_G_RXUNICASTPACKETS_G_RD(data) do {\
	MMC_RXUNICASTPACKETS_G_RD(data);\
} while (0)

#define MMC_RX1024TOMAXOCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7c0))

#define MMC_RX1024TOMAXOCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RX1024TOMAXOCTETS_GB_OFFSET);\
} while (0)

#define MMC_RX1024TOMAXOCTETS_GB_RX1024TOMAXOCTETS_GB_RD(data) do {\
	MMC_RX1024TOMAXOCTETS_GB_RD(data);\
} while (0)

#define MMC_RX512TO1023OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7bc))

#define MMC_RX512TO1023OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RX512TO1023OCTETS_GB_OFFSET);\
} while (0)

#define MMC_RX512TO1023OCTETS_GB_RX512TO1023OCTETS_GB_RD(data) do {\
	MMC_RX512TO1023OCTETS_GB_RD(data);\
} while (0)

#define MMC_RX256TO511OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7b8))

#define MMC_RX256TO511OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RX256TO511OCTETS_GB_OFFSET);\
} while (0)

#define MMC_RX256TO511OCTETS_GB_RX256TO511OCTETS_GB_RD(data) do {\
	MMC_RX256TO511OCTETS_GB_RD(data);\
} while (0)

#define MMC_RX128TO255OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7b4))

#define MMC_RX128TO255OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RX128TO255OCTETS_GB_OFFSET);\
} while (0)

#define MMC_RX128TO255OCTETS_GB_RX128TO255OCTETS_GB_RD(data) do {\
	MMC_RX128TO255OCTETS_GB_RD(data);\
} while (0)

#define MMC_RX65TO127OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7b0))

#define MMC_RX65TO127OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RX65TO127OCTETS_GB_OFFSET);\
} while (0)

#define MMC_RX65TO127OCTETS_GB_RX65TO127OCTETS_GB_RD(data) do {\
	MMC_RX65TO127OCTETS_GB_RD(data);\
} while (0)

#define MMC_RX64OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7ac))

#define MMC_RX64OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RX64OCTETS_GB_OFFSET);\
} while (0)

#define MMC_RX64OCTETS_GB_RX64OCTETS_GB_RD(data) do {\
	MMC_RX64OCTETS_GB_RD(data);\
} while (0)

#define MMC_RXOVERSIZE_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7a8))

#define MMC_RXOVERSIZE_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXOVERSIZE_G_OFFSET);\
} while (0)

#define MMC_RXOVERSIZE_G_RXOVERSIZE_G_RD(data) do {\
	MMC_RXOVERSIZE_G_RD(data);\
} while (0)

#define MMC_RXUNDERSIZE_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7a4))

#define MMC_RXUNDERSIZE_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXUNDERSIZE_G_OFFSET);\
} while (0)

#define MMC_RXUNDERSIZE_G_RXUNDERSIZE_G_RD(data) do {\
	MMC_RXUNDERSIZE_G_RD(data);\
} while (0)

#define MMC_RXJABBERERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7a0))

#define MMC_RXJABBERERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXJABBERERROR_OFFSET);\
} while (0)

#define MMC_RXJABBERERROR_RXJABBERERROR_RD(data) do {\
	MMC_RXJABBERERROR_RD(data);\
} while (0)

#define MMC_RXRUNTERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x79c))

#define MMC_RXRUNTERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXRUNTERROR_OFFSET);\
} while (0)

#define MMC_RXRUNTERROR_RXRUNTERROR_RD(data) do {\
	MMC_RXRUNTERROR_RD(data);\
} while (0)

#define MMC_RXALIGNMENTERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x798))

#define MMC_RXALIGNMENTERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXALIGNMENTERROR_OFFSET);\
} while (0)

#define MMC_RXALIGNMENTERROR_RXALIGNMENTERROR_RD(data) do {\
	MMC_RXALIGNMENTERROR_RD(data);\
} while (0)

#define MMC_RXCRCERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x794))

#define MMC_RXCRCERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_RXCRCERROR_OFFSET);\
} while (0)

#define MMC_RXCRCERROR_RXCRCERROR_RD(data) do {\
	MMC_RXCRCERROR_RD(data);\
} while (0)

#define MMC_RXMULTICASTPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x790))

#define MMC_RXMULTICASTPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXMULTICASTPACKETS_G_OFFSET);\
} while (0)

#define MMC_RXMULTICASTPACKETS_G_RXMULTICASTPACKETS_G_RD(data) do {\
	MMC_RXMULTICASTPACKETS_G_RD(data);\
} while (0)

#define MMC_RXBROADCASTPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x78c))

#define MMC_RXBROADCASTPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXBROADCASTPACKETS_G_OFFSET);\
} while (0)

#define MMC_RXBROADCASTPACKETS_G_RXBROADCASTPACKETS_G_RD(data) do {\
	MMC_RXBROADCASTPACKETS_G_RD(data);\
} while (0)

#define MMC_RXOCTETCOUNT_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x788))

#define MMC_RXOCTETCOUNT_G_RD(data) do {\
	(data) = ioread32((void *)MMC_RXOCTETCOUNT_G_OFFSET);\
} while (0)

#define MMC_RXOCTETCOUNT_G_RXOCTETCOUNT_G_RD(data) do {\
	MMC_RXOCTETCOUNT_G_RD(data);\
} while (0)

#define MMC_RXOCTETCOUNT_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x784))

#define MMC_RXOCTETCOUNT_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RXOCTETCOUNT_GB_OFFSET);\
} while (0)

#define MMC_RXOCTETCOUNT_GB_RXOCTETCOUNT_GB_RD(data) do {\
	MMC_RXOCTETCOUNT_GB_RD(data);\
} while (0)

#define MMC_RXPACKETCOUNT_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x780))

#define MMC_RXPACKETCOUNT_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_RXPACKETCOUNT_GB_OFFSET);\
} while (0)

#define MMC_RXPACKETCOUNT_GB_RXPACKETCOUNT_GB_RD(data) do {\
	MMC_RXPACKETCOUNT_GB_RD(data);\
} while (0)

#define MMC_TXOVERSIZE_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x778))

#define MMC_TXOVERSIZE_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXOVERSIZE_G_OFFSET);\
} while (0)

#define MMC_TXOVERSIZE_G_TXOVERSIZE_G_RD(data) do {\
	MMC_TXOVERSIZE_G_RD(data);\
} while (0)

#define MMC_TXVLANPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x774))

#define MMC_TXVLANPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXVLANPACKETS_G_OFFSET);\
} while (0)

#define MMC_TXVLANPACKETS_G_TXVLANPACKETS_G_RD(data) do {\
	MMC_TXVLANPACKETS_G_RD(data);\
} while (0)

#define MMC_TXPAUSEPACKETS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x770))

#define MMC_TXPAUSEPACKETS_RD(data) do {\
	(data) = ioread32((void *)MMC_TXPAUSEPACKETS_OFFSET);\
} while (0)

#define MMC_TXPAUSEPACKETS_TXPAUSEPACKETS_RD(data) do {\
	MMC_TXPAUSEPACKETS_RD(data);\
} while (0)

#define MMC_TXEXCESSDEF_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x76c))

#define MMC_TXEXCESSDEF_RD(data) do {\
	(data) = ioread32((void *)MMC_TXEXCESSDEF_OFFSET);\
} while (0)

#define MMC_TXEXCESSDEF_TXEXCESSDEF_RD(data) do {\
	MMC_TXEXCESSDEF_RD(data);\
} while (0)

#define MMC_TXPACKETSCOUNT_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x768))

#define MMC_TXPACKETSCOUNT_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXPACKETSCOUNT_G_OFFSET);\
} while (0)

#define MMC_TXPACKETSCOUNT_G_TXPACKETSCOUNT_G_RD(data) do {\
	MMC_TXPACKETSCOUNT_G_RD(data);\
} while (0)

#define MMC_TXOCTETCOUNT_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x764))

#define MMC_TXOCTETCOUNT_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXOCTETCOUNT_G_OFFSET);\
} while (0)

#define MMC_TXOCTETCOUNT_G_TXOCTETCOUNT_G_RD(data) do {\
	MMC_TXOCTETCOUNT_G_RD(data);\
} while (0)

#define MMC_TXCARRIERERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x760))

#define MMC_TXCARRIERERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_TXCARRIERERROR_OFFSET);\
} while (0)

#define MMC_TXCARRIERERROR_TXCARRIERERROR_RD(data) do {\
	MMC_TXCARRIERERROR_RD(data);\
} while (0)

#define MMC_TXEXESSCOL_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x75c))

#define MMC_TXEXESSCOL_RD(data) do {\
	(data) = ioread32((void *)MMC_TXEXESSCOL_OFFSET);\
} while (0)

#define MMC_TXEXESSCOL_TXEXESSCOL_RD(data) do {\
	MMC_TXEXESSCOL_RD(data);\
} while (0)

#define MMC_TXLATECOL_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x758))

#define MMC_TXLATECOL_RD(data) do {\
	(data) = ioread32((void *)MMC_TXLATECOL_OFFSET);\
} while (0)

#define MMC_TXLATECOL_TXLATECOL_RD(data) do {\
	MMC_TXLATECOL_RD(data);\
} while (0)

#define MMC_TXDEFERRED_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x754))

#define MMC_TXDEFERRED_RD(data) do {\
	(data) = ioread32((void *)MMC_TXDEFERRED_OFFSET);\
} while (0)

#define MMC_TXDEFERRED_TXDEFERRED_RD(data) do {\
	MMC_TXDEFERRED_RD(data);\
} while (0)

#define MMC_TXMULTICOL_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x750))

#define MMC_TXMULTICOL_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXMULTICOL_G_OFFSET);\
} while (0)

#define MMC_TXMULTICOL_G_TXMULTICOL_G_RD(data) do {\
	MMC_TXMULTICOL_G_RD(data);\
} while (0)

#define MMC_TXSINGLECOL_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x74c))

#define MMC_TXSINGLECOL_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXSINGLECOL_G_OFFSET);\
} while (0)

#define MMC_TXSINGLECOL_G_TXSINGLECOL_G_RD(data) do {\
	MMC_TXSINGLECOL_G_RD(data);\
} while (0)

#define MMC_TXUNDERFLOWERROR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x748))

#define MMC_TXUNDERFLOWERROR_RD(data) do {\
	(data) = ioread32((void *)MMC_TXUNDERFLOWERROR_OFFSET);\
} while (0)

#define MMC_TXUNDERFLOWERROR_TXUNDERFLOWERROR_RD(data) do {\
	MMC_TXUNDERFLOWERROR_RD(data);\
} while (0)

#define MMC_TXBROADCASTPACKETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x744))

#define MMC_TXBROADCASTPACKETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TXBROADCASTPACKETS_GB_OFFSET);\
} while (0)

#define MMC_TXBROADCASTPACKETS_GB_TXBROADCASTPACKETS_GB_RD(data) do {\
	MMC_TXBROADCASTPACKETS_GB_RD(data);\
} while (0)

#define MMC_TXMULTICASTPACKETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x740))

#define MMC_TXMULTICASTPACKETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TXMULTICASTPACKETS_GB_OFFSET);\
} while (0)

#define MMC_TXMULTICASTPACKETS_GB_TXMULTICASTPACKETS_GB_RD(data) do {\
	MMC_TXMULTICASTPACKETS_GB_RD(data);\
} while (0)

#define MMC_TXUNICASTPACKETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x73c))

#define MMC_TXUNICASTPACKETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TXUNICASTPACKETS_GB_OFFSET);\
} while (0)

#define MMC_TXUNICASTPACKETS_GB_TXUNICASTPACKETS_GB_RD(data) do {\
	MMC_TXUNICASTPACKETS_GB_RD(data);\
} while (0)

#define MMC_TX1024TOMAXOCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x738))

#define MMC_TX1024TOMAXOCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TX1024TOMAXOCTETS_GB_OFFSET);\
} while (0)

#define MMC_TX1024TOMAXOCTETS_GB_TX1024TOMAXOCTETS_GB_RD(data) do {\
	MMC_TX1024TOMAXOCTETS_GB_RD(data);\
} while (0)

#define MMC_TX512TO1023OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x734))

#define MMC_TX512TO1023OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TX512TO1023OCTETS_GB_OFFSET);\
} while (0)

#define MMC_TX512TO1023OCTETS_GB_TX512TO1023OCTETS_GB_RD(data) do {\
	MMC_TX512TO1023OCTETS_GB_RD(data);\
} while (0)

#define MMC_TX256TO511OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x730))

#define MMC_TX256TO511OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TX256TO511OCTETS_GB_OFFSET);\
} while (0)

#define MMC_TX256TO511OCTETS_GB_TX256TO511OCTETS_GB_RD(data) do {\
	MMC_TX256TO511OCTETS_GB_RD(data);\
} while (0)

#define MMC_TX128TO255OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x72c))

#define MMC_TX128TO255OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TX128TO255OCTETS_GB_OFFSET);\
} while (0)

#define MMC_TX128TO255OCTETS_GB_TX128TO255OCTETS_GB_RD(data) do {\
	MMC_TX128TO255OCTETS_GB_RD(data);\
} while (0)

#define MMC_TX65TO127OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x728))

#define MMC_TX65TO127OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TX65TO127OCTETS_GB_OFFSET);\
} while (0)

#define MMC_TX65TO127OCTETS_GB_TX65TO127OCTETS_GB_RD(data) do {\
	MMC_TX65TO127OCTETS_GB_RD(data);\
} while (0)

#define MMC_TX64OCTETS_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x724))

#define MMC_TX64OCTETS_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TX64OCTETS_GB_OFFSET);\
} while (0)

#define MMC_TX64OCTETS_GB_TX64OCTETS_GB_RD(data) do {\
	MMC_TX64OCTETS_GB_RD(data);\
} while (0)

#define MMC_TXMULTICASTPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x720))

#define MMC_TXMULTICASTPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXMULTICASTPACKETS_G_OFFSET);\
} while (0)

#define MMC_TXMULTICASTPACKETS_G_TXMULTICASTPACKETS_G_RD(data) do {\
	MMC_TXMULTICASTPACKETS_G_RD(data);\
} while (0)

#define MMC_TXBROADCASTPACKETS_G_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x71c))

#define MMC_TXBROADCASTPACKETS_G_RD(data) do {\
	(data) = ioread32((void *)MMC_TXBROADCASTPACKETS_G_OFFSET);\
} while (0)

#define MMC_TXBROADCASTPACKETS_G_TXBROADCASTPACKETS_G_RD(data) do {\
	MMC_TXBROADCASTPACKETS_G_RD(data);\
} while (0)

#define MMC_TXPACKETCOUNT_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x718))

#define MMC_TXPACKETCOUNT_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TXPACKETCOUNT_GB_OFFSET);\
} while (0)

#define MMC_TXPACKETCOUNT_GB_TXPACKETCOUNT_GB_RD(data) do {\
	MMC_TXPACKETCOUNT_GB_RD(data);\
} while (0)

#define MMC_TXOCTETCOUNT_GB_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x714))

#define MMC_TXOCTETCOUNT_GB_RD(data) do {\
	(data) = ioread32((void *)MMC_TXOCTETCOUNT_GB_OFFSET);\
} while (0)

#define MMC_TXOCTETCOUNT_GB_TXOCTETCOUNT_GB_RD(data) do {\
	MMC_TXOCTETCOUNT_GB_RD(data);\
} while (0)

#define MMC_IPC_INTR_RX_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x808))

#define MMC_IPC_INTR_RX_RD(data) do {\
	(data) = ioread32((void *)MMC_IPC_INTR_RX_OFFSET);\
} while (0)


#define MMC_IPC_INTR_RX_RXICMP_ERR_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXICMP_ERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 29) & MMC_IPC_INTR_RX_RXICMP_ERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXICMP_GD_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXICMP_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 28) & MMC_IPC_INTR_RX_RXICMP_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXTCP_ERR_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXTCP_ERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 27) & MMC_IPC_INTR_RX_RXTCP_ERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXTCP_GD_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXTCP_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 26) & MMC_IPC_INTR_RX_RXTCP_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXUDP_ERR_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXUDP_ERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 25) & MMC_IPC_INTR_RX_RXUDP_ERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXUDP_GD_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXUDP_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 24) & MMC_IPC_INTR_RX_RXUDP_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV6_NOPAY_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV6_NOPAY_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 23) & MMC_IPC_INTR_RX_RXIPV6_NOPAY_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV6_HDRERR_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV6_HDRERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 22) & MMC_IPC_INTR_RX_RXIPV6_HDRERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV6_GD_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV6_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 21) & MMC_IPC_INTR_RX_RXIPV6_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_UDSBL_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_UDSBL_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 20) & MMC_IPC_INTR_RX_RXIPV4_UDSBL_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_FRAG_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_FRAG_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 19) & MMC_IPC_INTR_RX_RXIPV4_FRAG_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_NOPAY_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_NOPAY_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 18) & MMC_IPC_INTR_RX_RXIPV4_NOPAY_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_HDRERR_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_HDRERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 17) & MMC_IPC_INTR_RX_RXIPV4_HDRERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_GD_OCTETS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 16) & MMC_IPC_INTR_RX_RXIPV4_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXICMP_ERR_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXICMP_ERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 13) & MMC_IPC_INTR_RX_RXICMP_ERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXICMP_GD_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXICMP_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 12) & MMC_IPC_INTR_RX_RXICMP_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXTCP_ERR_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXTCP_ERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 11) & MMC_IPC_INTR_RX_RXTCP_ERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXTCP_GD_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXTCP_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 10) & MMC_IPC_INTR_RX_RXTCP_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXUDP_ERR_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXUDP_ERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 9) & MMC_IPC_INTR_RX_RXUDP_ERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXUDP_GD_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXUDP_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 8) & MMC_IPC_INTR_RX_RXUDP_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV6_NOPAY_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV6_NOPAY_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 7) & MMC_IPC_INTR_RX_RXIPV6_NOPAY_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV6_HDRERR_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV6_HDRERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 6) & MMC_IPC_INTR_RX_RXIPV6_HDRERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV6_GD_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV6_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 5) & MMC_IPC_INTR_RX_RXIPV6_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_UDSBL_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_UDSBL_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 4) & MMC_IPC_INTR_RX_RXIPV4_UDSBL_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_FRAG_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_FRAG_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 3) & MMC_IPC_INTR_RX_RXIPV4_FRAG_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_NOPAY_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_NOPAY_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 2) & MMC_IPC_INTR_RX_RXIPV4_NOPAY_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_HDRERR_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_HDRERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 1) & MMC_IPC_INTR_RX_RXIPV4_HDRERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_RX_RXIPV4_GD_FRMS_MASK (ULONG)(0x1)

#define MMC_IPC_INTR_RX_RXIPV4_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_RX_RD(data);\
	data = ((data >> 0) & MMC_IPC_INTR_RX_RXIPV4_GD_FRMS_MASK);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x800))

#define MMC_IPC_INTR_MASK_RX_WR(data) do {\
	iowrite32(data, (void *)MMC_IPC_INTR_MASK_RX_OFFSET);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RD(data) do {\
	(data) = ioread32((void *)MMC_IPC_INTR_MASK_RX_OFFSET);\
} while (0)


#define  MMC_IPC_INTR_MASK_RX_MASK_30 (ULONG)(0x3)


#define MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30 (ULONG)(0x3fffffff)


#define  MMC_IPC_INTR_MASK_RX_MASK_14 (ULONG)(0x3)


#define MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14 (ULONG)(0xffff3fff)


#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_WR_MASK (ULONG)(0xdfffffff)

#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_MASK)<<29));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 29) & MMC_IPC_INTR_MASK_RX_RXICMP_ERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_WR_MASK (ULONG)(0xefffffff)

#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_MASK)<<28));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 28) & MMC_IPC_INTR_MASK_RX_RXICMP_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_WR_MASK (ULONG)(0xf7ffffff)

#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_MASK)<<27));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 27) & MMC_IPC_INTR_MASK_RX_RXTCP_ERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_WR_MASK (ULONG)(0xfbffffff)

#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_MASK)<<26));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 26) & MMC_IPC_INTR_MASK_RX_RXTCP_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_WR_MASK (ULONG)(0xfdffffff)

#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_MASK)<<25));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 25) & MMC_IPC_INTR_MASK_RX_RXUDP_ERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_WR_MASK (ULONG)(0xfeffffff)

#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_MASK)<<24));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 24) & MMC_IPC_INTR_MASK_RX_RXUDP_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_WR_MASK (ULONG)(0xff7fffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_MASK)<<23));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 23) & MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_WR_MASK (ULONG)(0xffbfffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_MASK)<<22));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 22) & MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_WR_MASK (ULONG)(0xffdfffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_MASK)<<21));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 21) & MMC_IPC_INTR_MASK_RX_RXIPV6_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_WR_MASK (ULONG)(0xffefffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_MASK)<<20));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 20) & MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_WR_MASK (ULONG)(0xfff7ffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_MASK)<<19));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 19) & MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_WR_MASK (ULONG)(0xfffbffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_MASK)<<18));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 18) & MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_WR_MASK (ULONG)(0xfffdffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_MASK)<<17));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 17) & MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_WR_MASK (ULONG)(0xfffeffff)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_MASK)<<16));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 16) & MMC_IPC_INTR_MASK_RX_RXIPV4_GD_OCTETS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_WR_MASK (ULONG)(0xffffdfff)

#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_MASK)<<13));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 13) & MMC_IPC_INTR_MASK_RX_RXICMP_ERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_WR_MASK (ULONG)(0xffffefff)

#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_MASK)<<12));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 12) & MMC_IPC_INTR_MASK_RX_RXICMP_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_WR_MASK (ULONG)(0xfffff7ff)

#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_MASK)<<11));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 11) & MMC_IPC_INTR_MASK_RX_RXTCP_ERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_WR_MASK (ULONG)(0xfffffbff)

#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_MASK)<<10));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 10) & MMC_IPC_INTR_MASK_RX_RXTCP_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_WR_MASK (ULONG)(0xfffffdff)

#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_MASK)<<9));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 9) & MMC_IPC_INTR_MASK_RX_RXUDP_ERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_WR_MASK (ULONG)(0xfffffeff)

#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_MASK)<<8));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 8) & MMC_IPC_INTR_MASK_RX_RXUDP_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_WR_MASK (ULONG)(0xffffff7f)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_MASK)<<7));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 7) & MMC_IPC_INTR_MASK_RX_RXIPV6_NOPAY_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_WR_MASK (ULONG)(0xffffffbf)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_MASK)<<6));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 6) & MMC_IPC_INTR_MASK_RX_RXIPV6_HDRERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_WR_MASK (ULONG)(0xffffffdf)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_MASK)<<5));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 5) & MMC_IPC_INTR_MASK_RX_RXIPV6_GD_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_WR_MASK (ULONG)(0xffffffef)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_MASK)<<4));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 4) & MMC_IPC_INTR_MASK_RX_RXIPV4_UDSBL_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_WR_MASK (ULONG)(0xfffffff7)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_MASK)<<3));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 3) & MMC_IPC_INTR_MASK_RX_RXIPV4_FRAG_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_WR_MASK (ULONG)(0xfffffffb)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_MASK)<<2));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 2) & MMC_IPC_INTR_MASK_RX_RXIPV4_NOPAY_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_WR_MASK (ULONG)(0xfffffffd)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_MASK)<<1));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 1) & MMC_IPC_INTR_MASK_RX_RXIPV4_HDRERR_FRMS_MASK);\
} while (0)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_MASK (ULONG)(0x1)


#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_WR_MASK (ULONG)(0xfffffffe)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_WR(data) do {\
	ULONG v;\
	MMC_IPC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_30))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_30))<<30);\
	v = (v & (MMC_IPC_INTR_MASK_RX_RES_WR_MASK_14))\
	|(((0) & (MMC_IPC_INTR_MASK_RX_MASK_14))<<14);\
	v = ((v & MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_WR_MASK)\
	|((data & MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_MASK)<<0));\
	MMC_IPC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_RD(data) do {\
	MMC_IPC_INTR_MASK_RX_RD(data);\
	data = ((data >> 0) & MMC_IPC_INTR_MASK_RX_RXIPV4_GD_FRMS_MASK);\
} while (0)

#define MMC_INTR_MASK_TX_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x710))

#define MMC_INTR_MASK_TX_WR(data) do {\
	iowrite32(data, (void *)MMC_INTR_MASK_TX_OFFSET);\
} while (0)

#define MMC_INTR_MASK_TX_RD(data) do {\
	(data) = ioread32((void *)MMC_INTR_MASK_TX_OFFSET);\
} while (0)


#define  MMC_INTR_MASK_TX_MASK_25 (ULONG)(0x7f)


#define MMC_INTR_MASK_TX_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define MMC_INTR_MASK_TX_TXVLANFRAMES_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXVLANFRAMES_G_WR_MASK (ULONG)(0xfeffffff)

#define MMC_INTR_MASK_TX_TXVLANFRAMES_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXVLANFRAMES_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXVLANFRAMES_G_MASK)<<24));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXVLANFRAMES_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 24) & MMC_INTR_MASK_TX_TXVLANFRAMES_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXPAUSEFRAMES_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXPAUSEFRAMES_WR_MASK (ULONG)(0xff7fffff)

#define MMC_INTR_MASK_TX_TXPAUSEFRAMES_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXPAUSEFRAMES_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXPAUSEFRAMES_MASK)<<23));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXPAUSEFRAMES_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 23) & MMC_INTR_MASK_TX_TXPAUSEFRAMES_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXEXCESSDEF_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXEXCESSDEF_WR_MASK (ULONG)(0xffbfffff)

#define MMC_INTR_MASK_TX_TXEXCESSDEF_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXEXCESSDEF_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXEXCESSDEF_MASK)<<22));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXEXCESSDEF_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 22) & MMC_INTR_MASK_TX_TXEXCESSDEF_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXFRAMECOUNT_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXFRAMECOUNT_G_WR_MASK (ULONG)(0xffdfffff)

#define MMC_INTR_MASK_TX_TXFRAMECOUNT_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXFRAMECOUNT_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXFRAMECOUNT_G_MASK)<<21));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXFRAMECOUNT_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 21) & MMC_INTR_MASK_TX_TXFRAMECOUNT_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXOCTETCOUNT_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXOCTETCOUNT_G_WR_MASK (ULONG)(0xffefffff)

#define MMC_INTR_MASK_TX_TXOCTETCOUNT_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXOCTETCOUNT_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXOCTETCOUNT_G_MASK)<<20));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXOCTETCOUNT_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 20) & MMC_INTR_MASK_TX_TXOCTETCOUNT_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXCARRIERERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXCARRIERERROR_WR_MASK (ULONG)(0xfff7ffff)

#define MMC_INTR_MASK_TX_TXCARRIERERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXCARRIERERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXCARRIERERROR_MASK)<<19));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXCARRIERERROR_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 19) & MMC_INTR_MASK_TX_TXCARRIERERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXEXESSCOL_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXEXESSCOL_WR_MASK (ULONG)(0xfffbffff)

#define MMC_INTR_MASK_TX_TXEXESSCOL_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXEXESSCOL_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXEXESSCOL_MASK)<<18));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXEXESSCOL_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 18) & MMC_INTR_MASK_TX_TXEXESSCOL_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXLATECOL_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXLATECOL_WR_MASK (ULONG)(0xfffdffff)

#define MMC_INTR_MASK_TX_TXLATECOL_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXLATECOL_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXLATECOL_MASK)<<17));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXLATECOL_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 17) & MMC_INTR_MASK_TX_TXLATECOL_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXDEFERRED_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXDEFERRED_WR_MASK (ULONG)(0xfffeffff)

#define MMC_INTR_MASK_TX_TXDEFERRED_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXDEFERRED_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXDEFERRED_MASK)<<16));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXDEFERRED_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 16) & MMC_INTR_MASK_TX_TXDEFERRED_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXMULTICOL_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXMULTICOL_G_WR_MASK (ULONG)(0xffff7fff)

#define MMC_INTR_MASK_TX_TXMULTICOL_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXMULTICOL_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXMULTICOL_G_MASK)<<15));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXMULTICOL_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 15) & MMC_INTR_MASK_TX_TXMULTICOL_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXSINGLECOL_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXSINGLECOL_G_WR_MASK (ULONG)(0xffffbfff)

#define MMC_INTR_MASK_TX_TXSINGLECOL_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXSINGLECOL_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXSINGLECOL_G_MASK)<<14));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXSINGLECOL_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 14) & MMC_INTR_MASK_TX_TXSINGLECOL_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXUNDERFLOWERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXUNDERFLOWERROR_WR_MASK (ULONG)(0xffffdfff)

#define MMC_INTR_MASK_TX_TXUNDERFLOWERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXUNDERFLOWERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXUNDERFLOWERROR_MASK)<<13));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXUNDERFLOWERROR_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 13) & MMC_INTR_MASK_TX_TXUNDERFLOWERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_WR_MASK (ULONG)(0xffffefff)

#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_MASK)<<12));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 12) & MMC_INTR_MASK_TX_TXBROADCASTFRAMES_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_WR_MASK (ULONG)(0xfffff7ff)

#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_MASK)<<11));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 11) & MMC_INTR_MASK_TX_TXMULTICASTFRAMES_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_WR_MASK (ULONG)(0xfffffbff)

#define MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_MASK)<<10));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 10) & MMC_INTR_MASK_TX_TXUNICASTFRAMES_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_WR_MASK (ULONG)(0xfffffdff)

#define MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_MASK)<<9));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 9) & MMC_INTR_MASK_TX_TX1024TOMAXOCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_WR_MASK (ULONG)(0xfffffeff)

#define MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_MASK)<<8));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 8) & MMC_INTR_MASK_TX_TX512TO1023OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_WR_MASK (ULONG)(0xffffff7f)

#define MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_MASK)<<7));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 7) & MMC_INTR_MASK_TX_TX256TO511OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_WR_MASK (ULONG)(0xffffffbf)

#define MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_MASK)<<6));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 6) & MMC_INTR_MASK_TX_TX128TO255OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_WR_MASK (ULONG)(0xffffffdf)

#define MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_MASK)<<5));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 5) & MMC_INTR_MASK_TX_TX65TO127OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TX64OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TX64OCTETS_GB_WR_MASK (ULONG)(0xffffffef)

#define MMC_INTR_MASK_TX_TX64OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TX64OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TX64OCTETS_GB_MASK)<<4));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TX64OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 4) & MMC_INTR_MASK_TX_TX64OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_WR_MASK (ULONG)(0xfffffff7)

#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_MASK)<<3));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 3) & MMC_INTR_MASK_TX_TXMULTICASTFRAMES_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_WR_MASK (ULONG)(0xfffffffb)

#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_MASK)<<2));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 2) & MMC_INTR_MASK_TX_TXBROADCASTFRAMES_G_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_WR_MASK (ULONG)(0xfffffffd)

#define MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_MASK)<<1));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 1) & MMC_INTR_MASK_TX_TXFRAMECOUNT_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_WR_MASK (ULONG)(0xfffffffe)

#define MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_TX_RD(v);\
	v = (v & (MMC_INTR_MASK_TX_RES_WR_MASK_25))\
	|(((0) & (MMC_INTR_MASK_TX_MASK_25))<<25);\
	v = ((v & MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_MASK)<<0));\
	MMC_INTR_MASK_TX_WR(v);\
} while (0)

#define MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_RD(data) do {\
	MMC_INTR_MASK_TX_RD(data);\
	data = ((data >> 0) & MMC_INTR_MASK_TX_TXOCTETCOUNT_GB_MASK);\
} while (0)

#define MMC_INTR_MASK_RX_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x70c))

#define MMC_INTR_MASK_RX_WR(data) do {\
	iowrite32(data, (void *)MMC_INTR_MASK_RX_OFFSET);\
} while (0)

#define MMC_INTR_MASK_RX_RD(data) do {\
	(data) = ioread32((void *)MMC_INTR_MASK_RX_OFFSET);\
} while (0)


#define  MMC_INTR_MASK_RX_MASK_24 (ULONG)(0xff)


#define MMC_INTR_MASK_RX_RES_WR_MASK_24 (ULONG)(0xffffff)


#define MMC_INTR_MASK_RX_RXWATCHDOG_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXWATCHDOG_WR_MASK (ULONG)(0xff7fffff)

#define MMC_INTR_MASK_RX_RXWATCHDOG_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXWATCHDOG_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXWATCHDOG_MASK)<<23));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXWATCHDOG_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 23) & MMC_INTR_MASK_RX_RXWATCHDOG_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXVLANFRAMES_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXVLANFRAMES_GB_WR_MASK (ULONG)(0xffbfffff)

#define MMC_INTR_MASK_RX_RXVLANFRAMES_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXVLANFRAMES_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXVLANFRAMES_GB_MASK)<<22));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXVLANFRAMES_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 22) & MMC_INTR_MASK_RX_RXVLANFRAMES_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXFIFOOVERFLOW_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXFIFOOVERFLOW_WR_MASK (ULONG)(0xffdfffff)

#define MMC_INTR_MASK_RX_RXFIFOOVERFLOW_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXFIFOOVERFLOW_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXFIFOOVERFLOW_MASK)<<21));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXFIFOOVERFLOW_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 21) & MMC_INTR_MASK_RX_RXFIFOOVERFLOW_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXPAUSEFRAMES_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXPAUSEFRAMES_WR_MASK (ULONG)(0xffefffff)

#define MMC_INTR_MASK_RX_RXPAUSEFRAMES_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXPAUSEFRAMES_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXPAUSEFRAMES_MASK)<<20));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXPAUSEFRAMES_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 20) & MMC_INTR_MASK_RX_RXPAUSEFRAMES_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_WR_MASK (ULONG)(0xfff7ffff)

#define MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_MASK)<<19));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 19) & MMC_INTR_MASK_RX_RXOUTOFRANGETYPE_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXLENGTHERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXLENGTHERROR_WR_MASK (ULONG)(0xfffbffff)

#define MMC_INTR_MASK_RX_RXLENGTHERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXLENGTHERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXLENGTHERROR_MASK)<<18));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXLENGTHERROR_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 18) & MMC_INTR_MASK_RX_RXLENGTHERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_WR_MASK (ULONG)(0xfffdffff)

#define MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_MASK)<<17));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 17) & MMC_INTR_MASK_RX_RXUNICASTFRAMES_G_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_WR_MASK (ULONG)(0xfffeffff)

#define MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_MASK)<<16));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 16) & MMC_INTR_MASK_RX_RX1024TOMAXOCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_WR_MASK (ULONG)(0xffff7fff)

#define MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_MASK)<<15));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 15) & MMC_INTR_MASK_RX_RX512TO1023OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_WR_MASK (ULONG)(0xffffbfff)

#define MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_MASK)<<14));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 14) & MMC_INTR_MASK_RX_RX256TO511OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_WR_MASK (ULONG)(0xffffdfff)

#define MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_MASK)<<13));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 13) & MMC_INTR_MASK_RX_RX128TO255OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_WR_MASK (ULONG)(0xffffefff)

#define MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_MASK)<<12));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 12) & MMC_INTR_MASK_RX_RX65TO127OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RX64OCTETS_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RX64OCTETS_GB_WR_MASK (ULONG)(0xfffff7ff)

#define MMC_INTR_MASK_RX_RX64OCTETS_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RX64OCTETS_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RX64OCTETS_GB_MASK)<<11));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RX64OCTETS_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 11) & MMC_INTR_MASK_RX_RX64OCTETS_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXOVERSIZE_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXOVERSIZE_G_WR_MASK (ULONG)(0xfffffbff)

#define MMC_INTR_MASK_RX_RXOVERSIZE_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXOVERSIZE_G_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXOVERSIZE_G_MASK)<<10));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXOVERSIZE_G_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 10) & MMC_INTR_MASK_RX_RXOVERSIZE_G_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXUNDERSIZE_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXUNDERSIZE_G_WR_MASK (ULONG)(0xfffffdff)

#define MMC_INTR_MASK_RX_RXUNDERSIZE_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXUNDERSIZE_G_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXUNDERSIZE_G_MASK)<<9));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXUNDERSIZE_G_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 9) & MMC_INTR_MASK_RX_RXUNDERSIZE_G_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXJABBERERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXJABBERERROR_WR_MASK (ULONG)(0xfffffeff)

#define MMC_INTR_MASK_RX_RXJABBERERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXJABBERERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXJABBERERROR_MASK)<<8));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXJABBERERROR_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 8) & MMC_INTR_MASK_RX_RXJABBERERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXRUNTERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXRUNTERROR_WR_MASK (ULONG)(0xffffff7f)

#define MMC_INTR_MASK_RX_RXRUNTERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXRUNTERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXRUNTERROR_MASK)<<7));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXRUNTERROR_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 7) & MMC_INTR_MASK_RX_RXRUNTERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXALIGNMENTERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXALIGNMENTERROR_WR_MASK (ULONG)(0xffffffbf)

#define MMC_INTR_MASK_RX_RXALIGNMENTERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXALIGNMENTERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXALIGNMENTERROR_MASK)<<6));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXALIGNMENTERROR_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 6) & MMC_INTR_MASK_RX_RXALIGNMENTERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXCRCERROR_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXCRCERROR_WR_MASK (ULONG)(0xffffffdf)

#define MMC_INTR_MASK_RX_RXCRCERROR_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXCRCERROR_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXCRCERROR_MASK)<<5));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXCRCERROR_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 5) & MMC_INTR_MASK_RX_RXCRCERROR_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_WR_MASK (ULONG)(0xffffffef)

#define MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_MASK)<<4));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 4) & MMC_INTR_MASK_RX_RXMULTICASTFRAMES_G_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_WR_MASK (ULONG)(0xfffffff7)

#define MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_MASK)<<3));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 3) & MMC_INTR_MASK_RX_RXBROADCASTFRAMES_G_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXOCTETCOUNT_G_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXOCTETCOUNT_G_WR_MASK (ULONG)(0xfffffffb)

#define MMC_INTR_MASK_RX_RXOCTETCOUNT_G_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXOCTETCOUNT_G_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXOCTETCOUNT_G_MASK)<<2));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXOCTETCOUNT_G_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 2) & MMC_INTR_MASK_RX_RXOCTETCOUNT_G_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_WR_MASK (ULONG)(0xfffffffd)

#define MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_MASK)<<1));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 1) & MMC_INTR_MASK_RX_RXOCTETCOUNT_GB_MASK);\
} while (0)


#define MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_MASK (ULONG)(0x1)


#define MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_WR_MASK (ULONG)(0xfffffffe)

#define MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_WR(data) do {\
	ULONG v;\
	MMC_INTR_MASK_RX_RD(v);\
	v = (v & (MMC_INTR_MASK_RX_RES_WR_MASK_24))\
	|(((0) & (MMC_INTR_MASK_RX_MASK_24))<<24);\
	v = ((v & MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_WR_MASK)\
	|((data & MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_MASK)<<0));\
	MMC_INTR_MASK_RX_WR(v);\
} while (0)

#define MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_RD(data) do {\
	MMC_INTR_MASK_RX_RD(data);\
	data = ((data >> 0) & MMC_INTR_MASK_RX_RXFRAMECOUNT_GB_MASK);\
} while (0)

#define MMC_INTR_TX_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x708))

#define MMC_INTR_TX_WR(data) do {\
	iowrite32(data, (void *)MMC_INTR_TX_OFFSET);\
} while (0)

#define MMC_INTR_TX_RD(data) do {\
	(data) = ioread32((void *)MMC_INTR_TX_OFFSET);\
} while (0)


#define  MMC_INTR_TX_MASK_26 (ULONG)(0x3f)


#define MMC_INTR_TX_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MMC_INTR_TX_TXOSIZEGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXOSIZEGPIS_WR_MASK (ULONG)(0xfdffffff)

#define MMC_INTR_TX_TXOSIZEGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXOSIZEGPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXOSIZEGPIS_MASK)<<25));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXOSIZEGPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 25) & MMC_INTR_TX_TXOSIZEGPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXVLANGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXVLANGPIS_WR_MASK (ULONG)(0xfeffffff)

#define MMC_INTR_TX_TXVLANGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXVLANGPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXVLANGPIS_MASK)<<24));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXVLANGPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 24) & MMC_INTR_TX_TXVLANGPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXPAUSPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXPAUSPIS_WR_MASK (ULONG)(0xff7fffff)

#define MMC_INTR_TX_TXPAUSPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXPAUSPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXPAUSPIS_MASK)<<23));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXPAUSPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 23) & MMC_INTR_TX_TXPAUSPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXEXDEFPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXEXDEFPIS_WR_MASK (ULONG)(0xffbfffff)

#define MMC_INTR_TX_TXEXDEFPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXEXDEFPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXEXDEFPIS_MASK)<<22));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXEXDEFPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 22) & MMC_INTR_TX_TXEXDEFPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXGPKTIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXGPKTIS_WR_MASK (ULONG)(0xffdfffff)

#define MMC_INTR_TX_TXGPKTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXGPKTIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXGPKTIS_MASK)<<21));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXGPKTIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 21) & MMC_INTR_TX_TXGPKTIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXGOCTIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXGOCTIS_WR_MASK (ULONG)(0xffefffff)

#define MMC_INTR_TX_TXGOCTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXGOCTIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXGOCTIS_MASK)<<20));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXGOCTIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 20) & MMC_INTR_TX_TXGOCTIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXCARERPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXCARERPIS_WR_MASK (ULONG)(0xfff7ffff)

#define MMC_INTR_TX_TXCARERPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXCARERPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXCARERPIS_MASK)<<19));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXCARERPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 19) & MMC_INTR_TX_TXCARERPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXEXCOLPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXEXCOLPIS_WR_MASK (ULONG)(0xfffbffff)

#define MMC_INTR_TX_TXEXCOLPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXEXCOLPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXEXCOLPIS_MASK)<<18));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXEXCOLPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 18) & MMC_INTR_TX_TXEXCOLPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXLATCOLPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXLATCOLPIS_WR_MASK (ULONG)(0xfffdffff)

#define MMC_INTR_TX_TXLATCOLPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXLATCOLPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXLATCOLPIS_MASK)<<17));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXLATCOLPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 17) & MMC_INTR_TX_TXLATCOLPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXDEFPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXDEFPIS_WR_MASK (ULONG)(0xfffeffff)

#define MMC_INTR_TX_TXDEFPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXDEFPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXDEFPIS_MASK)<<16));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXDEFPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 16) & MMC_INTR_TX_TXDEFPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXMCOLGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXMCOLGPIS_WR_MASK (ULONG)(0xffff7fff)

#define MMC_INTR_TX_TXMCOLGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXMCOLGPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXMCOLGPIS_MASK)<<15));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXMCOLGPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 15) & MMC_INTR_TX_TXMCOLGPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXSCOLGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXSCOLGPIS_WR_MASK (ULONG)(0xffffbfff)

#define MMC_INTR_TX_TXSCOLGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXSCOLGPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXSCOLGPIS_MASK)<<14));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXSCOLGPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 14) & MMC_INTR_TX_TXSCOLGPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXUFLOWERFIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXUFLOWERFIS_WR_MASK (ULONG)(0xffffdfff)

#define MMC_INTR_TX_TXUFLOWERFIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXUFLOWERFIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXUFLOWERFIS_MASK)<<13));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXUFLOWERFIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 13) & MMC_INTR_TX_TXUFLOWERFIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXBCGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXBCGBPIS_WR_MASK (ULONG)(0xffffefff)

#define MMC_INTR_TX_TXBCGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXBCGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXBCGBPIS_MASK)<<12));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXBCGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 12) & MMC_INTR_TX_TXBCGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXMCGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXMCGBPIS_WR_MASK (ULONG)(0xfffff7ff)

#define MMC_INTR_TX_TXMCGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXMCGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXMCGBPIS_MASK)<<11));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXMCGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 11) & MMC_INTR_TX_TXMCGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXUCGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXUCGBPIS_WR_MASK (ULONG)(0xfffffbff)

#define MMC_INTR_TX_TXUCGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXUCGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXUCGBPIS_MASK)<<10));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXUCGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 10) & MMC_INTR_TX_TXUCGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TX1024TMAXOCTGBFIS_WR_MASK (ULONG)(0xfffffdff)

#define MMC_INTR_TX_TX1024TMAXOCTGBFIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TX1024TMAXOCTGBFIS_WR_MASK)\
	|((data & MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK)<<9));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TX1024TMAXOCTGBFIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 9) & MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK);\
} while (0)


#define MMC_INTR_TX_TX512T1023OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TX512T1023OCTGBPIS_WR_MASK (ULONG)(0xfffffeff)

#define MMC_INTR_TX_TX512T1023OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TX512T1023OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TX512T1023OCTGBPIS_MASK)<<8));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TX512T1023OCTGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 8) & MMC_INTR_TX_TX512T1023OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TX256T511OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TX256T511OCTGBPIS_WR_MASK (ULONG)(0xffffff7f)

#define MMC_INTR_TX_TX256T511OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TX256T511OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TX256T511OCTGBPIS_MASK)<<7));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TX256T511OCTGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 7) & MMC_INTR_TX_TX256T511OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TX128T255OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TX128T255OCTGBPIS_WR_MASK (ULONG)(0xffffffbf)

#define MMC_INTR_TX_TX128T255OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TX128T255OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TX128T255OCTGBPIS_MASK)<<6));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TX128T255OCTGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 6) & MMC_INTR_TX_TX128T255OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TX65T127OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TX65T127OCTGBPIS_WR_MASK (ULONG)(0xffffffdf)

#define MMC_INTR_TX_TX65T127OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TX65T127OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TX65T127OCTGBPIS_MASK)<<5));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TX65T127OCTGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 5) & MMC_INTR_TX_TX65T127OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TX64OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TX64OCTGBPIS_WR_MASK (ULONG)(0xffffffef)

#define MMC_INTR_TX_TX64OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TX64OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TX64OCTGBPIS_MASK)<<4));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TX64OCTGBPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 4) & MMC_INTR_TX_TX64OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXMCGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXMCGPIS_WR_MASK (ULONG)(0xfffffff7)

#define MMC_INTR_TX_TXMCGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXMCGPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXMCGPIS_MASK)<<3));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXMCGPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 3) & MMC_INTR_TX_TXMCGPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXBCGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXBCGPIS_WR_MASK (ULONG)(0xfffffffb)

#define MMC_INTR_TX_TXBCGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXBCGPIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXBCGPIS_MASK)<<2));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXBCGPIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 2) & MMC_INTR_TX_TXBCGPIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXGBPKTIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXGBPKTIS_WR_MASK (ULONG)(0xfffffffd)

#define MMC_INTR_TX_TXGBPKTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXGBPKTIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXGBPKTIS_MASK)<<1));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXGBPKTIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 1) & MMC_INTR_TX_TXGBPKTIS_MASK);\
} while (0)


#define MMC_INTR_TX_TXGBOCTIS_MASK (ULONG)(0x1)


#define MMC_INTR_TX_TXGBOCTIS_WR_MASK (ULONG)(0xfffffffe)

#define MMC_INTR_TX_TXGBOCTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_TX_RD(v);\
	v = (v & (MMC_INTR_TX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_TX_MASK_26))<<26);\
	v = ((v & MMC_INTR_TX_TXGBOCTIS_WR_MASK)\
	|((data & MMC_INTR_TX_TXGBOCTIS_MASK)<<0));\
	MMC_INTR_TX_WR(v);\
} while (0)

#define MMC_INTR_TX_TXGBOCTIS_RD(data) do {\
	MMC_INTR_TX_RD(data);\
	data = ((data >> 0) & MMC_INTR_TX_TXGBOCTIS_MASK);\
} while (0)

#define MMC_INTR_RX_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x704))

#define MMC_INTR_RX_WR(data) do {\
	iowrite32(data, (void *)MMC_INTR_RX_OFFSET);\
} while (0)

#define MMC_INTR_RX_RD(data) do {\
	(data) = ioread32((void *)MMC_INTR_RX_OFFSET);\
} while (0)


#define  MMC_INTR_RX_MASK_26 (ULONG)(0x3f)


#define MMC_INTR_RX_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define MMC_INTR_RX_RXCTRLPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXCTRLPIS_WR_MASK (ULONG)(0xfdffffff)

#define MMC_INTR_RX_RXCTRLPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXCTRLPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXCTRLPIS_MASK)<<25));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXCTRLPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 25) & MMC_INTR_RX_RXCTRLPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXRCVERRPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXRCVERRPIS_WR_MASK (ULONG)(0xfeffffff)

#define MMC_INTR_RX_RXRCVERRPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXRCVERRPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXRCVERRPIS_MASK)<<24));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXRCVERRPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 24) & MMC_INTR_RX_RXRCVERRPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXWDOGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXWDOGPIS_WR_MASK (ULONG)(0xff7fffff)

#define MMC_INTR_RX_RXWDOGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXWDOGPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXWDOGPIS_MASK)<<23));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXWDOGPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 23) & MMC_INTR_RX_RXWDOGPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXVLANGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXVLANGBPIS_WR_MASK (ULONG)(0xffbfffff)

#define MMC_INTR_RX_RXVLANGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXVLANGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXVLANGBPIS_MASK)<<22));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXVLANGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 22) & MMC_INTR_RX_RXVLANGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXFOVPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXFOVPIS_WR_MASK (ULONG)(0xffdfffff)

#define MMC_INTR_RX_RXFOVPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXFOVPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXFOVPIS_MASK)<<21));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXFOVPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 21) & MMC_INTR_RX_RXFOVPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXPAUSPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXPAUSPIS_WR_MASK (ULONG)(0xffefffff)

#define MMC_INTR_RX_RXPAUSPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXPAUSPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXPAUSPIS_MASK)<<20));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXPAUSPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 20) & MMC_INTR_RX_RXPAUSPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXORANGEPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXORANGEPIS_WR_MASK (ULONG)(0xfff7ffff)

#define MMC_INTR_RX_RXORANGEPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXORANGEPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXORANGEPIS_MASK)<<19));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXORANGEPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 19) & MMC_INTR_RX_RXORANGEPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXLENERPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXLENERPIS_WR_MASK (ULONG)(0xfffbffff)

#define MMC_INTR_RX_RXLENERPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXLENERPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXLENERPIS_MASK)<<18));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXLENERPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 18) & MMC_INTR_RX_RXLENERPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXUCBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXUCBPIS_WR_MASK (ULONG)(0xfffdffff)

#define MMC_INTR_RX_RXUCBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXUCBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXUCBPIS_MASK)<<17));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXUCBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 17) & MMC_INTR_RX_RXUCBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RX1024TMAXOCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RX1024TMAXOCTGBPIS_WR_MASK (ULONG)(0xfffeffff)

#define MMC_INTR_RX_RX1024TMAXOCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RX1024TMAXOCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RX1024TMAXOCTGBPIS_MASK)<<16));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RX1024TMAXOCTGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 16) & MMC_INTR_RX_RX1024TMAXOCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RX512T1023OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RX512T1023OCTGBPIS_WR_MASK (ULONG)(0xffff7fff)

#define MMC_INTR_RX_RX512T1023OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RX512T1023OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RX512T1023OCTGBPIS_MASK)<<15));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RX512T1023OCTGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 15) & MMC_INTR_RX_RX512T1023OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RX256T511OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RX256T511OCTGBPIS_WR_MASK (ULONG)(0xffffbfff)

#define MMC_INTR_RX_RX256T511OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RX256T511OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RX256T511OCTGBPIS_MASK)<<14));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RX256T511OCTGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 14) & MMC_INTR_RX_RX256T511OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RX128T255OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RX128T255OCTGBPIS_WR_MASK (ULONG)(0xffffdfff)

#define MMC_INTR_RX_RX128T255OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RX128T255OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RX128T255OCTGBPIS_MASK)<<13));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RX128T255OCTGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 13) & MMC_INTR_RX_RX128T255OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RX65T127OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RX65T127OCTGBPIS_WR_MASK (ULONG)(0xffffefff)

#define MMC_INTR_RX_RX65T127OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RX65T127OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RX65T127OCTGBPIS_MASK)<<12));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RX65T127OCTGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 12) & MMC_INTR_RX_RX65T127OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RX64OCTGBPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RX64OCTGBPIS_WR_MASK (ULONG)(0xfffff7ff)

#define MMC_INTR_RX_RX64OCTGBPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RX64OCTGBPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RX64OCTGBPIS_MASK)<<11));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RX64OCTGBPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 11) & MMC_INTR_RX_RX64OCTGBPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXOSIZEGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXOSIZEGPIS_WR_MASK (ULONG)(0xfffffbff)

#define MMC_INTR_RX_RXOSIZEGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXOSIZEGPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXOSIZEGPIS_MASK)<<10));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXOSIZEGPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 10) & MMC_INTR_RX_RXOSIZEGPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXUSIZEGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXUSIZEGPIS_WR_MASK (ULONG)(0xfffffdff)

#define MMC_INTR_RX_RXUSIZEGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXUSIZEGPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXUSIZEGPIS_MASK)<<9));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXUSIZEGPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 9) & MMC_INTR_RX_RXUSIZEGPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXJABERPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXJABERPIS_WR_MASK (ULONG)(0xfffffeff)

#define MMC_INTR_RX_RXJABERPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXJABERPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXJABERPIS_MASK)<<8));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXJABERPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 8) & MMC_INTR_RX_RXJABERPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXRUNTRIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXRUNTRIS_WR_MASK (ULONG)(0xffffff7f)

#define MMC_INTR_RX_RXRUNTRIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXRUNTRIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXRUNTRIS_MASK)<<7));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXRUNTRIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 7) & MMC_INTR_RX_RXRUNTRIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXALGNERPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXALGNERPIS_WR_MASK (ULONG)(0xffffffbf)

#define MMC_INTR_RX_RXALGNERPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXALGNERPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXALGNERPIS_MASK)<<6));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXALGNERPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 6) & MMC_INTR_RX_RXALGNERPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXCRCERPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXCRCERPIS_WR_MASK (ULONG)(0xffffffdf)

#define MMC_INTR_RX_RXCRCERPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXCRCERPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXCRCERPIS_MASK)<<5));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXCRCERPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 5) & MMC_INTR_RX_RXCRCERPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXMCGPIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXMCGPIS_WR_MASK (ULONG)(0xffffffef)

#define MMC_INTR_RX_RXMCGPIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXMCGPIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXMCGPIS_MASK)<<4));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXMCGPIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 4) & MMC_INTR_RX_RXMCGPIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXBCGTIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXBCGTIS_WR_MASK (ULONG)(0xfffffff7)

#define MMC_INTR_RX_RXBCGTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXBCGTIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXBCGTIS_MASK)<<3));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXBCGTIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 3) & MMC_INTR_RX_RXBCGTIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXGOCTIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXGOCTIS_WR_MASK (ULONG)(0xfffffffb)

#define MMC_INTR_RX_RXGOCTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXGOCTIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXGOCTIS_MASK)<<2));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXGOCTIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 2) & MMC_INTR_RX_RXGOCTIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXGBOCTIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXGBOCTIS_WR_MASK (ULONG)(0xfffffffd)

#define MMC_INTR_RX_RXGBOCTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXGBOCTIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXGBOCTIS_MASK)<<1));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXGBOCTIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 1) & MMC_INTR_RX_RXGBOCTIS_MASK);\
} while (0)


#define MMC_INTR_RX_RXGBPKTIS_MASK (ULONG)(0x1)


#define MMC_INTR_RX_RXGBPKTIS_WR_MASK (ULONG)(0xfffffffe)

#define MMC_INTR_RX_RXGBPKTIS_WR(data) do {\
	ULONG v;\
	MMC_INTR_RX_RD(v);\
	v = (v & (MMC_INTR_RX_RES_WR_MASK_26))\
	|(((0) & (MMC_INTR_RX_MASK_26))<<26);\
	v = ((v & MMC_INTR_RX_RXGBPKTIS_WR_MASK)\
	|((data & MMC_INTR_RX_RXGBPKTIS_MASK)<<0));\
	MMC_INTR_RX_WR(v);\
} while (0)

#define MMC_INTR_RX_RXGBPKTIS_RD(data) do {\
	MMC_INTR_RX_RD(data);\
	data = ((data >> 0) & MMC_INTR_RX_RXGBPKTIS_MASK);\
} while (0)

#define MMC_CNTRL_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x700))

#define MMC_CNTRL_WR(data) do {\
	iowrite32(data, (void *)MMC_CNTRL_OFFSET);\
} while (0)

#define MMC_CNTRL_RD(data) do {\
	(data) = ioread32((void *)MMC_CNTRL_OFFSET);\
} while (0)


#define  MMC_CNTRL_MASK_9 (ULONG)(0x7fffff)


#define MMC_CNTRL_RES_WR_MASK_9 (ULONG)(0x1ff)


#define  MMC_CNTRL_MASK_6 (ULONG)(0x3)


#define MMC_CNTRL_RES_WR_MASK_6 (ULONG)(0xffffff3f)


#define MMC_CNTRL_UCDBC_MASK (ULONG)(0x1)


#define MMC_CNTRL_UCDBC_WR_MASK (ULONG)(0xfffffeff)

#define MMC_CNTRL_UCDBC_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_UCDBC_WR_MASK)\
	|((data & MMC_CNTRL_UCDBC_MASK)<<8));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_UCDBC_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 8) & MMC_CNTRL_UCDBC_MASK);\
} while (0)


#define MMC_CNTRL_CNPRSTLVL_MASK (ULONG)(0x1)


#define MMC_CNTRL_CNPRSTLVL_WR_MASK (ULONG)(0xffffffdf)

#define MMC_CNTRL_CNPRSTLVL_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_CNPRSTLVL_WR_MASK)\
	|((data & MMC_CNTRL_CNPRSTLVL_MASK)<<5));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_CNPRSTLVL_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 5) & MMC_CNTRL_CNPRSTLVL_MASK);\
} while (0)


#define MMC_CNTRL_CNTPRST_MASK (ULONG)(0x1)


#define MMC_CNTRL_CNTPRST_WR_MASK (ULONG)(0xffffffef)

#define MMC_CNTRL_CNTPRST_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_CNTPRST_WR_MASK)\
	|((data & MMC_CNTRL_CNTPRST_MASK)<<4));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_CNTPRST_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 4) & MMC_CNTRL_CNTPRST_MASK);\
} while (0)


#define MMC_CNTRL_CNTFREEZ_MASK (ULONG)(0x1)


#define MMC_CNTRL_CNTFREEZ_WR_MASK (ULONG)(0xfffffff7)

#define MMC_CNTRL_CNTFREEZ_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_CNTFREEZ_WR_MASK)\
	|((data & MMC_CNTRL_CNTFREEZ_MASK)<<3));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_CNTFREEZ_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 3) & MMC_CNTRL_CNTFREEZ_MASK);\
} while (0)


#define MMC_CNTRL_RSTONRD_MASK (ULONG)(0x1)


#define MMC_CNTRL_RSTONRD_WR_MASK (ULONG)(0xfffffffb)

#define MMC_CNTRL_RSTONRD_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_RSTONRD_WR_MASK)\
	|((data & MMC_CNTRL_RSTONRD_MASK)<<2));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_RSTONRD_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 2) & MMC_CNTRL_RSTONRD_MASK);\
} while (0)


#define MMC_CNTRL_CNTSTOPRO_MASK (ULONG)(0x1)


#define MMC_CNTRL_CNTSTOPRO_WR_MASK (ULONG)(0xfffffffd)

#define MMC_CNTRL_CNTSTOPRO_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_CNTSTOPRO_WR_MASK)\
	|((data & MMC_CNTRL_CNTSTOPRO_MASK)<<1));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_CNTSTOPRO_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 1) & MMC_CNTRL_CNTSTOPRO_MASK);\
} while (0)


#define MMC_CNTRL_CNTRST_MASK (ULONG)(0x1)


#define MMC_CNTRL_CNTRST_WR_MASK (ULONG)(0xfffffffe)

#define MMC_CNTRL_CNTRST_WR(data) do {\
	ULONG v;\
	MMC_CNTRL_RD(v);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_9))\
	|(((0) & (MMC_CNTRL_MASK_9))<<9);\
	v = (v & (MMC_CNTRL_RES_WR_MASK_6))\
	|(((0) & (MMC_CNTRL_MASK_6))<<6);\
	v = ((v & MMC_CNTRL_CNTRST_WR_MASK)\
	|((data & MMC_CNTRL_CNTRST_MASK)<<0));\
	MMC_CNTRL_WR(v);\
} while (0)

#define MMC_CNTRL_CNTRST_RD(data) do {\
	MMC_CNTRL_RD(data);\
	data = ((data >> 0) & MMC_CNTRL_CNTRST_MASK);\
} while (0)

#define MAC_MA1LR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x30c))

#define MAC_MA1LR_WR(data) do {\
	iowrite32(data, (void *)MAC_MA1LR_OFFSET);\
} while (0)

#define MAC_MA1LR_RD(data) do {\
	(data) = ioread32((void *)MAC_MA1LR_OFFSET);\
} while (0)

#define MAC_MA1LR_ADDRLO_WR(data) do {\
	MAC_MA1LR_WR(data);\
} while (0)

#define MAC_MA1LR_ADDRLO_RD(data) do {\
	MAC_MA1LR_RD(data);\
} while (0)

#define MAC_MA1HR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x308))

#define MAC_MA1HR_WR(data) do {\
	iowrite32(data, (void *)MAC_MA1HR_OFFSET);\
} while (0)

#define MAC_MA1HR_RD(data) do {\
	(data) = ioread32((void *)MAC_MA1HR_OFFSET);\
} while (0)


#define  MAC_MA1HR_MASK_19 (ULONG)(0x1f)


#define MAC_MA1HR_RES_WR_MASK_19 (ULONG)(0xff07ffff)


#define MAC_MA1HR_AE_MASK (ULONG)(0x1)


#define MAC_MA1HR_AE_WR_MASK (ULONG)(0x7fffffff)

#define MAC_MA1HR_AE_WR(data) do {\
	ULONG v;\
	MAC_MA1HR_RD(v);\
	v = (v & (MAC_MA1HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1HR_MASK_19))<<19);\
	v = ((v & MAC_MA1HR_AE_WR_MASK)\
	|((data & MAC_MA1HR_AE_MASK)<<31));\
	MAC_MA1HR_WR(v);\
} while (0)

#define MAC_MA1HR_AE_RD(data) do {\
	MAC_MA1HR_RD(data);\
	data = ((data >> 31) & MAC_MA1HR_AE_MASK);\
} while (0)


#define MAC_MA1HR_SA_MASK (ULONG)(0x1)


#define MAC_MA1HR_SA_WR_MASK (ULONG)(0xbfffffff)

#define MAC_MA1HR_SA_WR(data) do {\
	ULONG v;\
	MAC_MA1HR_RD(v);\
	v = (v & (MAC_MA1HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1HR_MASK_19))<<19);\
	v = ((v & MAC_MA1HR_SA_WR_MASK)\
	|((data & MAC_MA1HR_SA_MASK)<<30));\
	MAC_MA1HR_WR(v);\
} while (0)

#define MAC_MA1HR_SA_RD(data) do {\
	MAC_MA1HR_RD(data);\
	data = ((data >> 30) & MAC_MA1HR_SA_MASK);\
} while (0)


#define MAC_MA1HR_MBC_MASK (ULONG)(0x3f)


#define MAC_MA1HR_MBC_WR_MASK (ULONG)(0xc0ffffff)

#define MAC_MA1HR_MBC_WR(data) do {\
	ULONG v;\
	MAC_MA1HR_RD(v);\
	v = (v & (MAC_MA1HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1HR_MASK_19))<<19);\
	v = ((v & MAC_MA1HR_MBC_WR_MASK)\
	|((data & MAC_MA1HR_MBC_MASK)<<24));\
	MAC_MA1HR_WR(v);\
} while (0)

#define MAC_MA1HR_MBC_RD(data) do {\
	MAC_MA1HR_RD(data);\
	data = ((data >> 24) & MAC_MA1HR_MBC_MASK);\
} while (0)


#define MAC_MA1HR_DCS_MASK (ULONG)(0x7)


#define MAC_MA1HR_DCS_WR_MASK (ULONG)(0xfff8ffff)

#define MAC_MA1HR_DCS_WR(data) do {\
	ULONG v;\
	MAC_MA1HR_RD(v);\
	v = (v & (MAC_MA1HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1HR_MASK_19))<<19);\
	v = ((v & MAC_MA1HR_DCS_WR_MASK)\
	|((data & MAC_MA1HR_DCS_MASK)<<16));\
	MAC_MA1HR_WR(v);\
} while (0)

#define MAC_MA1HR_DCS_RD(data) do {\
	MAC_MA1HR_RD(data);\
	data = ((data >> 16) & MAC_MA1HR_DCS_MASK);\
} while (0)


#define MAC_MA1HR_ADDRHI_MASK (ULONG)(0xffff)


#define MAC_MA1HR_ADDRHI_WR_MASK (ULONG)(0xffff0000)

#define MAC_MA1HR_ADDRHI_WR(data) do {\
	ULONG v;\
	MAC_MA1HR_RD(v);\
	v = (v & (MAC_MA1HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1HR_MASK_19))<<19);\
	v = ((v & MAC_MA1HR_ADDRHI_WR_MASK)\
	|((data & MAC_MA1HR_ADDRHI_MASK)<<0));\
	MAC_MA1HR_WR(v);\
} while (0)

#define MAC_MA1HR_ADDRHI_RD(data) do {\
	MAC_MA1HR_RD(data);\
	data = ((data >> 0) & MAC_MA1HR_ADDRHI_MASK);\
} while (0)

#define MAC_MA0LR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x304))

#define MAC_MA0LR_WR(data) do {\
	iowrite32(data, (void *)MAC_MA0LR_OFFSET);\
} while (0)

#define MAC_MA0LR_RD(data) do {\
	(data) = ioread32((void *)MAC_MA0LR_OFFSET);\
} while (0)

#define MAC_MA0LR_ADDRLO_WR(data) do {\
	MAC_MA0LR_WR(data);\
} while (0)

#define MAC_MA0LR_ADDRLO_RD(data) do {\
	MAC_MA0LR_RD(data);\
} while (0)

#define MAC_MA0HR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x300))

#define MAC_MA0HR_WR(data) do {\
	iowrite32(data, (void *)MAC_MA0HR_OFFSET);\
} while (0)

#define MAC_MA0HR_RD(data) do {\
	(data) = ioread32((void *)MAC_MA0HR_OFFSET);\
} while (0)


#define  MAC_MA0HR_MASK_19 (ULONG)(0xfff)


#define MAC_MA0HR_RES_WR_MASK_19 (ULONG)(0x8007ffff)


#define MAC_MA0HR_AE_MASK (ULONG)(0x1)


#define MAC_MA0HR_AE_WR_MASK (ULONG)(0x7fffffff)

#define MAC_MA0HR_AE_WR(data) do {\
	ULONG v;\
	MAC_MA0HR_RD(v);\
	v = (v & (MAC_MA0HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA0HR_MASK_19))<<19);\
	v = ((v & MAC_MA0HR_AE_WR_MASK)\
	|((data & MAC_MA0HR_AE_MASK)<<31));\
	MAC_MA0HR_WR(v);\
} while (0)

#define MAC_MA0HR_AE_RD(data) do {\
	MAC_MA0HR_RD(data);\
	data = ((data >> 31) & MAC_MA0HR_AE_MASK);\
} while (0)


#define MAC_MA0HR_DCS_MASK (ULONG)(0x7)


#define MAC_MA0HR_DCS_WR_MASK (ULONG)(0xfff8ffff)

#define MAC_MA0HR_DCS_WR(data) do {\
	ULONG v;\
	MAC_MA0HR_RD(v);\
	v = (v & (MAC_MA0HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA0HR_MASK_19))<<19);\
	v = ((v & MAC_MA0HR_DCS_WR_MASK)\
	|((data & MAC_MA0HR_DCS_MASK)<<16));\
	MAC_MA0HR_WR(v);\
} while (0)

#define MAC_MA0HR_DCS_RD(data) do {\
	MAC_MA0HR_RD(data);\
	data = ((data >> 16) & MAC_MA0HR_DCS_MASK);\
} while (0)


#define MAC_MA0HR_ADDRHI_MASK (ULONG)(0xffff)


#define MAC_MA0HR_ADDRHI_WR_MASK (ULONG)(0xffff0000)

#define MAC_MA0HR_ADDRHI_WR(data) do {\
	ULONG v;\
	MAC_MA0HR_RD(v);\
	v = (v & (MAC_MA0HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA0HR_MASK_19))<<19);\
	v = ((v & MAC_MA0HR_ADDRHI_WR_MASK)\
	|((data & MAC_MA0HR_ADDRHI_MASK)<<0));\
	MAC_MA0HR_WR(v);\
} while (0)

#define MAC_MA0HR_ADDRHI_RD(data) do {\
	MAC_MA0HR_RD(data);\
	data = ((data >> 0) & MAC_MA0HR_ADDRHI_MASK);\
} while (0)

#define MAC_GPIOR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x208))

#define MAC_GPIOR_WR(data) do {\
	iowrite32(data, (void *)MAC_GPIOR_OFFSET);\
} while (0)

#define MAC_GPIOR_RD(data) do {\
	(data) = ioread32((void *)MAC_GPIOR_OFFSET);\
} while (0)


#define  MAC_GPIOR_MASK_28 (ULONG)(0xf)


#define MAC_GPIOR_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define  MAC_GPIOR_MASK_20 (ULONG)(0xf)


#define MAC_GPIOR_RES_WR_MASK_20 (ULONG)(0xff0fffff)


#define  MAC_GPIOR_MASK_12 (ULONG)(0xf)


#define MAC_GPIOR_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MAC_GPIOR_MASK_4 (ULONG)(0xf)


#define MAC_GPIOR_RES_WR_MASK_4 (ULONG)(0xffffff0f)


#define MAC_GPIOR_GPIT_MASK (ULONG)(0xf)


#define MAC_GPIOR_GPIT_WR_MASK (ULONG)(0xf0ffffff)

#define MAC_GPIOR_GPIT_WR(data) do {\
	ULONG v;\
	MAC_GPIOR_RD(v);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_28))\
	|(((0) & (MAC_GPIOR_MASK_28))<<28);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_20))\
	|(((0) & (MAC_GPIOR_MASK_20))<<20);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_12))\
	|(((0) & (MAC_GPIOR_MASK_12))<<12);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_4))\
	|(((0) & (MAC_GPIOR_MASK_4))<<4);\
	v = ((v & MAC_GPIOR_GPIT_WR_MASK)\
	|((data & MAC_GPIOR_GPIT_MASK)<<24));\
	MAC_GPIOR_WR(v);\
} while (0)

#define MAC_GPIOR_GPIT_RD(data) do {\
	MAC_GPIOR_RD(data);\
	data = ((data >> 24) & MAC_GPIOR_GPIT_MASK);\
} while (0)


#define MAC_GPIOR_GPIE_MASK (ULONG)(0xf)


#define MAC_GPIOR_GPIE_WR_MASK (ULONG)(0xfff0ffff)

#define MAC_GPIOR_GPIE_WR(data) do {\
	ULONG v;\
	MAC_GPIOR_RD(v);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_28))\
	|(((0) & (MAC_GPIOR_MASK_28))<<28);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_20))\
	|(((0) & (MAC_GPIOR_MASK_20))<<20);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_12))\
	|(((0) & (MAC_GPIOR_MASK_12))<<12);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_4))\
	|(((0) & (MAC_GPIOR_MASK_4))<<4);\
	v = ((v & MAC_GPIOR_GPIE_WR_MASK)\
	|((data & MAC_GPIOR_GPIE_MASK)<<16));\
	MAC_GPIOR_WR(v);\
} while (0)

#define MAC_GPIOR_GPIE_RD(data) do {\
	MAC_GPIOR_RD(data);\
	data = ((data >> 16) & MAC_GPIOR_GPIE_MASK);\
} while (0)


#define MAC_GPIOR_GPO_MASK (ULONG)(0xf)


#define MAC_GPIOR_GPO_WR_MASK (ULONG)(0xfffff0ff)

#define MAC_GPIOR_GPO_WR(data) do {\
	ULONG v;\
	MAC_GPIOR_RD(v);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_28))\
	|(((0) & (MAC_GPIOR_MASK_28))<<28);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_20))\
	|(((0) & (MAC_GPIOR_MASK_20))<<20);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_12))\
	|(((0) & (MAC_GPIOR_MASK_12))<<12);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_4))\
	|(((0) & (MAC_GPIOR_MASK_4))<<4);\
	v = ((v & MAC_GPIOR_GPO_WR_MASK)\
	|((data & MAC_GPIOR_GPO_MASK)<<8));\
	MAC_GPIOR_WR(v);\
} while (0)

#define MAC_GPIOR_GPO_RD(data) do {\
	MAC_GPIOR_RD(data);\
	data = ((data >> 8) & MAC_GPIOR_GPO_MASK);\
} while (0)


#define MAC_GPIOR_GPIS_MASK (ULONG)(0xf)


#define MAC_GPIOR_GPIS_WR_MASK (ULONG)(0xfffffff0)

#define MAC_GPIOR_GPIS_WR(data) do {\
	ULONG v;\
	MAC_GPIOR_RD(v);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_28))\
	|(((0) & (MAC_GPIOR_MASK_28))<<28);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_20))\
	|(((0) & (MAC_GPIOR_MASK_20))<<20);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_12))\
	|(((0) & (MAC_GPIOR_MASK_12))<<12);\
	v = (v & (MAC_GPIOR_RES_WR_MASK_4))\
	|(((0) & (MAC_GPIOR_MASK_4))<<4);\
	v = ((v & MAC_GPIOR_GPIS_WR_MASK)\
	|((data & MAC_GPIOR_GPIS_MASK)<<0));\
	MAC_GPIOR_WR(v);\
} while (0)

#define MAC_GPIOR_GPIS_RD(data) do {\
	MAC_GPIOR_RD(data);\
	data = ((data >> 0) & MAC_GPIOR_GPIS_MASK);\
} while (0)

#define MAC_GMIIDR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x204))

#define MAC_GMIIDR_WR(data) do {\
	iowrite32(data, (void *)MAC_GMIIDR_OFFSET);\
} while (0)

#define MAC_GMIIDR_RD(data) do {\
	(data) = ioread32((void *)MAC_GMIIDR_OFFSET);\
} while (0)


#define MAC_GMIIDR_RA_MASK (ULONG)(0xffff)


#define MAC_GMIIDR_RA_WR_MASK (ULONG)(0xffff)

#define MAC_GMIIDR_RA_WR(data) do {\
	ULONG v;\
	MAC_GMIIDR_RD(v);\
	v = ((v & MAC_GMIIDR_RA_WR_MASK)\
	|((data & MAC_GMIIDR_RA_MASK)<<16));\
	MAC_GMIIDR_WR(v);\
} while (0)

#define MAC_GMIIDR_RA_RD(data) do {\
	MAC_GMIIDR_RD(data);\
	data = ((data >> 16) & MAC_GMIIDR_RA_MASK);\
} while (0)


#define MAC_GMIIDR_GD_MASK (ULONG)(0xffff)


#define MAC_GMIIDR_GD_WR_MASK (ULONG)(0xffff0000)

#define MAC_GMIIDR_GD_WR(data) do {\
	ULONG v;\
	MAC_GMIIDR_RD(v);\
	v = ((v & MAC_GMIIDR_GD_WR_MASK)\
	|((data & MAC_GMIIDR_GD_MASK)<<0));\
	MAC_GMIIDR_WR(v);\
} while (0)

#define MAC_GMIIDR_GD_RD(data) do {\
	MAC_GMIIDR_RD(data);\
	data = ((data >> 0) & MAC_GMIIDR_GD_MASK);\
} while (0)

#define MAC_GMIIAR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x200))

#define MAC_GMIIAR_WR(data) do {\
	iowrite32(data, (void *)MAC_GMIIAR_OFFSET);\
} while (0)

#define MAC_GMIIAR_RD(data) do {\
	(data) = ioread32((void *)MAC_GMIIAR_OFFSET);\
} while (0)


#define  MAC_GMIIAR_MASK_26 (ULONG)(0x3f)


#define MAC_GMIIAR_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define  MAC_GMIIAR_MASK_12 (ULONG)(0xf)


#define MAC_GMIIAR_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define  MAC_GMIIAR_MASK_5 (ULONG)(0x7)


#define MAC_GMIIAR_RES_WR_MASK_5 (ULONG)(0xffffff1f)


#define MAC_GMIIAR_PA_MASK (ULONG)(0x1f)


#define MAC_GMIIAR_PA_WR_MASK (ULONG)(0xfc1fffff)

#define MAC_GMIIAR_PA_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_PA_WR_MASK)\
	|((data & MAC_GMIIAR_PA_MASK)<<21));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_PA_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 21) & MAC_GMIIAR_PA_MASK);\
} while (0)


#define MAC_GMIIAR_GR_MASK (ULONG)(0x1f)


#define MAC_GMIIAR_GR_WR_MASK (ULONG)(0xffe0ffff)

#define MAC_GMIIAR_GR_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_GR_WR_MASK)\
	|((data & MAC_GMIIAR_GR_MASK)<<16));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_GR_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 16) & MAC_GMIIAR_GR_MASK);\
} while (0)


#define MAC_GMIIAR_CR_MASK (ULONG)(0xf)


#define MAC_GMIIAR_CR_WR_MASK (ULONG)(0xfffff0ff)

#define MAC_GMIIAR_CR_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_CR_WR_MASK)\
	|((data & MAC_GMIIAR_CR_MASK)<<8));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_CR_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 8) & MAC_GMIIAR_CR_MASK);\
} while (0)


#define MAC_GMIIAR_SKAP_MASK (ULONG)(0x1)


#define MAC_GMIIAR_SKAP_WR_MASK (ULONG)(0xffffffef)

#define MAC_GMIIAR_SKAP_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_SKAP_WR_MASK)\
	|((data & MAC_GMIIAR_SKAP_MASK)<<4));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_SKAP_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 4) & MAC_GMIIAR_SKAP_MASK);\
} while (0)


#define MAC_GMIIAR_GOC_MASK (ULONG)(0x3)


#define MAC_GMIIAR_GOC_WR_MASK (ULONG)(0xfffffff3)

#define MAC_GMIIAR_GOC_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_GOC_WR_MASK)\
	|((data & MAC_GMIIAR_GOC_MASK)<<2));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_GOC_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 2) & MAC_GMIIAR_GOC_MASK);\
} while (0)


#define MAC_GMIIAR_C45E_MASK (ULONG)(0x1)


#define MAC_GMIIAR_C45E_WR_MASK (ULONG)(0xfffffffd)

#define MAC_GMIIAR_C45E_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_C45E_WR_MASK)\
	|((data & MAC_GMIIAR_C45E_MASK)<<1));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_C45E_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 1) & MAC_GMIIAR_C45E_MASK);\
} while (0)


#define MAC_GMIIAR_GB_MASK (ULONG)(0x1)


#define MAC_GMIIAR_GB_WR_MASK (ULONG)(0xfffffffe)

#define MAC_GMIIAR_GB_WR(data) do {\
	ULONG v;\
	MAC_GMIIAR_RD(v);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_26))\
	|(((0) & (MAC_GMIIAR_MASK_26))<<26);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_12))\
	|(((0) & (MAC_GMIIAR_MASK_12))<<12);\
	v = (v & (MAC_GMIIAR_RES_WR_MASK_5))\
	|(((0) & (MAC_GMIIAR_MASK_5))<<5);\
	v = ((v & MAC_GMIIAR_GB_WR_MASK)\
	|((data & MAC_GMIIAR_GB_MASK)<<0));\
	MAC_GMIIAR_WR(v);\
} while (0)

#define MAC_GMIIAR_GB_RD(data) do {\
	MAC_GMIIAR_RD(data);\
	data = ((data >> 0) & MAC_GMIIAR_GB_MASK);\
} while (0)

#define MAC_HFR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x124))

#define MAC_HFR2_RD(data) do {\
	(data) = ioread32((void *)MAC_HFR2_OFFSET);\
} while (0)


#define MAC_HFR2_AUXSNAPNUM_MASK (ULONG)(0x7)

#define MAC_HFR2_AUXSNAPNUM_RD(data) do {\
	MAC_HFR2_RD(data);\
	data = ((data >> 28) & MAC_HFR2_AUXSNAPNUM_MASK);\
} while (0)


#define MAC_HFR2_PPSOUTNUM_MASK (ULONG)(0x7)

#define MAC_HFR2_PPSOUTNUM_RD(data) do {\
	MAC_HFR2_RD(data);\
	data = ((data >> 24) & MAC_HFR2_PPSOUTNUM_MASK);\
} while (0)


#define MAC_HFR2_TXCHCNT_MASK (ULONG)(0xf)

#define MAC_HFR2_TXCHCNT_RD(data) do {\
	MAC_HFR2_RD(data);\
	data = ((data >> 18) & MAC_HFR2_TXCHCNT_MASK);\
} while (0)


#define MAC_HFR2_RXCHCNT_MASK (ULONG)(0xf)

#define MAC_HFR2_RXCHCNT_RD(data) do {\
	MAC_HFR2_RD(data);\
	data = ((data >> 12) & MAC_HFR2_RXCHCNT_MASK);\
} while (0)


#define MAC_HFR2_TXQCNT_MASK (ULONG)(0xf)

#define MAC_HFR2_TXQCNT_RD(data) do {\
	MAC_HFR2_RD(data);\
	data = ((data >> 6) & MAC_HFR2_TXQCNT_MASK);\
} while (0)


#define MAC_HFR2_RXQCNT_MASK (ULONG)(0xf)

#define MAC_HFR2_RXQCNT_RD(data) do {\
	MAC_HFR2_RD(data);\
	data = ((data >> 0) & MAC_HFR2_RXQCNT_MASK);\
} while (0)

#define MAC_HFR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x120))

#define MAC_HFR1_RD(data) do {\
	(data) = ioread32((void *)MAC_HFR1_OFFSET);\
} while (0)


#define MAC_HFR1_L3L4FILTERNUM_MASK (ULONG)(0xf)

#define MAC_HFR1_L3L4FILTERNUM_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 27) & MAC_HFR1_L3L4FILTERNUM_MASK);\
} while (0)


#define MAC_HFR1_HASHTBLSZ_MASK (ULONG)(0x3)

#define MAC_HFR1_HASHTBLSZ_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 24) & MAC_HFR1_HASHTBLSZ_MASK);\
} while (0)


#define MAC_HFR1_LPMODEEN_MASK (ULONG)(0x1)

#define MAC_HFR1_LPMODEEN_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 23) & MAC_HFR1_LPMODEEN_MASK);\
} while (0)


#define MAC_HFR1_AVSEL_MASK (ULONG)(0x1)

#define MAC_HFR1_AVSEL_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 20) & MAC_HFR1_AVSEL_MASK);\
} while (0)


#define MAC_HFR1_DMADEBUGEN_MASK (ULONG)(0x1)

#define MAC_HFR1_DMADEBUGEN_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 19) & MAC_HFR1_DMADEBUGEN_MASK);\
} while (0)


#define MAC_HFR1_TSOEN_MASK (ULONG)(0x1)

#define MAC_HFR1_TSOEN_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 18) & MAC_HFR1_TSOEN_MASK);\
} while (0)


#define MAC_HFR1_SPHEN_MASK (ULONG)(0x1)

#define MAC_HFR1_SPHEN_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 17) & MAC_HFR1_SPHEN_MASK);\
} while (0)


#define MAC_HFR1_DCBEN_MASK (ULONG)(0x1)

#define MAC_HFR1_DCBEN_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 16) & MAC_HFR1_DCBEN_MASK);\
} while (0)


#define MAC_HFR1_ADVTHWORD_MASK (ULONG)(0x1)

#define MAC_HFR1_ADVTHWORD_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 13) & MAC_HFR1_ADVTHWORD_MASK);\
} while (0)


#define MAC_HFR1_TXFIFOSIZE_MASK (ULONG)(0x1f)

#define MAC_HFR1_TXFIFOSIZE_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 6) & MAC_HFR1_TXFIFOSIZE_MASK);\
} while (0)


#define MAC_HFR1_RXFIFOSIZE_MASK (ULONG)(0x1f)

#define MAC_HFR1_RXFIFOSIZE_RD(data) do {\
	MAC_HFR1_RD(data);\
	data = ((data >> 0) & MAC_HFR1_RXFIFOSIZE_MASK);\
} while (0)

#define MAC_HFR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11c))

#define MAC_HFR0_RD(data) do {\
	(data) = ioread32((void *)MAC_HFR0_OFFSET);\
} while (0)


#define MAC_HFR0_ACTPHYSEL_MASK (ULONG)(0x7)

#define MAC_HFR0_ACTPHYSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 28) & MAC_HFR0_ACTPHYSEL_MASK);\
} while (0)


#define MAC_HFR0_SAVLANINS_MASK (ULONG)(0x1)

#define MAC_HFR0_SAVLANINS_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 27) & MAC_HFR0_SAVLANINS_MASK);\
} while (0)


#define MAC_HFR0_TSINTSEL_MASK (ULONG)(0x3)

#define MAC_HFR0_TSINTSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 25) & MAC_HFR0_TSINTSEL_MASK);\
} while (0)


#define MAC_HFR0_MACADR64SEL_MASK (ULONG)(0x1)

#define MAC_HFR0_MACADR64SEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 24) & MAC_HFR0_MACADR64SEL_MASK);\
} while (0)


#define MAC_HFR0_MACADR32SEL_MASK (ULONG)(0x1)

#define MAC_HFR0_MACADR32SEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 23) & MAC_HFR0_MACADR32SEL_MASK);\
} while (0)


#define MAC_HFR0_ADDMACADRSEL_MASK (ULONG)(0x1f)

#define MAC_HFR0_ADDMACADRSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 18) & MAC_HFR0_ADDMACADRSEL_MASK);\
} while (0)


#define MAC_HFR0_RXCOE_MASK (ULONG)(0x1)

#define MAC_HFR0_RXCOE_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 16) & MAC_HFR0_RXCOE_MASK);\
} while (0)


#define MAC_HFR0_TXCOESEL_MASK (ULONG)(0x1)

#define MAC_HFR0_TXCOESEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 14) & MAC_HFR0_TXCOESEL_MASK);\
} while (0)


#define MAC_HFR0_EEESEL_MASK (ULONG)(0x1)

#define MAC_HFR0_EEESEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 13) & MAC_HFR0_EEESEL_MASK);\
} while (0)


#define MAC_HFR0_TSSSEL_MASK (ULONG)(0x1)

#define MAC_HFR0_TSSSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 12) & MAC_HFR0_TSSSEL_MASK);\
} while (0)


#define MAC_HFR0_ARPOFFLDEN_MASK (ULONG)(0x1)

#define MAC_HFR0_ARPOFFLDEN_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 9) & MAC_HFR0_ARPOFFLDEN_MASK);\
} while (0)


#define MAC_HFR0_MMCSEL_MASK (ULONG)(0x1)

#define MAC_HFR0_MMCSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 8) & MAC_HFR0_MMCSEL_MASK);\
} while (0)


#define MAC_HFR0_MGKSEL_MASK (ULONG)(0x1)

#define MAC_HFR0_MGKSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 7) & MAC_HFR0_MGKSEL_MASK);\
} while (0)


#define MAC_HFR0_RWKSEL_MASK (ULONG)(0x1)

#define MAC_HFR0_RWKSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 6) & MAC_HFR0_RWKSEL_MASK);\
} while (0)


#define MAC_HFR0_SMASEL_MASK (ULONG)(0x1)

#define MAC_HFR0_SMASEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 5) & MAC_HFR0_SMASEL_MASK);\
} while (0)


#define MAC_HFR0_VLANHASEL_MASK (ULONG)(0x1)

#define MAC_HFR0_VLANHASEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 4) & MAC_HFR0_VLANHASEL_MASK);\
} while (0)


#define MAC_HFR0_PCSSEL_MASK (ULONG)(0x1)

#define MAC_HFR0_PCSSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 3) & MAC_HFR0_PCSSEL_MASK);\
} while (0)


#define MAC_HFR0_HDSEL_MASK (ULONG)(0x1)

#define MAC_HFR0_HDSEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 2) & MAC_HFR0_HDSEL_MASK);\
} while (0)


#define MAC_HFR0_GMIISEL_MASK (ULONG)(0x1)

#define MAC_HFR0_GMIISEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 1) & MAC_HFR0_GMIISEL_MASK);\
} while (0)


#define MAC_HFR0_MIISEL_MASK (ULONG)(0x1)

#define MAC_HFR0_MIISEL_RD(data) do {\
	MAC_HFR0_RD(data);\
	data = ((data >> 0) & MAC_HFR0_MIISEL_MASK);\
} while (0)

#define MAC_MDR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x114))

#define MAC_MDR_RD(data) do {\
	(data) = ioread32((void *)MAC_MDR_OFFSET);\
} while (0)


#define MAC_MDR_TFCSTS_MASK (ULONG)(0x3)

#define MAC_MDR_TFCSTS_RD(data) do {\
	MAC_MDR_RD(data);\
	data = ((data >> 17) & MAC_MDR_TFCSTS_MASK);\
} while (0)


#define MAC_MDR_TPESTS_MASK (ULONG)(0x1)

#define MAC_MDR_TPESTS_RD(data) do {\
	MAC_MDR_RD(data);\
	data = ((data >> 16) & MAC_MDR_TPESTS_MASK);\
} while (0)


#define MAC_MDR_RFCFCSTS_MASK (ULONG)(0x3)

#define MAC_MDR_RFCFCSTS_RD(data) do {\
	MAC_MDR_RD(data);\
	data = ((data >> 1) & MAC_MDR_RFCFCSTS_MASK);\
} while (0)


#define MAC_MDR_RPESTS_MASK (ULONG)(0x1)

#define MAC_MDR_RPESTS_RD(data) do {\
	MAC_MDR_RD(data);\
	data = ((data >> 0) & MAC_MDR_RPESTS_MASK);\
} while (0)

#define MAC_VR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x110))

#define MAC_VR_RD(data) do {\
	(data) = ioread32((void *)MAC_VR_OFFSET);\
} while (0)


#define MAC_VR_USERVER_MASK (ULONG)(0xff)

#define MAC_VR_USERVER_RD(data) do {\
	MAC_VR_RD(data);\
	data = ((data >> 8) & MAC_VR_USERVER_MASK);\
} while (0)


#define MAC_VR_SNPSVER_MASK (ULONG)(0xff)

#define MAC_VR_SNPSVER_RD(data) do {\
	MAC_VR_RD(data);\
	data = ((data >> 0) & MAC_VR_SNPSVER_MASK);\
} while (0)

#define MAC_HTR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x2c))

#define MAC_HTR7_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR7_OFFSET);\
} while (0)

#define MAC_HTR7_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR7_OFFSET);\
} while (0)

#define MAC_HTR7_HT_WR(data) do {\
	MAC_HTR7_WR(data);\
} while (0)

#define MAC_HTR7_HT_RD(data) do {\
	MAC_HTR7_RD(data);\
} while (0)

#define MAC_HTR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x28))

#define MAC_HTR6_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR6_OFFSET);\
} while (0)

#define MAC_HTR6_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR6_OFFSET);\
} while (0)

#define MAC_HTR6_HT_WR(data) do {\
	MAC_HTR6_WR(data);\
} while (0)

#define MAC_HTR6_HT_RD(data) do {\
	MAC_HTR6_RD(data);\
} while (0)

#define MAC_HTR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x24))

#define MAC_HTR5_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR5_OFFSET);\
} while (0)

#define MAC_HTR5_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR5_OFFSET);\
} while (0)

#define MAC_HTR5_HT_WR(data) do {\
	MAC_HTR5_WR(data);\
} while (0)

#define MAC_HTR5_HT_RD(data) do {\
	MAC_HTR5_RD(data);\
} while (0)

#define MAC_HTR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x20))

#define MAC_HTR4_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR4_OFFSET);\
} while (0)

#define MAC_HTR4_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR4_OFFSET);\
} while (0)

#define MAC_HTR4_HT_WR(data) do {\
	MAC_HTR4_WR(data);\
} while (0)

#define MAC_HTR4_HT_RD(data) do {\
	MAC_HTR4_RD(data);\
} while (0)

#define MAC_HTR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1c))

#define MAC_HTR3_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR3_OFFSET);\
} while (0)

#define MAC_HTR3_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR3_OFFSET);\
} while (0)

#define MAC_HTR3_HT_WR(data) do {\
	MAC_HTR3_WR(data);\
} while (0)

#define MAC_HTR3_HT_RD(data) do {\
	MAC_HTR3_RD(data);\
} while (0)

#define MAC_HTR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x18))

#define MAC_HTR2_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR2_OFFSET);\
} while (0)

#define MAC_HTR2_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR2_OFFSET);\
} while (0)

#define MAC_HTR2_HT_WR(data) do {\
	MAC_HTR2_WR(data);\
} while (0)

#define MAC_HTR2_HT_RD(data) do {\
	MAC_HTR2_RD(data);\
} while (0)

#define MAC_HTR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14))

#define MAC_HTR1_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR1_OFFSET);\
} while (0)

#define MAC_HTR1_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR1_OFFSET);\
} while (0)

#define MAC_HTR1_HT_WR(data) do {\
	MAC_HTR1_WR(data);\
} while (0)

#define MAC_HTR1_HT_RD(data) do {\
	MAC_HTR1_RD(data);\
} while (0)

#define MAC_HTR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x10))

#define MAC_HTR0_WR(data) do {\
	iowrite32(data, (void *)MAC_HTR0_OFFSET);\
} while (0)

#define MAC_HTR0_RD(data) do {\
	(data) = ioread32((void *)MAC_HTR0_OFFSET);\
} while (0)

#define MAC_HTR0_HT_WR(data) do {\
	MAC_HTR0_WR(data);\
} while (0)

#define MAC_HTR0_HT_RD(data) do {\
	MAC_HTR0_RD(data);\
} while (0)

#define DMA_RIWTR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14b8))

#define DMA_RIWTR7_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR7_OFFSET);\
} while (0)

#define DMA_RIWTR7_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR7_OFFSET);\
} while (0)


#define  DMA_RIWTR7_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR7_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR7_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR7_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR7_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR7_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR7_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR7_RWT_WR_MASK)\
	|((data & DMA_RIWTR7_RWT_MASK)<<0));\
	DMA_RIWTR7_WR(v);\
} while (0)

#define DMA_RIWTR7_RWT_RD(data) do {\
	DMA_RIWTR7_RD(data);\
	data = ((data >> 0) & DMA_RIWTR7_RWT_MASK);\
} while (0)

#define DMA_RIWTR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1438))

#define DMA_RIWTR6_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR6_OFFSET);\
} while (0)

#define DMA_RIWTR6_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR6_OFFSET);\
} while (0)


#define  DMA_RIWTR6_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR6_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR6_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR6_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR6_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR6_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR6_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR6_RWT_WR_MASK)\
	|((data & DMA_RIWTR6_RWT_MASK)<<0));\
	DMA_RIWTR6_WR(v);\
} while (0)

#define DMA_RIWTR6_RWT_RD(data) do {\
	DMA_RIWTR6_RD(data);\
	data = ((data >> 0) & DMA_RIWTR6_RWT_MASK);\
} while (0)

#define DMA_RIWTR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13b8))

#define DMA_RIWTR5_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR5_OFFSET);\
} while (0)

#define DMA_RIWTR5_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR5_OFFSET);\
} while (0)


#define  DMA_RIWTR5_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR5_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR5_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR5_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR5_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR5_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR5_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR5_RWT_WR_MASK)\
	|((data & DMA_RIWTR5_RWT_MASK)<<0));\
	DMA_RIWTR5_WR(v);\
} while (0)

#define DMA_RIWTR5_RWT_RD(data) do {\
	DMA_RIWTR5_RD(data);\
	data = ((data >> 0) & DMA_RIWTR5_RWT_MASK);\
} while (0)

#define DMA_RIWTR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1338))

#define DMA_RIWTR4_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR4_OFFSET);\
} while (0)

#define DMA_RIWTR4_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR4_OFFSET);\
} while (0)


#define  DMA_RIWTR4_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR4_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR4_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR4_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR4_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR4_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR4_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR4_RWT_WR_MASK)\
	|((data & DMA_RIWTR4_RWT_MASK)<<0));\
	DMA_RIWTR4_WR(v);\
} while (0)

#define DMA_RIWTR4_RWT_RD(data) do {\
	DMA_RIWTR4_RD(data);\
	data = ((data >> 0) & DMA_RIWTR4_RWT_MASK);\
} while (0)

#define DMA_RIWTR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12b8))

#define DMA_RIWTR3_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR3_OFFSET);\
} while (0)

#define DMA_RIWTR3_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR3_OFFSET);\
} while (0)


#define  DMA_RIWTR3_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR3_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR3_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR3_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR3_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR3_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR3_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR3_RWT_WR_MASK)\
	|((data & DMA_RIWTR3_RWT_MASK)<<0));\
	DMA_RIWTR3_WR(v);\
} while (0)

#define DMA_RIWTR3_RWT_RD(data) do {\
	DMA_RIWTR3_RD(data);\
	data = ((data >> 0) & DMA_RIWTR3_RWT_MASK);\
} while (0)

#define DMA_RIWTR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1238))

#define DMA_RIWTR2_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR2_OFFSET);\
} while (0)

#define DMA_RIWTR2_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR2_OFFSET);\
} while (0)


#define  DMA_RIWTR2_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR2_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR2_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR2_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR2_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR2_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR2_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR2_RWT_WR_MASK)\
	|((data & DMA_RIWTR2_RWT_MASK)<<0));\
	DMA_RIWTR2_WR(v);\
} while (0)

#define DMA_RIWTR2_RWT_RD(data) do {\
	DMA_RIWTR2_RD(data);\
	data = ((data >> 0) & DMA_RIWTR2_RWT_MASK);\
} while (0)

#define DMA_RIWTR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11b8))

#define DMA_RIWTR1_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR1_OFFSET);\
} while (0)

#define DMA_RIWTR1_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR1_OFFSET);\
} while (0)


#define  DMA_RIWTR1_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR1_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR1_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR1_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR1_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR1_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR1_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR1_RWT_WR_MASK)\
	|((data & DMA_RIWTR1_RWT_MASK)<<0));\
	DMA_RIWTR1_WR(v);\
} while (0)

#define DMA_RIWTR1_RWT_RD(data) do {\
	DMA_RIWTR1_RD(data);\
	data = ((data >> 0) & DMA_RIWTR1_RWT_MASK);\
} while (0)

#define DMA_RIWTR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1138))

#define DMA_RIWTR0_WR(data) do {\
	iowrite32(data, (void *)DMA_RIWTR0_OFFSET);\
} while (0)

#define DMA_RIWTR0_RD(data) do {\
	(data) = ioread32((void *)DMA_RIWTR0_OFFSET);\
} while (0)


#define  DMA_RIWTR0_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR0_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR0_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR0_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR0_RWT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR0_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR0_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR0_RWT_WR_MASK)\
	|((data & DMA_RIWTR0_RWT_MASK)<<0));\
	DMA_RIWTR0_WR(v);\
} while (0)

#define DMA_RIWTR0_RWT_RD(data) do {\
	DMA_RIWTR0_RD(data);\
	data = ((data >> 0) & DMA_RIWTR0_RWT_MASK);\
} while (0)

#define DMA_RDRLR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14b0))

#define DMA_RDRLR7_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR7_OFFSET);\
} while (0)

#define DMA_RDRLR7_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR7_OFFSET);\
} while (0)


#define  DMA_RDRLR7_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR7_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR7_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR7_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR7_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR7_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR7_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR7_RDRL_WR_MASK)\
	|((data & DMA_RDRLR7_RDRL_MASK)<<0));\
	DMA_RDRLR7_WR(v);\
} while (0)

#define DMA_RDRLR7_RDRL_RD(data) do {\
	DMA_RDRLR7_RD(data);\
	data = ((data >> 0) & DMA_RDRLR7_RDRL_MASK);\
} while (0)

#define DMA_RDRLR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1430))

#define DMA_RDRLR6_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR6_OFFSET);\
} while (0)

#define DMA_RDRLR6_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR6_OFFSET);\
} while (0)


#define  DMA_RDRLR6_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR6_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR6_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR6_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR6_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR6_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR6_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR6_RDRL_WR_MASK)\
	|((data & DMA_RDRLR6_RDRL_MASK)<<0));\
	DMA_RDRLR6_WR(v);\
} while (0)

#define DMA_RDRLR6_RDRL_RD(data) do {\
	DMA_RDRLR6_RD(data);\
	data = ((data >> 0) & DMA_RDRLR6_RDRL_MASK);\
} while (0)

#define DMA_RDRLR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13b0))

#define DMA_RDRLR5_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR5_OFFSET);\
} while (0)

#define DMA_RDRLR5_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR5_OFFSET);\
} while (0)


#define  DMA_RDRLR5_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR5_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR5_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR5_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR5_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR5_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR5_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR5_RDRL_WR_MASK)\
	|((data & DMA_RDRLR5_RDRL_MASK)<<0));\
	DMA_RDRLR5_WR(v);\
} while (0)

#define DMA_RDRLR5_RDRL_RD(data) do {\
	DMA_RDRLR5_RD(data);\
	data = ((data >> 0) & DMA_RDRLR5_RDRL_MASK);\
} while (0)

#define DMA_RDRLR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1330))

#define DMA_RDRLR4_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR4_OFFSET);\
} while (0)

#define DMA_RDRLR4_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR4_OFFSET);\
} while (0)


#define  DMA_RDRLR4_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR4_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR4_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR4_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR4_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR4_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR4_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR4_RDRL_WR_MASK)\
	|((data & DMA_RDRLR4_RDRL_MASK)<<0));\
	DMA_RDRLR4_WR(v);\
} while (0)

#define DMA_RDRLR4_RDRL_RD(data) do {\
	DMA_RDRLR4_RD(data);\
	data = ((data >> 0) & DMA_RDRLR4_RDRL_MASK);\
} while (0)

#define DMA_RDRLR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12b0))

#define DMA_RDRLR3_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR3_OFFSET);\
} while (0)

#define DMA_RDRLR3_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR3_OFFSET);\
} while (0)


#define  DMA_RDRLR3_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR3_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR3_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR3_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR3_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR3_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR3_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR3_RDRL_WR_MASK)\
	|((data & DMA_RDRLR3_RDRL_MASK)<<0));\
	DMA_RDRLR3_WR(v);\
} while (0)

#define DMA_RDRLR3_RDRL_RD(data) do {\
	DMA_RDRLR3_RD(data);\
	data = ((data >> 0) & DMA_RDRLR3_RDRL_MASK);\
} while (0)

#define DMA_RDRLR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1230))

#define DMA_RDRLR2_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR2_OFFSET);\
} while (0)

#define DMA_RDRLR2_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR2_OFFSET);\
} while (0)


#define  DMA_RDRLR2_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR2_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR2_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR2_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR2_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR2_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR2_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR2_RDRL_WR_MASK)\
	|((data & DMA_RDRLR2_RDRL_MASK)<<0));\
	DMA_RDRLR2_WR(v);\
} while (0)

#define DMA_RDRLR2_RDRL_RD(data) do {\
	DMA_RDRLR2_RD(data);\
	data = ((data >> 0) & DMA_RDRLR2_RDRL_MASK);\
} while (0)

#define DMA_RDRLR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11b0))

#define DMA_RDRLR1_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR1_OFFSET);\
} while (0)

#define DMA_RDRLR1_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR1_OFFSET);\
} while (0)


#define  DMA_RDRLR1_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR1_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR1_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR1_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR1_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR1_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR1_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR1_RDRL_WR_MASK)\
	|((data & DMA_RDRLR1_RDRL_MASK)<<0));\
	DMA_RDRLR1_WR(v);\
} while (0)

#define DMA_RDRLR1_RDRL_RD(data) do {\
	DMA_RDRLR1_RD(data);\
	data = ((data >> 0) & DMA_RDRLR1_RDRL_MASK);\
} while (0)

#define DMA_RDRLR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1130))

#define DMA_RDRLR0_WR(data) do {\
	iowrite32(data, (void *)DMA_RDRLR0_OFFSET);\
} while (0)

#define DMA_RDRLR0_RD(data) do {\
	(data) = ioread32((void *)DMA_RDRLR0_OFFSET);\
} while (0)


#define  DMA_RDRLR0_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR0_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR0_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR0_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR0_RDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR0_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR0_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR0_RDRL_WR_MASK)\
	|((data & DMA_RDRLR0_RDRL_MASK)<<0));\
	DMA_RDRLR0_WR(v);\
} while (0)

#define DMA_RDRLR0_RDRL_RD(data) do {\
	DMA_RDRLR0_RD(data);\
	data = ((data >> 0) & DMA_RDRLR0_RDRL_MASK);\
} while (0)

#define DMA_TDRLR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14ac))

#define DMA_TDRLR7_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR7_OFFSET);\
} while (0)

#define DMA_TDRLR7_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR7_OFFSET);\
} while (0)


#define  DMA_TDRLR7_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR7_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR7_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR7_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR7_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR7_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR7_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR7_TDRL_WR_MASK)\
	|((data & DMA_TDRLR7_TDRL_MASK)<<0));\
	DMA_TDRLR7_WR(v);\
} while (0)

#define DMA_TDRLR7_TDRL_RD(data) do {\
	DMA_TDRLR7_RD(data);\
	data = ((data >> 0) & DMA_TDRLR7_TDRL_MASK);\
} while (0)

#define DMA_TDRLR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x142c))

#define DMA_TDRLR6_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR6_OFFSET);\
} while (0)

#define DMA_TDRLR6_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR6_OFFSET);\
} while (0)


#define  DMA_TDRLR6_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR6_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR6_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR6_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR6_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR6_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR6_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR6_TDRL_WR_MASK)\
	|((data & DMA_TDRLR6_TDRL_MASK)<<0));\
	DMA_TDRLR6_WR(v);\
} while (0)

#define DMA_TDRLR6_TDRL_RD(data) do {\
	DMA_TDRLR6_RD(data);\
	data = ((data >> 0) & DMA_TDRLR6_TDRL_MASK);\
} while (0)

#define DMA_TDRLR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13ac))

#define DMA_TDRLR5_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR5_OFFSET);\
} while (0)

#define DMA_TDRLR5_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR5_OFFSET);\
} while (0)


#define  DMA_TDRLR5_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR5_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR5_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR5_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR5_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR5_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR5_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR5_TDRL_WR_MASK)\
	|((data & DMA_TDRLR5_TDRL_MASK)<<0));\
	DMA_TDRLR5_WR(v);\
} while (0)

#define DMA_TDRLR5_TDRL_RD(data) do {\
	DMA_TDRLR5_RD(data);\
	data = ((data >> 0) & DMA_TDRLR5_TDRL_MASK);\
} while (0)

#define DMA_TDRLR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x132c))

#define DMA_TDRLR4_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR4_OFFSET);\
} while (0)

#define DMA_TDRLR4_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR4_OFFSET);\
} while (0)


#define  DMA_TDRLR4_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR4_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR4_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR4_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR4_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR4_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR4_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR4_TDRL_WR_MASK)\
	|((data & DMA_TDRLR4_TDRL_MASK)<<0));\
	DMA_TDRLR4_WR(v);\
} while (0)

#define DMA_TDRLR4_TDRL_RD(data) do {\
	DMA_TDRLR4_RD(data);\
	data = ((data >> 0) & DMA_TDRLR4_TDRL_MASK);\
} while (0)

#define DMA_TDRLR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12ac))

#define DMA_TDRLR3_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR3_OFFSET);\
} while (0)

#define DMA_TDRLR3_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR3_OFFSET);\
} while (0)


#define  DMA_TDRLR3_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR3_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR3_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR3_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR3_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR3_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR3_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR3_TDRL_WR_MASK)\
	|((data & DMA_TDRLR3_TDRL_MASK)<<0));\
	DMA_TDRLR3_WR(v);\
} while (0)

#define DMA_TDRLR3_TDRL_RD(data) do {\
	DMA_TDRLR3_RD(data);\
	data = ((data >> 0) & DMA_TDRLR3_TDRL_MASK);\
} while (0)

#define DMA_TDRLR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x122c))

#define DMA_TDRLR2_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR2_OFFSET);\
} while (0)

#define DMA_TDRLR2_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR2_OFFSET);\
} while (0)


#define  DMA_TDRLR2_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR2_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR2_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR2_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR2_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR2_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR2_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR2_TDRL_WR_MASK)\
	|((data & DMA_TDRLR2_TDRL_MASK)<<0));\
	DMA_TDRLR2_WR(v);\
} while (0)

#define DMA_TDRLR2_TDRL_RD(data) do {\
	DMA_TDRLR2_RD(data);\
	data = ((data >> 0) & DMA_TDRLR2_TDRL_MASK);\
} while (0)

#define DMA_TDRLR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11ac))

#define DMA_TDRLR1_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR1_OFFSET);\
} while (0)

#define DMA_TDRLR1_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR1_OFFSET);\
} while (0)


#define  DMA_TDRLR1_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR1_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR1_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR1_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR1_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR1_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR1_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR1_TDRL_WR_MASK)\
	|((data & DMA_TDRLR1_TDRL_MASK)<<0));\
	DMA_TDRLR1_WR(v);\
} while (0)

#define DMA_TDRLR1_TDRL_RD(data) do {\
	DMA_TDRLR1_RD(data);\
	data = ((data >> 0) & DMA_TDRLR1_TDRL_MASK);\
} while (0)

#define DMA_TDRLR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x112c))

#define DMA_TDRLR0_WR(data) do {\
	iowrite32(data, (void *)DMA_TDRLR0_OFFSET);\
} while (0)

#define DMA_TDRLR0_RD(data) do {\
	(data) = ioread32((void *)DMA_TDRLR0_OFFSET);\
} while (0)


#define  DMA_TDRLR0_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR0_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR0_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR0_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR0_TDRL_WR(data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR0_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR0_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR0_TDRL_WR_MASK)\
	|((data & DMA_TDRLR0_TDRL_MASK)<<0));\
	DMA_TDRLR0_WR(v);\
} while (0)

#define DMA_TDRLR0_TDRL_RD(data) do {\
	DMA_TDRLR0_RD(data);\
	data = ((data >> 0) & DMA_TDRLR0_TDRL_MASK);\
} while (0)

#define DMA_RDTP_RPDR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14a8))

#define DMA_RDTP_RPDR7_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR7_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR7_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR7_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR7_RDT_WR(data) do {\
	DMA_RDTP_RPDR7_WR(data);\
} while (0)

#define DMA_RDTP_RPDR7_RDT_RD(data) do {\
	DMA_RDTP_RPDR7_RD(data);\
} while (0)

#define DMA_RDTP_RPDR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1428))

#define DMA_RDTP_RPDR6_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR6_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR6_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR6_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR6_RDT_WR(data) do {\
	DMA_RDTP_RPDR6_WR(data);\
} while (0)

#define DMA_RDTP_RPDR6_RDT_RD(data) do {\
	DMA_RDTP_RPDR6_RD(data);\
} while (0)

#define DMA_RDTP_RPDR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13a8))

#define DMA_RDTP_RPDR5_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR5_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR5_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR5_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR5_RDT_WR(data) do {\
	DMA_RDTP_RPDR5_WR(data);\
} while (0)

#define DMA_RDTP_RPDR5_RDT_RD(data) do {\
	DMA_RDTP_RPDR5_RD(data);\
} while (0)

#define DMA_RDTP_RPDR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1328))

#define DMA_RDTP_RPDR4_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR4_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR4_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR4_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR4_RDT_WR(data) do {\
	DMA_RDTP_RPDR4_WR(data);\
} while (0)

#define DMA_RDTP_RPDR4_RDT_RD(data) do {\
	DMA_RDTP_RPDR4_RD(data);\
} while (0)

#define DMA_RDTP_RPDR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12a8))

#define DMA_RDTP_RPDR3_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR3_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR3_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR3_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR3_RDT_WR(data) do {\
	DMA_RDTP_RPDR3_WR(data);\
} while (0)

#define DMA_RDTP_RPDR3_RDT_RD(data) do {\
	DMA_RDTP_RPDR3_RD(data);\
} while (0)

#define DMA_RDTP_RPDR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1228))

#define DMA_RDTP_RPDR2_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR2_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR2_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR2_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR2_RDT_WR(data) do {\
	DMA_RDTP_RPDR2_WR(data);\
} while (0)

#define DMA_RDTP_RPDR2_RDT_RD(data) do {\
	DMA_RDTP_RPDR2_RD(data);\
} while (0)

#define DMA_RDTP_RPDR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11a8))

#define DMA_RDTP_RPDR1_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR1_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR1_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR1_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR1_RDT_WR(data) do {\
	DMA_RDTP_RPDR1_WR(data);\
} while (0)

#define DMA_RDTP_RPDR1_RDT_RD(data) do {\
	DMA_RDTP_RPDR1_RD(data);\
} while (0)

#define DMA_RDTP_RPDR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1128))

#define DMA_RDTP_RPDR0_WR(data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR0_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR0_RD(data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR0_OFFSET);\
} while (0)

#define DMA_RDTP_RPDR0_RDT_WR(data) do {\
	DMA_RDTP_RPDR0_WR(data);\
} while (0)

#define DMA_RDTP_RPDR0_RDT_RD(data) do {\
	DMA_RDTP_RPDR0_RD(data);\
} while (0)

#define DMA_TDTP_TPDR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14a0))

#define DMA_TDTP_TPDR7_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR7_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR7_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR7_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR7_TDT_WR(data) do {\
	DMA_TDTP_TPDR7_WR(data);\
} while (0)

#define DMA_TDTP_TPDR7_TDT_RD(data) do {\
	DMA_TDTP_TPDR7_RD(data);\
} while (0)

#define DMA_TDTP_TPDR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1420))

#define DMA_TDTP_TPDR6_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR6_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR6_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR6_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR6_TDT_WR(data) do {\
	DMA_TDTP_TPDR6_WR(data);\
} while (0)

#define DMA_TDTP_TPDR6_TDT_RD(data) do {\
	DMA_TDTP_TPDR6_RD(data);\
} while (0)

#define DMA_TDTP_TPDR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13a0))

#define DMA_TDTP_TPDR5_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR5_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR5_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR5_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR5_TDT_WR(data) do {\
	DMA_TDTP_TPDR5_WR(data);\
} while (0)

#define DMA_TDTP_TPDR5_TDT_RD(data) do {\
	DMA_TDTP_TPDR5_RD(data);\
} while (0)

#define DMA_TDTP_TPDR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1320))

#define DMA_TDTP_TPDR4_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR4_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR4_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR4_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR4_TDT_WR(data) do {\
	DMA_TDTP_TPDR4_WR(data);\
} while (0)

#define DMA_TDTP_TPDR4_TDT_RD(data) do {\
	DMA_TDTP_TPDR4_RD(data);\
} while (0)

#define DMA_TDTP_TPDR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12a0))

#define DMA_TDTP_TPDR3_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR3_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR3_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR3_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR3_TDT_WR(data) do {\
	DMA_TDTP_TPDR3_WR(data);\
} while (0)

#define DMA_TDTP_TPDR3_TDT_RD(data) do {\
	DMA_TDTP_TPDR3_RD(data);\
} while (0)

#define DMA_TDTP_TPDR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1220))

#define DMA_TDTP_TPDR2_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR2_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR2_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR2_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR2_TDT_WR(data) do {\
	DMA_TDTP_TPDR2_WR(data);\
} while (0)

#define DMA_TDTP_TPDR2_TDT_RD(data) do {\
	DMA_TDTP_TPDR2_RD(data);\
} while (0)

#define DMA_TDTP_TPDR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11a0))

#define DMA_TDTP_TPDR1_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR1_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR1_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR1_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR1_TDT_WR(data) do {\
	DMA_TDTP_TPDR1_WR(data);\
} while (0)

#define DMA_TDTP_TPDR1_TDT_RD(data) do {\
	DMA_TDTP_TPDR1_RD(data);\
} while (0)

#define DMA_TDTP_TPDR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1120))

#define DMA_TDTP_TPDR0_WR(data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR0_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR0_RD(data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR0_OFFSET);\
} while (0)

#define DMA_TDTP_TPDR0_TDT_WR(data) do {\
	DMA_TDTP_TPDR0_WR(data);\
} while (0)

#define DMA_TDTP_TPDR0_TDT_RD(data) do {\
	DMA_TDTP_TPDR0_RD(data);\
} while (0)

#define DMA_RDLAR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x149c))

#define DMA_RDLAR7_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR7_OFFSET);\
} while (0)

#define DMA_RDLAR7_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR7_OFFSET);\
} while (0)

#define DMA_RDLAR7_RDESLA_WR(data) do {\
	DMA_RDLAR7_WR(data);\
} while (0)

#define DMA_RDLAR7_RDESLA_RD(data) do {\
	DMA_RDLAR7_RD(data);\
} while (0)

#define DMA_RDLAR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x141c))

#define DMA_RDLAR6_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR6_OFFSET);\
} while (0)

#define DMA_RDLAR6_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR6_OFFSET);\
} while (0)

#define DMA_RDLAR6_RDESLA_WR(data) do {\
	DMA_RDLAR6_WR(data);\
} while (0)

#define DMA_RDLAR6_RDESLA_RD(data) do {\
	DMA_RDLAR6_RD(data);\
} while (0)

#define DMA_RDLAR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x139c))

#define DMA_RDLAR5_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR5_OFFSET);\
} while (0)

#define DMA_RDLAR5_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR5_OFFSET);\
} while (0)

#define DMA_RDLAR5_RDESLA_WR(data) do {\
	DMA_RDLAR5_WR(data);\
} while (0)

#define DMA_RDLAR5_RDESLA_RD(data) do {\
	DMA_RDLAR5_RD(data);\
} while (0)

#define DMA_RDLAR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x131c))

#define DMA_RDLAR4_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR4_OFFSET);\
} while (0)

#define DMA_RDLAR4_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR4_OFFSET);\
} while (0)

#define DMA_RDLAR4_RDESLA_WR(data) do {\
	DMA_RDLAR4_WR(data);\
} while (0)

#define DMA_RDLAR4_RDESLA_RD(data) do {\
	DMA_RDLAR4_RD(data);\
} while (0)

#define DMA_RDLAR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x129c))

#define DMA_RDLAR3_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR3_OFFSET);\
} while (0)

#define DMA_RDLAR3_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR3_OFFSET);\
} while (0)

#define DMA_RDLAR3_RDESLA_WR(data) do {\
	DMA_RDLAR3_WR(data);\
} while (0)

#define DMA_RDLAR3_RDESLA_RD(data) do {\
	DMA_RDLAR3_RD(data);\
} while (0)

#define DMA_RDLAR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x121c))

#define DMA_RDLAR2_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR2_OFFSET);\
} while (0)

#define DMA_RDLAR2_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR2_OFFSET);\
} while (0)

#define DMA_RDLAR2_RDESLA_WR(data) do {\
	DMA_RDLAR2_WR(data);\
} while (0)

#define DMA_RDLAR2_RDESLA_RD(data) do {\
	DMA_RDLAR2_RD(data);\
} while (0)

#define DMA_RDLAR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x119c))

#define DMA_RDLAR1_WR(data) do {\
	iowrite32(data, (void *)DMA_RDLAR1_OFFSET);\
} while (0)

#define DMA_RDLAR1_RD(data) do {\
	(data) = ioread32((void *)DMA_RDLAR1_OFFSET);\
} while (0)

#define DMA_RDLAR1_RDESLA_WR(data) do {\
	DMA_RDLAR1_WR(data);\
} while (0)

#define DMA_RDLAR1_RDESLA_RD(data) do {\
	DMA_RDLAR1_RD(data);\
} while (0)

#define DMA_RDLARH0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1118))

#define DMA_RDLAR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x111c))

#define DMA_RDLAR0_WR(data) do {\
	iowrite32((((data) >> 32) & 0xFF), (void *)DMA_RDLARH0_OFFSET);\
	iowrite32(data, (void *)DMA_RDLAR0_OFFSET);\
} while (0)

#define DMA_RDLARH0_RD(data) do {\
	data = ioread32((void *)DMA_RDLARH0_OFFSET);\
} while (0)

#define DMA_RDLARL0_RD(data) do {\
	data = ioread32((void *)DMA_RDLAR0_OFFSET);\
} while (0)

#define DMA_RDLAR0_RD(data) do {\
	uint64_t rd_low;\
	uint64_t rd_hi;\
	DMA_RDLARH0_RD(rd_hi);\
	DMA_RDLARL0_RD(rd_low);\
	data = (rd_hi << 32) | rd_low;\
} while (0)

#define DMA_RDLAR0_RDESLA_WR(data) do {\
	DMA_RDLAR0_WR(data);\
} while (0)

#define DMA_RDLAR0_RDESLA_RD(data) do {\
	DMA_RDLAR0_RD(data);\
} while (0)

#define DMA_TDLAR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1494))

#define DMA_TDLAR7_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR7_OFFSET);\
} while (0)

#define DMA_TDLAR7_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR7_OFFSET);\
} while (0)

#define DMA_TDLAR7_TDESLA_WR(data) do {\
	DMA_TDLAR7_WR(data);\
} while (0)

#define DMA_TDLAR7_TDESLA_RD(data) do {\
	DMA_TDLAR7_RD(data);\
} while (0)

#define DMA_TDLAR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1414))

#define DMA_TDLAR6_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR6_OFFSET);\
} while (0)

#define DMA_TDLAR6_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR6_OFFSET);\
} while (0)

#define DMA_TDLAR6_TDESLA_WR(data) do {\
	DMA_TDLAR6_WR(data);\
} while (0)

#define DMA_TDLAR6_TDESLA_RD(data) do {\
	DMA_TDLAR6_RD(data);\
} while (0)

#define DMA_TDLAR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1394))

#define DMA_TDLAR5_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR5_OFFSET);\
} while (0)

#define DMA_TDLAR5_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR5_OFFSET);\
} while (0)

#define DMA_TDLAR5_TDESLA_WR(data) do {\
	DMA_TDLAR5_WR(data);\
} while (0)

#define DMA_TDLAR5_TDESLA_RD(data) do {\
	DMA_TDLAR5_RD(data);\
} while (0)

#define DMA_TDLAR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1314))

#define DMA_TDLAR4_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR4_OFFSET);\
} while (0)

#define DMA_TDLAR4_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR4_OFFSET);\
} while (0)

#define DMA_TDLAR4_TDESLA_WR(data) do {\
	DMA_TDLAR4_WR(data);\
} while (0)

#define DMA_TDLAR4_TDESLA_RD(data) do {\
	DMA_TDLAR4_RD(data);\
} while (0)

#define DMA_TDLAR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1294))

#define DMA_TDLAR3_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR3_OFFSET);\
} while (0)

#define DMA_TDLAR3_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR3_OFFSET);\
} while (0)

#define DMA_TDLAR3_TDESLA_WR(data) do {\
	DMA_TDLAR3_WR(data);\
} while (0)

#define DMA_TDLAR3_TDESLA_RD(data) do {\
	DMA_TDLAR3_RD(data);\
} while (0)

#define DMA_TDLAR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1214))

#define DMA_TDLAR2_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR2_OFFSET);\
} while (0)

#define DMA_TDLAR2_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR2_OFFSET);\
} while (0)

#define DMA_TDLAR2_TDESLA_WR(data) do {\
	DMA_TDLAR2_WR(data);\
} while (0)

#define DMA_TDLAR2_TDESLA_RD(data) do {\
	DMA_TDLAR2_RD(data);\
} while (0)

#define DMA_TDLAR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1194))

#define DMA_TDLAR1_WR(data) do {\
	iowrite32(data, (void *)DMA_TDLAR1_OFFSET);\
} while (0)

#define DMA_TDLAR1_RD(data) do {\
	(data) = ioread32((void *)DMA_TDLAR1_OFFSET);\
} while (0)

#define DMA_TDLAR1_TDESLA_WR(data) do {\
	DMA_TDLAR1_WR(data);\
} while (0)

#define DMA_TDLAR1_TDESLA_RD(data) do {\
	DMA_TDLAR1_RD(data);\
} while (0)

#define DMA_TDLARH0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1110))

#define DMA_TDLAR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1114))

#define DMA_TDLAR0_WR(data) do {\
	iowrite32((((data)>>32)&0xFF), (void *) DMA_TDLARH0_OFFSET);\
	iowrite32(data, (void *)DMA_TDLAR0_OFFSET);\
} while (0)

#define DMA_TDLAR0_RD(data) do {\
	uint64_t rd_hi = ioread32((void *)DMA_TDLARH0_OFFSET);\
	uint64_t rd_low = ioread32((void *)DMA_TDLAR0_OFFSET);\
	data = (rd_hi << 32) | rd_low;\
} while (0)

#define DMA_TDLAR0_TDESLA_WR(data) do {\
	DMA_TDLAR0_WR(data);\
} while (0)

#define DMA_TDLAR0_TDESLA_RD(data) do {\
	DMA_TDLAR0_RD(data);\
} while (0)

#define MAC_IMR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb4))

#define MAC_IMR_WR(data) do {\
	iowrite32(data, (void *)MAC_IMR_OFFSET);\
} while (0)

#define MAC_IMR_RD(data) do {\
	(data) = ioread32((void *)MAC_IMR_OFFSET);\
} while (0)


#define  MAC_IMR_MASK_13 (ULONG)(0x7ffff)


#define MAC_IMR_RES_WR_MASK_13 (ULONG)(0x1fff)


#define  MAC_IMR_MASK_6 (ULONG)(0x3f)


#define MAC_IMR_RES_WR_MASK_6 (ULONG)(0xfffff03f)


#define MAC_IMR_TSIM_MASK (ULONG)(0x1)


#define MAC_IMR_TSIM_WR_MASK (ULONG)(0xffffefff)

#define MAC_IMR_TSIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_TSIM_WR_MASK)\
	|((data & MAC_IMR_TSIM_MASK)<<12));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_TSIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 12) & MAC_IMR_TSIM_MASK);\
} while (0)


#define MAC_IMR_LPIIM_MASK (ULONG)(0x1)


#define MAC_IMR_LPIIM_WR_MASK (ULONG)(0xffffffdf)

#define MAC_IMR_LPIIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_LPIIM_WR_MASK)\
	|((data & MAC_IMR_LPIIM_MASK)<<5));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_LPIIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 5) & MAC_IMR_LPIIM_MASK);\
} while (0)


#define MAC_IMR_PMTIM_MASK (ULONG)(0x1)


#define MAC_IMR_PMTIM_WR_MASK (ULONG)(0xffffffef)

#define MAC_IMR_PMTIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_PMTIM_WR_MASK)\
	|((data & MAC_IMR_PMTIM_MASK)<<4));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_PMTIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 4) & MAC_IMR_PMTIM_MASK);\
} while (0)


#define MAC_IMR_PHYIM_MASK (ULONG)(0x1)


#define MAC_IMR_PHYIM_WR_MASK (ULONG)(0xfffffff7)

#define MAC_IMR_PHYIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_PHYIM_WR_MASK)\
	|((data & MAC_IMR_PHYIM_MASK)<<3));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_PHYIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 3) & MAC_IMR_PHYIM_MASK);\
} while (0)


#define MAC_IMR_PCSANCIM_MASK (ULONG)(0x1)


#define MAC_IMR_PCSANCIM_WR_MASK (ULONG)(0xfffffffb)

#define MAC_IMR_PCSANCIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_PCSANCIM_WR_MASK)\
	|((data & MAC_IMR_PCSANCIM_MASK)<<2));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_PCSANCIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 2) & MAC_IMR_PCSANCIM_MASK);\
} while (0)


#define MAC_IMR_PCSLCHGIM_MASK (ULONG)(0x1)


#define MAC_IMR_PCSLCHGIM_WR_MASK (ULONG)(0xfffffffd)

#define MAC_IMR_PCSLCHGIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_PCSLCHGIM_WR_MASK)\
	|((data & MAC_IMR_PCSLCHGIM_MASK)<<1));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_PCSLCHGIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 1) & MAC_IMR_PCSLCHGIM_MASK);\
} while (0)


#define MAC_IMR_RGSMIIIM_MASK (ULONG)(0x1)


#define MAC_IMR_RGSMIIIM_WR_MASK (ULONG)(0xfffffffe)

#define MAC_IMR_RGSMIIIM_WR(data) do {\
	ULONG v;\
	MAC_IMR_RD(v);\
	v = (v & (MAC_IMR_RES_WR_MASK_13))\
	|(((0) & (MAC_IMR_MASK_13))<<13);\
	v = (v & (MAC_IMR_RES_WR_MASK_6))\
	|(((0) & (MAC_IMR_MASK_6))<<6);\
	v = ((v & MAC_IMR_RGSMIIIM_WR_MASK)\
	|((data & MAC_IMR_RGSMIIIM_MASK)<<0));\
	MAC_IMR_WR(v);\
} while (0)

#define MAC_IMR_RGSMIIIM_RD(data) do {\
	MAC_IMR_RD(data);\
	data = ((data >> 0) & MAC_IMR_RGSMIIIM_MASK);\
} while (0)

#define MAC_ISR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xb0))

#define MAC_ISR_RD(data) do {\
	(data) = ioread32((void *)MAC_ISR_OFFSET);\
} while (0)


#define MAC_ISR_RWT_MASK (ULONG)(0x1)

#define MAC_ISR_RWT_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 14) & MAC_ISR_RWT_MASK);\
} while (0)


#define MAC_ISR_TJT_MASK (ULONG)(0x1)

#define MAC_ISR_TJT_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 13) & MAC_ISR_TJT_MASK);\
} while (0)


#define MAC_ISR_TSIS_MASK (ULONG)(0x1)

#define MAC_ISR_TSIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 12) & MAC_ISR_TSIS_MASK);\
} while (0)


#define MAC_ISR_MMCRXIPIS_MASK (ULONG)(0x1)

#define MAC_ISR_MMCRXIPIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 11) & MAC_ISR_MMCRXIPIS_MASK);\
} while (0)


#define MAC_ISR_MMCTXIS_MASK (ULONG)(0x1)

#define MAC_ISR_MMCTXIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 10) & MAC_ISR_MMCTXIS_MASK);\
} while (0)


#define MAC_ISR_MMCRXIS_MASK (ULONG)(0x1)

#define MAC_ISR_MMCRXIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 9) & MAC_ISR_MMCRXIS_MASK);\
} while (0)


#define MAC_ISR_MMCIS_MASK (ULONG)(0x1)

#define MAC_ISR_MMCIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 8) & MAC_ISR_MMCIS_MASK);\
} while (0)


#define MAC_ISR_LPIIS_MASK (ULONG)(0x1)

#define MAC_ISR_LPIIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 5) & MAC_ISR_LPIIS_MASK);\
} while (0)


#define MAC_ISR_PMTIS_MASK (ULONG)(0x1)

#define MAC_ISR_PMTIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 4) & MAC_ISR_PMTIS_MASK);\
} while (0)


#define MAC_ISR_PHYIS_MASK (ULONG)(0x1)

#define MAC_ISR_PHYIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 3) & MAC_ISR_PHYIS_MASK);\
} while (0)


#define MAC_ISR_PCSANCIA_MASK (ULONG)(0x1)

#define MAC_ISR_PCSANCIA_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 2) & MAC_ISR_PCSANCIA_MASK);\
} while (0)


#define MAC_ISR_PCSLCHGIS_MASK (ULONG)(0x1)

#define MAC_ISR_PCSLCHGIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 1) & MAC_ISR_PCSLCHGIS_MASK);\
} while (0)


#define MAC_ISR_RGSMIIIS_MASK (ULONG)(0x1)

#define MAC_ISR_RGSMIIIS_RD(data) do {\
	MAC_ISR_RD(data);\
	data = ((data >> 0) & MAC_ISR_RGSMIIIS_MASK);\
} while (0)

#define MTL_ISR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc20))

#define MTL_ISR_RD(data) do {\
	(data) = ioread32((void *)MTL_ISR_OFFSET);\
} while (0)


#define MTL_ISR_MACIS_MASK (ULONG)(0x1)

#define MTL_ISR_MACIS_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 16) & MTL_ISR_MACIS_MASK);\
} while (0)


#define MTL_ISR_Q7RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q7RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 15) & MTL_ISR_Q7RXO_MASK);\
} while (0)


#define MTL_ISR_Q7TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q7TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 14) & MTL_ISR_Q7TXU_MASK);\
} while (0)


#define MTL_ISR_Q6RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q6RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 13) & MTL_ISR_Q6RXO_MASK);\
} while (0)


#define MTL_ISR_Q6TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q6TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 12) & MTL_ISR_Q6TXU_MASK);\
} while (0)


#define MTL_ISR_Q5RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q5RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 11) & MTL_ISR_Q5RXO_MASK);\
} while (0)


#define MTL_ISR_Q5TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q5TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 10) & MTL_ISR_Q5TXU_MASK);\
} while (0)


#define MTL_ISR_Q4RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q4RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 9) & MTL_ISR_Q4RXO_MASK);\
} while (0)


#define MTL_ISR_Q4TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q4TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 8) & MTL_ISR_Q4TXU_MASK);\
} while (0)


#define MTL_ISR_Q3RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q3RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 7) & MTL_ISR_Q3RXO_MASK);\
} while (0)


#define MTL_ISR_Q3TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q3TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 6) & MTL_ISR_Q3TXU_MASK);\
} while (0)


#define MTL_ISR_Q2RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q2RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 5) & MTL_ISR_Q2RXO_MASK);\
} while (0)


#define MTL_ISR_Q2TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q2TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 4) & MTL_ISR_Q2TXU_MASK);\
} while (0)


#define MTL_ISR_Q1RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q1RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 3) & MTL_ISR_Q1RXO_MASK);\
} while (0)


#define MTL_ISR_Q1TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q1TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 2) & MTL_ISR_Q1TXU_MASK);\
} while (0)


#define MTL_ISR_Q0RXO_MASK (ULONG)(0x1)

#define MTL_ISR_Q0RXO_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 1) & MTL_ISR_Q0RXO_MASK);\
} while (0)


#define MTL_ISR_Q0TXU_MASK (ULONG)(0x1)

#define MTL_ISR_Q0TXU_RD(data) do {\
	MTL_ISR_RD(data);\
	data = ((data >> 0) & MTL_ISR_Q0TXU_MASK);\
} while (0)

#define DMA_ISR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1008))

#define DMA_ISR_RD(data) do {\
	(data) = ioread32((void *)DMA_ISR_OFFSET);\
} while (0)


#define DMA_ISR_MACIS_MASK (ULONG)(0x1)

#define DMA_ISR_MACIS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 17) & DMA_ISR_MACIS_MASK);\
} while (0)


#define DMA_ISR_MTLIS_MASK (ULONG)(0x1)

#define DMA_ISR_MTLIS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 16) & DMA_ISR_MTLIS_MASK);\
} while (0)


#define DMA_ISR_DC7IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC7IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 7) & DMA_ISR_DC7IS_MASK);\
} while (0)


#define DMA_ISR_DC6IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC6IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 6) & DMA_ISR_DC6IS_MASK);\
} while (0)


#define DMA_ISR_DC5IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC5IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 5) & DMA_ISR_DC5IS_MASK);\
} while (0)


#define DMA_ISR_DC4IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC4IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 4) & DMA_ISR_DC4IS_MASK);\
} while (0)


#define DMA_ISR_DC3IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC3IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 3) & DMA_ISR_DC3IS_MASK);\
} while (0)


#define DMA_ISR_DC2IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC2IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 2) & DMA_ISR_DC2IS_MASK);\
} while (0)


#define DMA_ISR_DC1IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC1IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 1) & DMA_ISR_DC1IS_MASK);\
} while (0)


#define DMA_ISR_DC0IS_MASK (ULONG)(0x1)

#define DMA_ISR_DC0IS_RD(data) do {\
	DMA_ISR_RD(data);\
	data = ((data >> 0) & DMA_ISR_DC0IS_MASK);\
} while (0)

#define DMA_DSR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1014))

#define DMA_DSR2_RD(data) do {\
	(data) = ioread32((void *)DMA_DSR2_OFFSET);\
} while (0)


#define DMA_DSR2_TPS7_MASK (ULONG)(0xf)

#define DMA_DSR2_TPS7_RD(data) do {\
	DMA_DSR2_RD(data);\
	data = ((data >> 4) & DMA_DSR2_TPS7_MASK);\
} while (0)


#define DMA_DSR2_RPS7_MASK (ULONG)(0xf)

#define DMA_DSR2_RPS7_RD(data) do {\
	DMA_DSR2_RD(data);\
	data = ((data >> 0) & DMA_DSR2_RPS7_MASK);\
} while (0)

#define DMA_DSR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1010))

#define DMA_DSR1_RD(data) do {\
	(data) = ioread32((void *)DMA_DSR1_OFFSET);\
} while (0)


#define DMA_DSR1_TPS6_MASK (ULONG)(0xf)

#define DMA_DSR1_TPS6_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 28) & DMA_DSR1_TPS6_MASK);\
} while (0)


#define DMA_DSR1_RPS6_MASK (ULONG)(0xf)

#define DMA_DSR1_RPS6_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 24) & DMA_DSR1_RPS6_MASK);\
} while (0)


#define DMA_DSR1_TPS5_MASK (ULONG)(0xf)

#define DMA_DSR1_TPS5_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 20) & DMA_DSR1_TPS5_MASK);\
} while (0)


#define DMA_DSR1_RPS5_MASK (ULONG)(0xf)

#define DMA_DSR1_RPS5_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 16) & DMA_DSR1_RPS5_MASK);\
} while (0)


#define DMA_DSR1_TPS4_MASK (ULONG)(0xf)

#define DMA_DSR1_TPS4_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 12) & DMA_DSR1_TPS4_MASK);\
} while (0)


#define DMA_DSR1_RPS4_MASK (ULONG)(0xf)

#define DMA_DSR1_RPS4_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 8) & DMA_DSR1_RPS4_MASK);\
} while (0)


#define DMA_DSR1_TPS3_MASK (ULONG)(0xf)

#define DMA_DSR1_TPS3_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 4) & DMA_DSR1_TPS3_MASK);\
} while (0)


#define DMA_DSR1_RPS3_MASK (ULONG)(0xf)

#define DMA_DSR1_RPS3_RD(data) do {\
	DMA_DSR1_RD(data);\
	data = ((data >> 0) & DMA_DSR1_RPS3_MASK);\
} while (0)

#define DMA_DSR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x100c))

#define DMA_DSR0_RD(data) do {\
	(data) = ioread32((void *)DMA_DSR0_OFFSET);\
} while (0)


#define DMA_DSR0_TPS2_MASK (ULONG)(0xf)

#define DMA_DSR0_TPS2_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 28) & DMA_DSR0_TPS2_MASK);\
} while (0)


#define DMA_DSR0_RPS2_MASK (ULONG)(0xf)

#define DMA_DSR0_RPS2_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 24) & DMA_DSR0_RPS2_MASK);\
} while (0)


#define DMA_DSR0_TPS1_MASK (ULONG)(0xf)

#define DMA_DSR0_TPS1_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 20) & DMA_DSR0_TPS1_MASK);\
} while (0)


#define DMA_DSR0_RPS1_MASK (ULONG)(0xf)

#define DMA_DSR0_RPS1_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 16) & DMA_DSR0_RPS1_MASK);\
} while (0)


#define DMA_DSR0_TPS0_MASK (ULONG)(0xf)

#define DMA_DSR0_TPS0_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 12) & DMA_DSR0_TPS0_MASK);\
} while (0)


#define DMA_DSR0_RPS0_MASK (ULONG)(0xf)

#define DMA_DSR0_RPS0_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 8) & DMA_DSR0_RPS0_MASK);\
} while (0)


#define DMA_DSR0_AXRHSTS_MASK (ULONG)(0x1)

#define DMA_DSR0_AXRHSTS_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 1) & DMA_DSR0_AXRHSTS_MASK);\
} while (0)


#define DMA_DSR0_AXWHSTS_MASK (ULONG)(0x1)

#define DMA_DSR0_AXWHSTS_RD(data) do {\
	DMA_DSR0_RD(data);\
	data = ((data >> 0) & DMA_DSR0_AXWHSTS_MASK);\
} while (0)

#define MTL_Q0RDR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd38))

#define MTL_Q0RDR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0RDR_OFFSET);\
} while (0)


#define MTL_Q0RDR_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_Q0RDR_PRXQ_RD(data) do {\
	MTL_Q0RDR_RD(data);\
	data = ((data >> 16) & MTL_Q0RDR_PRXQ_MASK);\
} while (0)


#define MTL_Q0RDR_RXQSTS_MASK (ULONG)(0x3)

#define MTL_Q0RDR_RXQSTS_RD(data) do {\
	MTL_Q0RDR_RD(data);\
	data = ((data >> 4) & MTL_Q0RDR_RXQSTS_MASK);\
} while (0)


#define MTL_Q0RDR_RRCSTS_MASK (ULONG)(0x3)

#define MTL_Q0RDR_RRCSTS_RD(data) do {\
	MTL_Q0RDR_RD(data);\
	data = ((data >> 1) & MTL_Q0RDR_RRCSTS_MASK);\
} while (0)


#define MTL_Q0RDR_RWCSTS_MASK (ULONG)(0x1)

#define MTL_Q0RDR_RWCSTS_RD(data) do {\
	MTL_Q0RDR_RD(data);\
	data = ((data >> 0) & MTL_Q0RDR_RWCSTS_MASK);\
} while (0)

#define MTL_Q0ESR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd14))

#define MTL_Q0ESR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0ESR_OFFSET);\
} while (0)


#define MTL_Q0ESR_ABSU_MASK (ULONG)(0x1)

#define MTL_Q0ESR_ABSU_RD(data) do {\
	MTL_Q0ESR_RD(data);\
	data = ((data >> 24) & MTL_Q0ESR_ABSU_MASK);\
} while (0)


#define MTL_Q0ESR_ABS_MASK (ULONG)(0xffffff)

#define MTL_Q0ESR_ABS_RD(data) do {\
	MTL_Q0ESR_RD(data);\
	data = ((data >> 0) & MTL_Q0ESR_ABS_MASK);\
} while (0)

#define MTL_Q0TDR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd08))

#define MTL_Q0TDR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0TDR_OFFSET);\
} while (0)


#define MTL_Q0TDR_STXSTSF_MASK (ULONG)(0x7)

#define MTL_Q0TDR_STXSTSF_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 20) & MTL_Q0TDR_STXSTSF_MASK);\
} while (0)


#define MTL_Q0TDR_PTXQ_MASK (ULONG)(0x7)

#define MTL_Q0TDR_PTXQ_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 16) & MTL_Q0TDR_PTXQ_MASK);\
} while (0)


#define MTL_Q0TDR_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_Q0TDR_TXSTSFSTS_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 5) & MTL_Q0TDR_TXSTSFSTS_MASK);\
} while (0)


#define MTL_Q0TDR_TXQSTS_MASK (ULONG)(0x1)

#define MTL_Q0TDR_TXQSTS_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 4) & MTL_Q0TDR_TXQSTS_MASK);\
} while (0)


#define MTL_Q0TDR_TWCSTS_MASK (ULONG)(0x1)

#define MTL_Q0TDR_TWCSTS_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 3) & MTL_Q0TDR_TWCSTS_MASK);\
} while (0)


#define MTL_Q0TDR_TRCSTS_MASK (ULONG)(0x3)

#define MTL_Q0TDR_TRCSTS_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 1) & MTL_Q0TDR_TRCSTS_MASK);\
} while (0)


#define MTL_Q0TDR_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_Q0TDR_TXQPAUSED_RD(data) do {\
	MTL_Q0TDR_RD(data);\
	data = ((data >> 0) & MTL_Q0TDR_TXQPAUSED_MASK);\
} while (0)

#define DMA_CHRBAR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14dc))

#define DMA_CHRBAR7_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR7_OFFSET);\
} while (0)

#define DMA_CHRBAR7_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR7_RD(data);\
} while (0)

#define DMA_CHRBAR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x145c))

#define DMA_CHRBAR6_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR6_OFFSET);\
} while (0)

#define DMA_CHRBAR6_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR6_RD(data);\
} while (0)

#define DMA_CHRBAR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13dc))

#define DMA_CHRBAR5_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR5_OFFSET);\
} while (0)

#define DMA_CHRBAR5_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR5_RD(data);\
} while (0)

#define DMA_CHRBAR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x135c))

#define DMA_CHRBAR4_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR4_OFFSET);\
} while (0)

#define DMA_CHRBAR4_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR4_RD(data);\
} while (0)

#define DMA_CHRBAR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12dc))

#define DMA_CHRBAR3_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR3_OFFSET);\
} while (0)

#define DMA_CHRBAR3_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR3_RD(data);\
} while (0)

#define DMA_CHRBAR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x125c))

#define DMA_CHRBAR2_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR2_OFFSET);\
} while (0)

#define DMA_CHRBAR2_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR2_RD(data);\
} while (0)

#define DMA_CHRBAR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11dc))

#define DMA_CHRBAR1_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR1_OFFSET);\
} while (0)

#define DMA_CHRBAR1_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR1_RD(data);\
} while (0)

#define DMA_CHRBAR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x115c))

#define DMA_CHRBAR0_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRBAR0_OFFSET);\
} while (0)

#define DMA_CHRBAR0_CURRBUFAPTR_RD(data) do {\
	DMA_CHRBAR0_RD(data);\
} while (0)

#define DMA_CHTBAR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14d4))

#define DMA_CHTBAR7_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR7_OFFSET);\
} while (0)

#define DMA_CHTBAR7_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR7_RD(data);\
} while (0)

#define DMA_CHTBAR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1454))

#define DMA_CHTBAR6_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR6_OFFSET);\
} while (0)

#define DMA_CHTBAR6_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR6_RD(data);\
} while (0)

#define DMA_CHTBAR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13d4))

#define DMA_CHTBAR5_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR5_OFFSET);\
} while (0)

#define DMA_CHTBAR5_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR5_RD(data);\
} while (0)

#define DMA_CHTBAR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1354))

#define DMA_CHTBAR4_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR4_OFFSET);\
} while (0)

#define DMA_CHTBAR4_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR4_RD(data);\
} while (0)

#define DMA_CHTBAR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12d4))

#define DMA_CHTBAR3_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR3_OFFSET);\
} while (0)

#define DMA_CHTBAR3_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR3_RD(data);\
} while (0)

#define DMA_CHTBAR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1254))

#define DMA_CHTBAR2_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR2_OFFSET);\
} while (0)

#define DMA_CHTBAR2_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR2_RD(data);\
} while (0)

#define DMA_CHTBAR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11d4))

#define DMA_CHTBAR1_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR1_OFFSET);\
} while (0)

#define DMA_CHTBAR1_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR1_RD(data);\
} while (0)

#define DMA_CHTBAR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1154))

#define DMA_CHTBAR0_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTBAR0_OFFSET);\
} while (0)

#define DMA_CHTBAR0_CURTBUFAPTR_RD(data) do {\
	DMA_CHTBAR0_RD(data);\
} while (0)

#define DMA_CHRDR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14cc))

#define DMA_CHRDR7_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR7_OFFSET);\
} while (0)

#define DMA_CHRDR7_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR7_RD(data);\
} while (0)

#define DMA_CHRDR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x144c))

#define DMA_CHRDR6_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR6_OFFSET);\
} while (0)

#define DMA_CHRDR6_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR6_RD(data);\
} while (0)

#define DMA_CHRDR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13cc))

#define DMA_CHRDR5_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR5_OFFSET);\
} while (0)

#define DMA_CHRDR5_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR5_RD(data);\
} while (0)

#define DMA_CHRDR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x134c))

#define DMA_CHRDR4_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR4_OFFSET);\
} while (0)

#define DMA_CHRDR4_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR4_RD(data);\
} while (0)

#define DMA_CHRDR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12cc))

#define DMA_CHRDR3_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR3_OFFSET);\
} while (0)

#define DMA_CHRDR3_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR3_RD(data);\
} while (0)

#define DMA_CHRDR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x124c))

#define DMA_CHRDR2_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR2_OFFSET);\
} while (0)

#define DMA_CHRDR2_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR2_RD(data);\
} while (0)

#define DMA_CHRDR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11cc))

#define DMA_CHRDR1_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR1_OFFSET);\
} while (0)

#define DMA_CHRDR1_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR1_RD(data);\
} while (0)

#define DMA_CHRDR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x114c))

#define DMA_CHRDR0_RD(data) do {\
	(data) = ioread32((void *)DMA_CHRDR0_OFFSET);\
} while (0)

#define DMA_CHRDR0_CURRDESAPTR_RD(data) do {\
	DMA_CHRDR0_RD(data);\
} while (0)

#define DMA_CHTDR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14c4))

#define DMA_CHTDR7_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR7_OFFSET);\
} while (0)

#define DMA_CHTDR7_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR7_RD(data);\
} while (0)

#define DMA_CHTDR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1444))

#define DMA_CHTDR6_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR6_OFFSET);\
} while (0)

#define DMA_CHTDR6_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR6_RD(data);\
} while (0)

#define DMA_CHTDR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13c4))

#define DMA_CHTDR5_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR5_OFFSET);\
} while (0)

#define DMA_CHTDR5_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR5_RD(data);\
} while (0)

#define DMA_CHTDR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1344))

#define DMA_CHTDR4_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR4_OFFSET);\
} while (0)

#define DMA_CHTDR4_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR4_RD(data);\
} while (0)

#define DMA_CHTDR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12c4))

#define DMA_CHTDR3_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR3_OFFSET);\
} while (0)

#define DMA_CHTDR3_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR3_RD(data);\
} while (0)

#define DMA_CHTDR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1244))

#define DMA_CHTDR2_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR2_OFFSET);\
} while (0)

#define DMA_CHTDR2_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR2_RD(data);\
} while (0)

#define DMA_CHTDR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11c4))

#define DMA_CHTDR1_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR1_OFFSET);\
} while (0)

#define DMA_CHTDR1_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR1_RD(data);\
} while (0)

#define DMA_CHTDR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1144))

#define DMA_CHTDR0_RD(data) do {\
	(data) = ioread32((void *)DMA_CHTDR0_OFFSET);\
} while (0)

#define DMA_CHTDR0_CURTDESAPTR_RD(data) do {\
	DMA_CHTDR0_RD(data);\
} while (0)

#define DMA_SFCSR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14bc))

#define DMA_SFCSR7_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR7_OFFSET);\
} while (0)

#define DMA_SFCSR7_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR7_OFFSET);\
} while (0)


#define  DMA_SFCSR7_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR7_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR7_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR7_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR7_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR7_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR7_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR7_RD(v);\
	v = (v & (DMA_SFCSR7_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR7_MASK_2))<<2);\
	v = (v & (DMA_SFCSR7_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR7_MASK_20))<<20);\
	v = ((v & DMA_SFCSR7_ESC_WR_MASK)\
	|((data & DMA_SFCSR7_ESC_MASK)<<0));\
	DMA_SFCSR7_WR(v);\
} while (0)

#define DMA_SFCSR7_ESC_RD(data) do {\
	DMA_SFCSR7_RD(data);\
	data = ((data >> 0) & DMA_SFCSR7_ESC_MASK);\
} while (0)


#define DMA_SFCSR7_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR7_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR7_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR7_RD(v);\
	v = (v & (DMA_SFCSR7_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR7_MASK_2))<<2);\
	v = (v & (DMA_SFCSR7_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR7_MASK_20))<<20);\
	v = ((v & DMA_SFCSR7_ASC_WR_MASK)\
	|((data & DMA_SFCSR7_ASC_MASK)<<1));\
	DMA_SFCSR7_WR(v);\
} while (0)

#define DMA_SFCSR7_ASC_RD(data) do {\
	DMA_SFCSR7_RD(data);\
	data = ((data >> 1) & DMA_SFCSR7_ASC_MASK);\
} while (0)


#define DMA_SFCSR7_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR7_RSN_RD(data) do {\
	DMA_SFCSR7_RD(data);\
	data = ((data >> 16) & DMA_SFCSR7_RSN_MASK);\
} while (0)

#define DMA_SFCSR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x143c))

#define DMA_SFCSR6_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR6_OFFSET);\
} while (0)

#define DMA_SFCSR6_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR6_OFFSET);\
} while (0)


#define  DMA_SFCSR6_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR6_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR6_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR6_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR6_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR6_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR6_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR6_RD(v);\
	v = (v & (DMA_SFCSR6_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR6_MASK_2))<<2);\
	v = (v & (DMA_SFCSR6_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR6_MASK_20))<<20);\
	v = ((v & DMA_SFCSR6_ESC_WR_MASK)\
	|((data & DMA_SFCSR6_ESC_MASK)<<0));\
	DMA_SFCSR6_WR(v);\
} while (0)

#define DMA_SFCSR6_ESC_RD(data) do {\
	DMA_SFCSR6_RD(data);\
	data = ((data >> 0) & DMA_SFCSR6_ESC_MASK);\
} while (0)


#define DMA_SFCSR6_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR6_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR6_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR6_RD(v);\
	v = (v & (DMA_SFCSR6_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR6_MASK_2))<<2);\
	v = (v & (DMA_SFCSR6_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR6_MASK_20))<<20);\
	v = ((v & DMA_SFCSR6_ASC_WR_MASK)\
	|((data & DMA_SFCSR6_ASC_MASK)<<1));\
	DMA_SFCSR6_WR(v);\
} while (0)

#define DMA_SFCSR6_ASC_RD(data) do {\
	DMA_SFCSR6_RD(data);\
	data = ((data >> 1) & DMA_SFCSR6_ASC_MASK);\
} while (0)


#define DMA_SFCSR6_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR6_RSN_RD(data) do {\
	DMA_SFCSR6_RD(data);\
	data = ((data >> 16) & DMA_SFCSR6_RSN_MASK);\
} while (0)

#define DMA_SFCSR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13bc))

#define DMA_SFCSR5_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR5_OFFSET);\
} while (0)

#define DMA_SFCSR5_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR5_OFFSET);\
} while (0)


#define  DMA_SFCSR5_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR5_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR5_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR5_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR5_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR5_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR5_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR5_RD(v);\
	v = (v & (DMA_SFCSR5_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR5_MASK_2))<<2);\
	v = (v & (DMA_SFCSR5_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR5_MASK_20))<<20);\
	v = ((v & DMA_SFCSR5_ESC_WR_MASK)\
	|((data & DMA_SFCSR5_ESC_MASK)<<0));\
	DMA_SFCSR5_WR(v);\
} while (0)

#define DMA_SFCSR5_ESC_RD(data) do {\
	DMA_SFCSR5_RD(data);\
	data = ((data >> 0) & DMA_SFCSR5_ESC_MASK);\
} while (0)


#define DMA_SFCSR5_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR5_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR5_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR5_RD(v);\
	v = (v & (DMA_SFCSR5_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR5_MASK_2))<<2);\
	v = (v & (DMA_SFCSR5_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR5_MASK_20))<<20);\
	v = ((v & DMA_SFCSR5_ASC_WR_MASK)\
	|((data & DMA_SFCSR5_ASC_MASK)<<1));\
	DMA_SFCSR5_WR(v);\
} while (0)

#define DMA_SFCSR5_ASC_RD(data) do {\
	DMA_SFCSR5_RD(data);\
	data = ((data >> 1) & DMA_SFCSR5_ASC_MASK);\
} while (0)


#define DMA_SFCSR5_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR5_RSN_RD(data) do {\
	DMA_SFCSR5_RD(data);\
	data = ((data >> 16) & DMA_SFCSR5_RSN_MASK);\
} while (0)

#define DMA_SFCSR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x133c))

#define DMA_SFCSR4_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR4_OFFSET);\
} while (0)

#define DMA_SFCSR4_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR4_OFFSET);\
} while (0)


#define  DMA_SFCSR4_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR4_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR4_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR4_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR4_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR4_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR4_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR4_RD(v);\
	v = (v & (DMA_SFCSR4_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR4_MASK_2))<<2);\
	v = (v & (DMA_SFCSR4_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR4_MASK_20))<<20);\
	v = ((v & DMA_SFCSR4_ESC_WR_MASK)\
	|((data & DMA_SFCSR4_ESC_MASK)<<0));\
	DMA_SFCSR4_WR(v);\
} while (0)

#define DMA_SFCSR4_ESC_RD(data) do {\
	DMA_SFCSR4_RD(data);\
	data = ((data >> 0) & DMA_SFCSR4_ESC_MASK);\
} while (0)


#define DMA_SFCSR4_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR4_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR4_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR4_RD(v);\
	v = (v & (DMA_SFCSR4_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR4_MASK_2))<<2);\
	v = (v & (DMA_SFCSR4_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR4_MASK_20))<<20);\
	v = ((v & DMA_SFCSR4_ASC_WR_MASK)\
	|((data & DMA_SFCSR4_ASC_MASK)<<1));\
	DMA_SFCSR4_WR(v);\
} while (0)

#define DMA_SFCSR4_ASC_RD(data) do {\
	DMA_SFCSR4_RD(data);\
	data = ((data >> 1) & DMA_SFCSR4_ASC_MASK);\
} while (0)


#define DMA_SFCSR4_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR4_RSN_RD(data) do {\
	DMA_SFCSR4_RD(data);\
	data = ((data >> 16) & DMA_SFCSR4_RSN_MASK);\
} while (0)

#define DMA_SFCSR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12bc))

#define DMA_SFCSR3_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR3_OFFSET);\
} while (0)

#define DMA_SFCSR3_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR3_OFFSET);\
} while (0)


#define  DMA_SFCSR3_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR3_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR3_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR3_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR3_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR3_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR3_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR3_RD(v);\
	v = (v & (DMA_SFCSR3_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR3_MASK_2))<<2);\
	v = (v & (DMA_SFCSR3_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR3_MASK_20))<<20);\
	v = ((v & DMA_SFCSR3_ESC_WR_MASK)\
	|((data & DMA_SFCSR3_ESC_MASK)<<0));\
	DMA_SFCSR3_WR(v);\
} while (0)

#define DMA_SFCSR3_ESC_RD(data) do {\
	DMA_SFCSR3_RD(data);\
	data = ((data >> 0) & DMA_SFCSR3_ESC_MASK);\
} while (0)


#define DMA_SFCSR3_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR3_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR3_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR3_RD(v);\
	v = (v & (DMA_SFCSR3_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR3_MASK_2))<<2);\
	v = (v & (DMA_SFCSR3_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR3_MASK_20))<<20);\
	v = ((v & DMA_SFCSR3_ASC_WR_MASK)\
	|((data & DMA_SFCSR3_ASC_MASK)<<1));\
	DMA_SFCSR3_WR(v);\
} while (0)

#define DMA_SFCSR3_ASC_RD(data) do {\
	DMA_SFCSR3_RD(data);\
	data = ((data >> 1) & DMA_SFCSR3_ASC_MASK);\
} while (0)


#define DMA_SFCSR3_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR3_RSN_RD(data) do {\
	DMA_SFCSR3_RD(data);\
	data = ((data >> 16) & DMA_SFCSR3_RSN_MASK);\
} while (0)

#define DMA_SFCSR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x123c))

#define DMA_SFCSR2_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR2_OFFSET);\
} while (0)

#define DMA_SFCSR2_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR2_OFFSET);\
} while (0)


#define  DMA_SFCSR2_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR2_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR2_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR2_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR2_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR2_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR2_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR2_RD(v);\
	v = (v & (DMA_SFCSR2_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR2_MASK_2))<<2);\
	v = (v & (DMA_SFCSR2_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR2_MASK_20))<<20);\
	v = ((v & DMA_SFCSR2_ESC_WR_MASK)\
	|((data & DMA_SFCSR2_ESC_MASK)<<0));\
	DMA_SFCSR2_WR(v);\
} while (0)

#define DMA_SFCSR2_ESC_RD(data) do {\
	DMA_SFCSR2_RD(data);\
	data = ((data >> 0) & DMA_SFCSR2_ESC_MASK);\
} while (0)


#define DMA_SFCSR2_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR2_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR2_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR2_RD(v);\
	v = (v & (DMA_SFCSR2_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR2_MASK_2))<<2);\
	v = (v & (DMA_SFCSR2_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR2_MASK_20))<<20);\
	v = ((v & DMA_SFCSR2_ASC_WR_MASK)\
	|((data & DMA_SFCSR2_ASC_MASK)<<1));\
	DMA_SFCSR2_WR(v);\
} while (0)

#define DMA_SFCSR2_ASC_RD(data) do {\
	DMA_SFCSR2_RD(data);\
	data = ((data >> 1) & DMA_SFCSR2_ASC_MASK);\
} while (0)


#define DMA_SFCSR2_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR2_RSN_RD(data) do {\
	DMA_SFCSR2_RD(data);\
	data = ((data >> 16) & DMA_SFCSR2_RSN_MASK);\
} while (0)

#define DMA_SFCSR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11bc))

#define DMA_SFCSR1_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR1_OFFSET);\
} while (0)

#define DMA_SFCSR1_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR1_OFFSET);\
} while (0)


#define  DMA_SFCSR1_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR1_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR1_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR1_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR1_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR1_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR1_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR1_RD(v);\
	v = (v & (DMA_SFCSR1_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR1_MASK_2))<<2);\
	v = (v & (DMA_SFCSR1_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR1_MASK_20))<<20);\
	v = ((v & DMA_SFCSR1_ESC_WR_MASK)\
	|((data & DMA_SFCSR1_ESC_MASK)<<0));\
	DMA_SFCSR1_WR(v);\
} while (0)

#define DMA_SFCSR1_ESC_RD(data) do {\
	DMA_SFCSR1_RD(data);\
	data = ((data >> 0) & DMA_SFCSR1_ESC_MASK);\
} while (0)


#define DMA_SFCSR1_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR1_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR1_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR1_RD(v);\
	v = (v & (DMA_SFCSR1_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR1_MASK_2))<<2);\
	v = (v & (DMA_SFCSR1_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR1_MASK_20))<<20);\
	v = ((v & DMA_SFCSR1_ASC_WR_MASK)\
	|((data & DMA_SFCSR1_ASC_MASK)<<1));\
	DMA_SFCSR1_WR(v);\
} while (0)

#define DMA_SFCSR1_ASC_RD(data) do {\
	DMA_SFCSR1_RD(data);\
	data = ((data >> 1) & DMA_SFCSR1_ASC_MASK);\
} while (0)


#define DMA_SFCSR1_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR1_RSN_RD(data) do {\
	DMA_SFCSR1_RD(data);\
	data = ((data >> 16) & DMA_SFCSR1_RSN_MASK);\
} while (0)

#define DMA_SFCSR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x113c))

#define DMA_SFCSR0_WR(data) do {\
	iowrite32(data, (void *)DMA_SFCSR0_OFFSET);\
} while (0)

#define DMA_SFCSR0_RD(data) do {\
	(data) = ioread32((void *)DMA_SFCSR0_OFFSET);\
} while (0)


#define  DMA_SFCSR0_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR0_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define  DMA_SFCSR0_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR0_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_SFCSR0_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR0_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR0_ESC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR0_RD(v);\
	v = (v & (DMA_SFCSR0_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR0_MASK_2))<<2);\
	v = (v & (DMA_SFCSR0_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR0_MASK_20))<<20);\
	v = ((v & DMA_SFCSR0_ESC_WR_MASK)\
	|((data & DMA_SFCSR0_ESC_MASK)<<0));\
	DMA_SFCSR0_WR(v);\
} while (0)

#define DMA_SFCSR0_ESC_RD(data) do {\
	DMA_SFCSR0_RD(data);\
	data = ((data >> 0) & DMA_SFCSR0_ESC_MASK);\
} while (0)


#define DMA_SFCSR0_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR0_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR0_ASC_WR(data) do {\
	ULONG v;\
	DMA_SFCSR0_RD(v);\
	v = (v & (DMA_SFCSR0_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR0_MASK_2))<<2);\
	v = (v & (DMA_SFCSR0_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR0_MASK_20))<<20);\
	v = ((v & DMA_SFCSR0_ASC_WR_MASK)\
	|((data & DMA_SFCSR0_ASC_MASK)<<1));\
	DMA_SFCSR0_WR(v);\
} while (0)

#define DMA_SFCSR0_ASC_RD(data) do {\
	DMA_SFCSR0_RD(data);\
	data = ((data >> 1) & DMA_SFCSR0_ASC_MASK);\
} while (0)


#define DMA_SFCSR0_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR0_RSN_RD(data) do {\
	DMA_SFCSR0_RD(data);\
	data = ((data >> 16) & DMA_SFCSR0_RSN_MASK);\
} while (0)

#define MAC_IVLANTIRR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x64))

#define MAC_IVLANTIRR_WR(data) do {\
	iowrite32(data, (void *)MAC_IVLANTIRR_OFFSET);\
} while (0)

#define MAC_IVLANTIRR_RD(data) do {\
	(data) = ioread32((void *)MAC_IVLANTIRR_OFFSET);\
} while (0)


#define  MAC_IVLANTIRR_MASK_21 (ULONG)(0x7ff)


#define MAC_IVLANTIRR_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MAC_IVLANTIRR_VLTI_MASK (ULONG)(0x1)


#define MAC_IVLANTIRR_VLTI_WR_MASK (ULONG)(0xffefffff)

#define MAC_IVLANTIRR_VLTI_WR(data) do {\
	ULONG v;\
	MAC_IVLANTIRR_RD(v);\
	v = (v & (MAC_IVLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_IVLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_IVLANTIRR_VLTI_WR_MASK)\
	|((data & MAC_IVLANTIRR_VLTI_MASK)<<20));\
	MAC_IVLANTIRR_WR(v);\
} while (0)

#define MAC_IVLANTIRR_VLTI_RD(data) do {\
	MAC_IVLANTIRR_RD(data);\
	data = ((data >> 20) & MAC_IVLANTIRR_VLTI_MASK);\
} while (0)


#define MAC_IVLANTIRR_CSVL_MASK (ULONG)(0x1)


#define MAC_IVLANTIRR_CSVL_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_IVLANTIRR_CSVL_WR(data) do {\
	ULONG v;\
	MAC_IVLANTIRR_RD(v);\
	v = (v & (MAC_IVLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_IVLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_IVLANTIRR_CSVL_WR_MASK)\
	|((data & MAC_IVLANTIRR_CSVL_MASK)<<19));\
	MAC_IVLANTIRR_WR(v);\
} while (0)

#define MAC_IVLANTIRR_CSVL_RD(data) do {\
	MAC_IVLANTIRR_RD(data);\
	data = ((data >> 19) & MAC_IVLANTIRR_CSVL_MASK);\
} while (0)


#define MAC_IVLANTIRR_VLP_MASK (ULONG)(0x1)


#define MAC_IVLANTIRR_VLP_WR_MASK (ULONG)(0xfffbffff)

#define MAC_IVLANTIRR_VLP_WR(data) do {\
	ULONG v;\
	MAC_IVLANTIRR_RD(v);\
	v = (v & (MAC_IVLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_IVLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_IVLANTIRR_VLP_WR_MASK)\
	|((data & MAC_IVLANTIRR_VLP_MASK)<<18));\
	MAC_IVLANTIRR_WR(v);\
} while (0)

#define MAC_IVLANTIRR_VLP_RD(data) do {\
	MAC_IVLANTIRR_RD(data);\
	data = ((data >> 18) & MAC_IVLANTIRR_VLP_MASK);\
} while (0)


#define MAC_IVLANTIRR_VLC_MASK (ULONG)(0x3)


#define MAC_IVLANTIRR_VLC_WR_MASK (ULONG)(0xfffcffff)

#define MAC_IVLANTIRR_VLC_WR(data) do {\
	ULONG v;\
	MAC_IVLANTIRR_RD(v);\
	v = (v & (MAC_IVLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_IVLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_IVLANTIRR_VLC_WR_MASK)\
	|((data & MAC_IVLANTIRR_VLC_MASK)<<16));\
	MAC_IVLANTIRR_WR(v);\
} while (0)

#define MAC_IVLANTIRR_VLC_RD(data) do {\
	MAC_IVLANTIRR_RD(data);\
	data = ((data >> 16) & MAC_IVLANTIRR_VLC_MASK);\
} while (0)


#define MAC_IVLANTIRR_VLT_MASK (ULONG)(0xffff)


#define MAC_IVLANTIRR_VLT_WR_MASK (ULONG)(0xffff0000)

#define MAC_IVLANTIRR_VLT_WR(data) do {\
	ULONG v;\
	MAC_IVLANTIRR_RD(v);\
	v = (v & (MAC_IVLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_IVLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_IVLANTIRR_VLT_WR_MASK)\
	|((data & MAC_IVLANTIRR_VLT_MASK)<<0));\
	MAC_IVLANTIRR_WR(v);\
} while (0)

#define MAC_IVLANTIRR_VLT_RD(data) do {\
	MAC_IVLANTIRR_RD(data);\
	data = ((data >> 0) & MAC_IVLANTIRR_VLT_MASK);\
} while (0)

#define MAC_VLANTIRR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x60))

#define MAC_VLANTIRR_WR(data) do {\
	iowrite32(data, (void *)MAC_VLANTIRR_OFFSET);\
} while (0)

#define MAC_VLANTIRR_RD(data) do {\
	(data) = ioread32((void *)MAC_VLANTIRR_OFFSET);\
} while (0)


#define  MAC_VLANTIRR_MASK_21 (ULONG)(0x7ff)


#define MAC_VLANTIRR_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MAC_VLANTIRR_VLTI_MASK (ULONG)(0x1)


#define MAC_VLANTIRR_VLTI_WR_MASK (ULONG)(0xffefffff)

#define MAC_VLANTIRR_VLTI_WR(data) do {\
	ULONG v;\
	MAC_VLANTIRR_RD(v);\
	v = (v & (MAC_VLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_VLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_VLANTIRR_VLTI_WR_MASK)\
	|((data & MAC_VLANTIRR_VLTI_MASK)<<20));\
	MAC_VLANTIRR_WR(v);\
} while (0)

#define MAC_VLANTIRR_VLTI_RD(data) do {\
	MAC_VLANTIRR_RD(data);\
	data = ((data >> 20) & MAC_VLANTIRR_VLTI_MASK);\
} while (0)


#define MAC_VLANTIRR_CSVL_MASK (ULONG)(0x1)


#define MAC_VLANTIRR_CSVL_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_VLANTIRR_CSVL_WR(data) do {\
	ULONG v;\
	MAC_VLANTIRR_RD(v);\
	v = (v & (MAC_VLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_VLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_VLANTIRR_CSVL_WR_MASK)\
	|((data & MAC_VLANTIRR_CSVL_MASK)<<19));\
	MAC_VLANTIRR_WR(v);\
} while (0)

#define MAC_VLANTIRR_CSVL_RD(data) do {\
	MAC_VLANTIRR_RD(data);\
	data = ((data >> 19) & MAC_VLANTIRR_CSVL_MASK);\
} while (0)


#define MAC_VLANTIRR_VLP_MASK (ULONG)(0x1)


#define MAC_VLANTIRR_VLP_WR_MASK (ULONG)(0xfffbffff)

#define MAC_VLANTIRR_VLP_WR(data) do {\
	ULONG v;\
	MAC_VLANTIRR_RD(v);\
	v = (v & (MAC_VLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_VLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_VLANTIRR_VLP_WR_MASK)\
	|((data & MAC_VLANTIRR_VLP_MASK)<<18));\
	MAC_VLANTIRR_WR(v);\
} while (0)

#define MAC_VLANTIRR_VLP_RD(data) do {\
	MAC_VLANTIRR_RD(data);\
	data = ((data >> 18) & MAC_VLANTIRR_VLP_MASK);\
} while (0)


#define MAC_VLANTIRR_VLC_MASK (ULONG)(0x3)


#define MAC_VLANTIRR_VLC_WR_MASK (ULONG)(0xfffcffff)

#define MAC_VLANTIRR_VLC_WR(data) do {\
	ULONG v;\
	MAC_VLANTIRR_RD(v);\
	v = (v & (MAC_VLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_VLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_VLANTIRR_VLC_WR_MASK)\
	|((data & MAC_VLANTIRR_VLC_MASK)<<16));\
	MAC_VLANTIRR_WR(v);\
} while (0)

#define MAC_VLANTIRR_VLC_RD(data) do {\
	MAC_VLANTIRR_RD(data);\
	data = ((data >> 16) & MAC_VLANTIRR_VLC_MASK);\
} while (0)


#define MAC_VLANTIRR_VLT_MASK (ULONG)(0xffff)


#define MAC_VLANTIRR_VLT_WR_MASK (ULONG)(0xffff0000)

#define MAC_VLANTIRR_VLT_WR(data) do {\
	ULONG v;\
	MAC_VLANTIRR_RD(v);\
	v = (v & (MAC_VLANTIRR_RES_WR_MASK_21))\
	|(((0) & (MAC_VLANTIRR_MASK_21))<<21);\
	v = ((v & MAC_VLANTIRR_VLT_WR_MASK)\
	|((data & MAC_VLANTIRR_VLT_MASK)<<0));\
	MAC_VLANTIRR_WR(v);\
} while (0)

#define MAC_VLANTIRR_VLT_RD(data) do {\
	MAC_VLANTIRR_RD(data);\
	data = ((data >> 0) & MAC_VLANTIRR_VLT_MASK);\
} while (0)

#define MAC_VLANHTR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x58))

#define MAC_VLANHTR_WR(data) do {\
	iowrite32(data, (void *)MAC_VLANHTR_OFFSET);\
} while (0)

#define MAC_VLANHTR_RD(data) do {\
	(data) = ioread32((void *)MAC_VLANHTR_OFFSET);\
} while (0)


#define  MAC_VLANHTR_MASK_16 (ULONG)(0xffff)


#define MAC_VLANHTR_RES_WR_MASK_16 (ULONG)(0xffff)


#define MAC_VLANHTR_VLHT_MASK (ULONG)(0xffff)


#define MAC_VLANHTR_VLHT_WR_MASK (ULONG)(0xffff0000)

#define MAC_VLANHTR_VLHT_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MAC_VLANHTR_RES_WR_MASK_16))\
	|(((0) & (MAC_VLANHTR_MASK_16))<<16);\
	(v) = ((v & MAC_VLANHTR_VLHT_WR_MASK)\
	|((data & MAC_VLANHTR_VLHT_MASK)<<0));\
	MAC_VLANHTR_WR(v);\
} while (0)

#define MAC_VLANHTR_VLHT_RD(data) do {\
	MAC_VLANHTR_RD(data);\
	data = ((data >> 0) & MAC_VLANHTR_VLHT_MASK);\
} while (0)

#define MAC_VLANTR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x50))

#define MAC_VLANTR_WR(data) do {\
	iowrite32(data, (void *)MAC_VLANTR_OFFSET);\
} while (0)

#define MAC_VLANTR_RD(data) do {\
	(data) = ioread32((void *)MAC_VLANTR_OFFSET);\
} while (0)


#define  MAC_VLANTR_MASK_30 (ULONG)(0x1)


#define MAC_VLANTR_RES_WR_MASK_30 (ULONG)(0xbfffffff)


#define  MAC_VLANTR_MASK_23 (ULONG)(0x1)


#define MAC_VLANTR_RES_WR_MASK_23 (ULONG)(0xff7fffff)


#define MAC_VLANTR_EIVLRXS_MASK (ULONG)(0x1)


#define MAC_VLANTR_EIVLRXS_WR_MASK (ULONG)(0x7fffffff)

#define MAC_VLANTR_EIVLRXS_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_EIVLRXS_WR_MASK)\
	|((data & MAC_VLANTR_EIVLRXS_MASK)<<31));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_EIVLRXS_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 31) & MAC_VLANTR_EIVLRXS_MASK);\
} while (0)


#define MAC_VLANTR_EIVLS_MASK (ULONG)(0x3)


#define MAC_VLANTR_EIVLS_WR_MASK (ULONG)(0xcfffffff)

#define MAC_VLANTR_EIVLS_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_EIVLS_WR_MASK)\
	|((data & MAC_VLANTR_EIVLS_MASK)<<28));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_EIVLS_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 28) & MAC_VLANTR_EIVLS_MASK);\
} while (0)


#define MAC_VLANTR_ERIVLT_MASK (ULONG)(0x1)


#define MAC_VLANTR_ERIVLT_WR_MASK (ULONG)(0xf7ffffff)

#define MAC_VLANTR_ERIVLT_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_ERIVLT_WR_MASK)\
	|((data & MAC_VLANTR_ERIVLT_MASK)<<27));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_ERIVLT_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 27) & MAC_VLANTR_ERIVLT_MASK);\
} while (0)


#define MAC_VLANTR_EDVLP_MASK (ULONG)(0x1)


#define MAC_VLANTR_EDVLP_WR_MASK (ULONG)(0xfbffffff)

#define MAC_VLANTR_EDVLP_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_EDVLP_WR_MASK)\
	|((data & MAC_VLANTR_EDVLP_MASK)<<26));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_EDVLP_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 26) & MAC_VLANTR_EDVLP_MASK);\
} while (0)


#define MAC_VLANTR_VTHM_MASK (ULONG)(0x1)


#define MAC_VLANTR_VTHM_WR_MASK (ULONG)(0xfdffffff)

#define MAC_VLANTR_VTHM_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_VTHM_WR_MASK)\
	|((data & MAC_VLANTR_VTHM_MASK)<<25));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_VTHM_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 25) & MAC_VLANTR_VTHM_MASK);\
} while (0)


#define MAC_VLANTR_EVLRXS_MASK (ULONG)(0x1)


#define MAC_VLANTR_EVLRXS_WR_MASK (ULONG)(0xfeffffff)

#define MAC_VLANTR_EVLRXS_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_EVLRXS_WR_MASK)\
	|((data & MAC_VLANTR_EVLRXS_MASK)<<24));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_EVLRXS_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 24) & MAC_VLANTR_EVLRXS_MASK);\
} while (0)


#define MAC_VLANTR_EVLS_MASK (ULONG)(0x3)


#define MAC_VLANTR_EVLS_WR_MASK (ULONG)(0xff9fffff)

#define MAC_VLANTR_EVLS_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_EVLS_WR_MASK)\
	|((data & MAC_VLANTR_EVLS_MASK)<<21));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_EVLS_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 21) & MAC_VLANTR_EVLS_MASK);\
} while (0)


#define MAC_VLANTR_DOVLTC_MASK (ULONG)(0x1)


#define MAC_VLANTR_DOVLTC_WR_MASK (ULONG)(0xffefffff)

#define MAC_VLANTR_DOVLTC_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_DOVLTC_WR_MASK)\
	|((data & MAC_VLANTR_DOVLTC_MASK)<<20));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_DOVLTC_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 20) & MAC_VLANTR_DOVLTC_MASK);\
} while (0)


#define MAC_VLANTR_ERSVLM_MASK (ULONG)(0x1)


#define MAC_VLANTR_ERSVLM_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_VLANTR_ERSVLM_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_ERSVLM_WR_MASK)\
	|((data & MAC_VLANTR_ERSVLM_MASK)<<19));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_ERSVLM_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 19) & MAC_VLANTR_ERSVLM_MASK);\
} while (0)


#define MAC_VLANTR_ESVL_MASK (ULONG)(0x1)


#define MAC_VLANTR_ESVL_WR_MASK (ULONG)(0xfffbffff)

#define MAC_VLANTR_ESVL_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_ESVL_WR_MASK)\
	|((data & MAC_VLANTR_ESVL_MASK)<<18));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_ESVL_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 18) & MAC_VLANTR_ESVL_MASK);\
} while (0)


#define MAC_VLANTR_VTIM_MASK (ULONG)(0x1)


#define MAC_VLANTR_VTIM_WR_MASK (ULONG)(0xfffdffff)

#define MAC_VLANTR_VTIM_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_VTIM_WR_MASK)\
	|((data & MAC_VLANTR_VTIM_MASK)<<17));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_VTIM_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 17) & MAC_VLANTR_VTIM_MASK);\
} while (0)


#define MAC_VLANTR_ETV_MASK (ULONG)(0x1)


#define MAC_VLANTR_ETV_WR_MASK (ULONG)(0xfffeffff)

#define MAC_VLANTR_ETV_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_ETV_WR_MASK)\
	|((data & MAC_VLANTR_ETV_MASK)<<16));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_ETV_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 16) & MAC_VLANTR_ETV_MASK);\
} while (0)


#define MAC_VLANTR_VL_MASK (ULONG)(0xffff)


#define MAC_VLANTR_VL_WR_MASK (ULONG)(0xffff0000)

#define MAC_VLANTR_VL_WR(data) do {\
	ULONG v;\
	MAC_VLANTR_RD(v);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_30))\
	|(((0) & (MAC_VLANTR_MASK_30))<<30);\
	v = (v & (MAC_VLANTR_RES_WR_MASK_23))\
	|(((0) & (MAC_VLANTR_MASK_23))<<23);\
	v = ((v & MAC_VLANTR_VL_WR_MASK)\
	|((data & MAC_VLANTR_VL_MASK)<<0));\
	MAC_VLANTR_WR(v);\
} while (0)

#define MAC_VLANTR_VL_RD(data) do {\
	MAC_VLANTR_RD(data);\
	data = ((data >> 0) & MAC_VLANTR_VL_MASK);\
} while (0)

#define DMA_SBUS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1004))

#define DMA_SBUS_WR(data) do {\
	iowrite32(data, (void *)DMA_SBUS_OFFSET);\
} while (0)

#define DMA_SBUS_RD(data) do {\
	(data) = ioread32((void *)DMA_SBUS_OFFSET);\
} while (0)


#define  DMA_SBUS_MASK_25 (ULONG)(0x1f)


#define DMA_SBUS_RES_WR_MASK_25 (ULONG)(0xc1ffffff)


#define  DMA_SBUS_MASK_20 (ULONG)(0x1)


#define DMA_SBUS_RES_WR_MASK_20 (ULONG)(0xffefffff)


#define  DMA_SBUS_MASK_15 (ULONG)(0x1)


#define DMA_SBUS_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_SBUS_MASK_8 (ULONG)(0xf)



/* For DMA addressing modes greater than 32 bit, 11th bit is not RO.
	Instead of using 4bit mask, use 3bit mask to reset 8th bit */

#define DMA_SBUS_RES_WR_MASK_8 (ULONG)(0xfffff8ff)


#define DMA_SBUS_EAME_MASK (ULONG)(0x1)

#define DMA_SBUS_EAME_WR_MASK (ULONG)(0xfffff7ff)

#define DMA_SBUS_EAME_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_EAME_WR_MASK)\
	|((data & DMA_SBUS_EAME_MASK)<<11));\
	DMA_SBUS_WR(v);\
} while (0)


#define DMA_SBUS_EN_LPI_MASK (ULONG)(0x1)


#define DMA_SBUS_EN_LPI_WR_MASK (ULONG)(0x7fffffff)

#define DMA_SBUS_EN_LPI_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_EN_LPI_WR_MASK)\
	|((data & DMA_SBUS_EN_LPI_MASK)<<31));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_EN_LPI_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 31) & DMA_SBUS_EN_LPI_MASK);\
} while (0)


#define DMA_SBUS_LPI_XIT_PKT_MASK (ULONG)(0x1)


#define DMA_SBUS_LPI_XIT_PKT_WR_MASK (ULONG)(0xbfffffff)

#define DMA_SBUS_LPI_XIT_PKT_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_LPI_XIT_PKT_WR_MASK)\
	|((data & DMA_SBUS_LPI_XIT_PKT_MASK)<<30));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_LPI_XIT_PKT_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 30) & DMA_SBUS_LPI_XIT_PKT_MASK);\
} while (0)

/* DMA AXI bitmap */
#define DMA_AXI_WR_OSR_LMT_V4              GENMASK(27, 24)
#define DMA_AXI_RD_OSR_LMT_V4              GENMASK(19, 16)
#define DMA_AXI_WR_OSR_LMT              GENMASK(28, 24)
#define DMA_AXI_WR_OSR_LMT_SHIFT        24
#define DMA_AXI_RD_OSR_LMT              GENMASK(20, 16)
#define DMA_AXI_RD_OSR_LMT_SHIFT        16
#define DMA_AXI_EAME            BIT(11)
#define DMA_AXI_BLEN256         BIT(7)
#define DMA_AXI_BLEN128         BIT(6)
#define DMA_AXI_BLEN64          BIT(5)
#define DMA_AXI_BLEN32          BIT(4)
#define DMA_AXI_BLEN16          BIT(3)
#define DMA_AXI_BLEN8           BIT(2)

#define DMA_SBUS_WR_OSR_LMT_MASK (ULONG)(0xf)


#define DMA_SBUS_WR_OSR_LMT_WR_MASK (ULONG)(0xfe1fffff)

#define DMA_SBUS_WR_OSR_LMT_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_WR_OSR_LMT_WR_MASK)\
	|((data & DMA_SBUS_WR_OSR_LMT_MASK)<<21));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_WR_OSR_LMT_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 21) & DMA_SBUS_WR_OSR_LMT_MASK);\
} while (0)


#define DMA_SBUS_RD_OSR_LMT_MASK (ULONG)(0xf)


#define DMA_SBUS_RD_OSR_LMT_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_SBUS_RD_OSR_LMT_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_RD_OSR_LMT_WR_MASK)\
	|((data & DMA_SBUS_RD_OSR_LMT_MASK)<<16));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_RD_OSR_LMT_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 16) & DMA_SBUS_RD_OSR_LMT_MASK);\
} while (0)


#define DMA_SBUS_MB_MASK (ULONG)(0x1)


#define DMA_SBUS_MB_WR_MASK (ULONG)(0xffffbfff)

#define DMA_SBUS_MB_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_MB_WR_MASK)\
	|((data & DMA_SBUS_MB_MASK)<<14));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_MB_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 14) & DMA_SBUS_MB_MASK);\
} while (0)


#define DMA_SBUS_ONEKBBE_MASK (ULONG)(0x1)


#define DMA_SBUS_ONEKBBE_WR_MASK (ULONG)(0xffffdfff)

#define DMA_SBUS_ONEKBBE_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_ONEKBBE_WR_MASK)\
	|((data & DMA_SBUS_ONEKBBE_MASK)<<13));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_ONEKBBE_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 13) & DMA_SBUS_ONEKBBE_MASK);\
} while (0)


#define DMA_SBUS_AAL_MASK (ULONG)(0x1)


#define DMA_SBUS_AAL_WR_MASK (ULONG)(0xffffefff)

#define DMA_SBUS_AAL_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_AAL_WR_MASK)\
	|((data & DMA_SBUS_AAL_MASK)<<12));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_AAL_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 12) & DMA_SBUS_AAL_MASK);\
} while (0)


#define DMA_SBUS_BLEN256_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN256_WR_MASK (ULONG)(0xffffff7f)

#define DMA_SBUS_BLEN256_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN256_WR_MASK)\
	|((data & DMA_SBUS_BLEN256_MASK)<<7));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN256_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 7) & DMA_SBUS_BLEN256_MASK);\
} while (0)


#define DMA_SBUS_BLEN128_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN128_WR_MASK (ULONG)(0xffffffbf)

#define DMA_SBUS_BLEN128_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN128_WR_MASK)\
	|((data & DMA_SBUS_BLEN128_MASK)<<6));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN128_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 6) & DMA_SBUS_BLEN128_MASK);\
} while (0)


#define DMA_SBUS_BLEN64_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN64_WR_MASK (ULONG)(0xffffffdf)

#define DMA_SBUS_BLEN64_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN64_WR_MASK)\
	|((data & DMA_SBUS_BLEN64_MASK)<<5));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN64_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 5) & DMA_SBUS_BLEN64_MASK);\
} while (0)


#define DMA_SBUS_BLEN32_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN32_WR_MASK (ULONG)(0xffffffef)

#define DMA_SBUS_BLEN32_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN32_WR_MASK)\
	|((data & DMA_SBUS_BLEN32_MASK)<<4));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN32_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 4) & DMA_SBUS_BLEN32_MASK);\
} while (0)


#define DMA_SBUS_BLEN16_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN16_WR_MASK (ULONG)(0xfffffff7)

#define DMA_SBUS_BLEN16_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN16_WR_MASK)\
	|((data & DMA_SBUS_BLEN16_MASK)<<3));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN16_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 3) & DMA_SBUS_BLEN16_MASK);\
} while (0)


#define DMA_SBUS_BLEN8_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN8_WR_MASK (ULONG)(0xfffffffb)

#define DMA_SBUS_BLEN8_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN8_WR_MASK)\
	|((data & DMA_SBUS_BLEN8_MASK)<<2));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN8_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 2) & DMA_SBUS_BLEN8_MASK);\
} while (0)


#define DMA_SBUS_BLEN4_MASK (ULONG)(0x1)


#define DMA_SBUS_BLEN4_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SBUS_BLEN4_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_BLEN4_WR_MASK)\
	|((data & DMA_SBUS_BLEN4_MASK)<<1));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_BLEN4_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 1) & DMA_SBUS_BLEN4_MASK);\
} while (0)


#define DMA_SBUS_UNDEF_FB_MASK (ULONG)(0x1)


#define DMA_SBUS_UNDEF_FB_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SBUS_UNDEF_FB_WR(data) do {\
	ULONG v;\
	DMA_SBUS_RD(v);\
	v = (v & (DMA_SBUS_RES_WR_MASK_25))\
	|(((0) & (DMA_SBUS_MASK_25))<<25);\
	v = (v & (DMA_SBUS_RES_WR_MASK_20))\
	|(((0) & (DMA_SBUS_MASK_20))<<20);\
	v = (v & (DMA_SBUS_RES_WR_MASK_15))\
	|(((0) & (DMA_SBUS_MASK_15))<<15);\
	v = (v & (DMA_SBUS_RES_WR_MASK_8))\
	|(((0) & (DMA_SBUS_MASK_8))<<8);\
	v = ((v & DMA_SBUS_UNDEF_FB_WR_MASK)\
	|((data & DMA_SBUS_UNDEF_FB_MASK)<<0));\
	DMA_SBUS_WR(v);\
} while (0)

#define DMA_SBUS_UNDEF_FB_RD(data) do {\
	DMA_SBUS_RD(data);\
	data = ((data >> 0) & DMA_SBUS_UNDEF_FB_MASK);\
} while (0)

#define DMA_BMR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1000))

#define DMA_BMR_WR(data) do {\
	iowrite32(data, (void *)DMA_BMR_OFFSET);\
} while (0)

#define DMA_BMR_RD(data) do {\
	(data) = ioread32((void *)DMA_BMR_OFFSET);\
} while (0)


#define  DMA_BMR_MASK_15 (ULONG)(0xffff)


#define DMA_BMR_RES_WR_MASK_15 (ULONG)(0x80007fff)


#define  DMA_BMR_MASK_6 (ULONG)(0x1f)


#define DMA_BMR_RES_WR_MASK_6 (ULONG)(0xfffff83f)


#define DMA_BMR_RIB_MASK (ULONG)(0x1)


#define DMA_BMR_RIB_WR_MASK (ULONG)(0x7fffffff)

#define DMA_BMR_RIB_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_RIB_WR_MASK)\
	|((data & DMA_BMR_RIB_MASK)<<31));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_RIB_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 31) & DMA_BMR_RIB_MASK);\
} while (0)


#define DMA_BMR_PR_MASK (ULONG)(0x7)


#define DMA_BMR_PR_WR_MASK (ULONG)(0xffff8fff)

#define DMA_BMR_PR_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_PR_WR_MASK)\
	|((data & DMA_BMR_PR_MASK)<<12));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_PR_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 12) & DMA_BMR_PR_MASK);\
} while (0)


#define DMA_BMR_TXPR_MASK (ULONG)(0x1)


#define DMA_BMR_TXPR_WR_MASK (ULONG)(0xfffff7ff)

#define DMA_BMR_TXPR_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_TXPR_WR_MASK)\
	|((data & DMA_BMR_TXPR_MASK)<<11));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_TXPR_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 11) & DMA_BMR_TXPR_MASK);\
} while (0)


#define DMA_BMR_DTXSTS_MASK (ULONG)(0x1)


#define DMA_BMR_DTXSTS_WR_MASK (ULONG)(0xffffffdf)

#define DMA_BMR_DTXSTS_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_DTXSTS_WR_MASK)\
	|((data & DMA_BMR_DTXSTS_MASK)<<5));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_DTXSTS_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 5) & DMA_BMR_DTXSTS_MASK);\
} while (0)


#define DMA_BMR_TAA_MASK (ULONG)(0x7)


#define DMA_BMR_TAA_WR_MASK (ULONG)(0xffffffe3)

#define DMA_BMR_TAA_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_TAA_WR_MASK)\
	|((data & DMA_BMR_TAA_MASK)<<2));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_TAA_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 2) & DMA_BMR_TAA_MASK);\
} while (0)


#define DMA_BMR_DA_MASK (ULONG)(0x1)


#define DMA_BMR_DA_WR_MASK (ULONG)(0xfffffffd)

#define DMA_BMR_DA_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_DA_WR_MASK)\
	|((data & DMA_BMR_DA_MASK)<<1));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_DA_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 1) & DMA_BMR_DA_MASK);\
} while (0)


#define DMA_BMR_SWR_MASK (ULONG)(0x1)


#define DMA_BMR_SWR_WR_MASK (ULONG)(0xfffffffe)

#define DMA_BMR_SWR_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	|(((0) & (DMA_BMR_MASK_15))<<15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	|(((0) & (DMA_BMR_MASK_6))<<6);\
	v = ((v & DMA_BMR_SWR_WR_MASK)\
	|((data & DMA_BMR_SWR_MASK)<<0));\
	DMA_BMR_WR(v);\
} while (0)

#define DMA_BMR_SWR_RD(data) do {\
	DMA_BMR_RD(data);\
	data = ((data >> 0) & DMA_BMR_SWR_MASK);\
} while (0)

#define DMA_BMR_DSPW_MASK (ULONG)(0x1)

#define DMA_BMR_DSPW_WR_MASK (ULONG)(0xfffffeff)

#define DMA_BMR_DSPW_WR(data) do {\
	ULONG v;\
	DMA_BMR_RD(v);\
	v = (v & (DMA_BMR_RES_WR_MASK_15))\
	| (((0) & (DMA_BMR_MASK_15)) << 15);\
	v = (v & (DMA_BMR_RES_WR_MASK_6))\
	| (((0) & (DMA_BMR_MASK_6)) << 6);\
	v = ((v & DMA_BMR_DSPW_WR_MASK)\
	| (((data) & DMA_BMR_DSPW_MASK) << 8));\
	DMA_BMR_WR(v);\
} while (0)

#define MAC_CSR_SW_CTRL_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x230))

#define MAC_CSR_SW_CTRL_RD(data) do {\
	(data) = ioread32((void *)MAC_CSR_SW_CTRL_OFFSET);\
} while (0)

#define MAC_CSR_SW_CTRL_WR(data) do {\
	iowrite32(data, (void *)MAC_CSR_SW_CTRL_OFFSET);\
} while (0)

#define MAC_CSR_SEEN_WR_MASK (ULONG)(0xfffffeff)
#define MAC_CSR_SEEN_MASK (ULONG)(0x1)

#define MAC_CSR_SEEN_WR(data) do {\
	ULONG v;\
	MAC_CSR_SW_CTRL_RD(v);\
	v = ((v & MAC_CSR_SEEN_WR_MASK)\
	| (((data) & MAC_CSR_SEEN_MASK) << 8));\
	MAC_CSR_SW_CTRL_WR(v);\
} while (0)

#define MTL_Q0RCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd3c))

#define MTL_Q0RCR_WR(data) do {\
	iowrite32(data, (void *)MTL_Q0RCR_OFFSET);\
} while (0)

#define MTL_Q0RCR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0RCR_OFFSET);\
} while (0)


#define  MTL_Q0RCR_MASK_4 (ULONG)(0xfffffff)


#define MTL_Q0RCR_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_Q0RCR_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_Q0RCR_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_Q0RCR_RXQ_PKT_ARBIT_WR(data) do {\
	ULONG v;\
	MTL_Q0RCR_RD(v);\
	v = (v & (MTL_Q0RCR_RES_WR_MASK_4))\
	|(((0) & (MTL_Q0RCR_MASK_4))<<4);\
	v = ((v & MTL_Q0RCR_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_Q0RCR_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_Q0RCR_WR(v);\
} while (0)

#define MTL_Q0RCR_RXQ_PKT_ARBIT_RD(data) do {\
	MTL_Q0RCR_RD(data);\
	data = ((data >> 3) & MTL_Q0RCR_RXQ_PKT_ARBIT_MASK);\
} while (0)


#define MTL_Q0RCR_RQW_MASK (ULONG)(0x7)


#define MTL_Q0RCR_RQW_WR_MASK (ULONG)(0xfffffff8)

#define MTL_Q0RCR_RQW_WR(data) do {\
	ULONG v;\
	MTL_Q0RCR_RD(v);\
	v = (v & (MTL_Q0RCR_RES_WR_MASK_4))\
	|(((0) & (MTL_Q0RCR_MASK_4))<<4);\
	v = ((v & MTL_Q0RCR_RQW_WR_MASK)\
	|((data & MTL_Q0RCR_RQW_MASK)<<0));\
	MTL_Q0RCR_WR(v);\
} while (0)

#define MTL_Q0RCR_RQW_RD(data) do {\
	MTL_Q0RCR_RD(data);\
	data = ((data >> 0) & MTL_Q0RCR_RQW_MASK);\
} while (0)

#define MTL_Q0OCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd34))

#define MTL_Q0OCR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0OCR_OFFSET);\
} while (0)


#define MTL_Q0OCR_MISCNTOVF_MASK (ULONG)(0x1)

#define MTL_Q0OCR_MISCNTOVF_RD(data) do {\
	MTL_Q0OCR_RD(data);\
	data = ((data >> 27) & MTL_Q0OCR_MISCNTOVF_MASK);\
} while (0)


#define MTL_Q0OCR_MISPKTCNT_MASK (ULONG)(0x7ff)

#define MTL_Q0OCR_MISPKTCNT_RD(data) do {\
	MTL_Q0OCR_RD(data);\
	data = ((data >> 16) & MTL_Q0OCR_MISPKTCNT_MASK);\
} while (0)


#define MTL_Q0OCR_OVFCNTOVF_MASK (ULONG)(0x1)

#define MTL_Q0OCR_OVFCNTOVF_RD(data) do {\
	MTL_Q0OCR_RD(data);\
	data = ((data >> 11) & MTL_Q0OCR_OVFCNTOVF_MASK);\
} while (0)


#define MTL_Q0OCR_OVFPKTCNT_MASK (ULONG)(0x7ff)

#define MTL_Q0OCR_OVFPKTCNT_RD(data) do {\
	MTL_Q0OCR_RD(data);\
	data = ((data >> 0) & MTL_Q0OCR_OVFPKTCNT_MASK);\
} while (0)

#define MTL_Q0ROMR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd30))

#define MTL_Q0ROMR_WR(data) do {\
	iowrite32(data, (void *)MTL_Q0ROMR_OFFSET);\
} while (0)

#define MTL_Q0ROMR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0ROMR_OFFSET);\
} while (0)


#define  MTL_Q0ROMR_MASK_30 (ULONG)(0x3)


#define MTL_Q0ROMR_RES_WR_MASK_30 (ULONG)(0x3fffffff)


#define  MTL_Q0ROMR_MASK_16 (ULONG)(0xf)


#define MTL_Q0ROMR_RES_WR_MASK_16 (ULONG)(0xfff0ffff)


#define  MTL_Q0ROMR_MASK_11 (ULONG)(0x3)


#define MTL_Q0ROMR_RES_WR_MASK_11 (ULONG)(0xffffe7ff)


#define  MTL_Q0ROMR_MASK_2 (ULONG)(0x1)


#define MTL_Q0ROMR_RES_WR_MASK_2 (ULONG)(0xfffffffb)


#define MTL_Q0ROMR_RQS_MASK (ULONG)(0x3ff)


#define MTL_Q0ROMR_RQS_WR_MASK (ULONG)(0xc00fffff)

#define MTL_Q0ROMR_RQS_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_RQS_WR_MASK)\
	|((data & MTL_Q0ROMR_RQS_MASK)<<20));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_RQS_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 20) & MTL_Q0ROMR_RQS_MASK);\
} while (0)


#define MTL_Q0ROMR_RFD_MASK (ULONG)(0x7)


#define MTL_Q0ROMR_RFD_WR_MASK (ULONG)(0xffff1fff)

#define MTL_Q0ROMR_RFD_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_RFD_WR_MASK)\
	|((data & MTL_Q0ROMR_RFD_MASK)<<13));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_RFD_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 13) & MTL_Q0ROMR_RFD_MASK);\
} while (0)


#define MTL_Q0ROMR_RFA_MASK (ULONG)(0x7)


#define MTL_Q0ROMR_RFA_WR_MASK (ULONG)(0xfffff8ff)

#define MTL_Q0ROMR_RFA_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_RFA_WR_MASK)\
	|((data & MTL_Q0ROMR_RFA_MASK)<<8));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_RFA_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 8) & MTL_Q0ROMR_RFA_MASK);\
} while (0)


#define MTL_Q0ROMR_EFC_MASK (ULONG)(0x1)


#define MTL_Q0ROMR_EFC_WR_MASK (ULONG)(0xffffff7f)

#define MTL_Q0ROMR_EFC_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_EFC_WR_MASK)\
	|((data & MTL_Q0ROMR_EFC_MASK)<<7));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_EFC_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 7) & MTL_Q0ROMR_EFC_MASK);\
} while (0)


#define MTL_Q0ROMR_DT_MASK (ULONG)(0x1)


#define MTL_Q0ROMR_DT_WR_MASK (ULONG)(0xffffffbf)

#define MTL_Q0ROMR_DT_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_DT_WR_MASK)\
	|((data & MTL_Q0ROMR_DT_MASK)<<6));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_DT_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 6) & MTL_Q0ROMR_DT_MASK);\
} while (0)


#define MTL_Q0ROMR_RSF_MASK (ULONG)(0x1)


#define MTL_Q0ROMR_RSF_WR_MASK (ULONG)(0xffffffdf)

#define MTL_Q0ROMR_RSF_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_RSF_WR_MASK)\
	|((data & MTL_Q0ROMR_RSF_MASK)<<5));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_RSF_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 5) & MTL_Q0ROMR_RSF_MASK);\
} while (0)


#define MTL_Q0ROMR_FEP_MASK (ULONG)(0x1)


#define MTL_Q0ROMR_FEP_WR_MASK (ULONG)(0xffffffef)

#define MTL_Q0ROMR_FEP_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_FEP_WR_MASK)\
	|((data & MTL_Q0ROMR_FEP_MASK)<<4));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_FEP_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 4) & MTL_Q0ROMR_FEP_MASK);\
} while (0)


#define MTL_Q0ROMR_FUP_MASK (ULONG)(0x1)


#define MTL_Q0ROMR_FUP_WR_MASK (ULONG)(0xfffffff7)

#define MTL_Q0ROMR_FUP_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_FUP_WR_MASK)\
	|((data & MTL_Q0ROMR_FUP_MASK)<<3));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_FUP_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 3) & MTL_Q0ROMR_FUP_MASK);\
} while (0)


#define MTL_Q0ROMR_RTC_MASK (ULONG)(0x3)


#define MTL_Q0ROMR_RTC_WR_MASK (ULONG)(0xfffffffc)

#define MTL_Q0ROMR_RTC_WR(data) do {\
	ULONG v;\
	MTL_Q0ROMR_RD(v);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_Q0ROMR_MASK_30))<<30);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_Q0ROMR_MASK_16))<<16);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_Q0ROMR_MASK_11))<<11);\
	v = (v & (MTL_Q0ROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_Q0ROMR_MASK_2))<<2);\
	v = ((v & MTL_Q0ROMR_RTC_WR_MASK)\
	|((data & MTL_Q0ROMR_RTC_MASK)<<0));\
	MTL_Q0ROMR_WR(v);\
} while (0)

#define MTL_Q0ROMR_RTC_RD(data) do {\
	MTL_Q0ROMR_RD(data);\
	data = ((data >> 0) & MTL_Q0ROMR_RTC_MASK);\
} while (0)

#define MTL_Q0QR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd18))

#define MTL_Q0QR_WR(data) do {\
	iowrite32(data, (void *)MTL_Q0QR_OFFSET);\
} while (0)

#define MTL_Q0QR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0QR_OFFSET);\
} while (0)


#define  MTL_Q0QR_MASK_21 (ULONG)(0x7ff)


#define MTL_Q0QR_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_Q0QR_QW_MASK (ULONG)(0x1fffff)


#define MTL_Q0QR_QW_WR_MASK (ULONG)(0xffe00000)

#define MTL_Q0QR_QW_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_Q0QR_RES_WR_MASK_21))\
	|(((0) & (MTL_Q0QR_MASK_21))<<21);\
	(v) = ((v & MTL_Q0QR_QW_WR_MASK)\
	|((data & MTL_Q0QR_QW_MASK)<<0));\
	MTL_Q0QR_WR(v);\
} while (0)

#define MTL_Q0QR_QW_RD(data) do {\
	MTL_Q0QR_RD(data);\
	data = ((data >> 0) & MTL_Q0QR_QW_MASK);\
} while (0)

#define MTL_Q0ECR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd10))

#define MTL_Q0ECR_WR(data) do {\
	iowrite32(data, (void *)MTL_Q0ECR_OFFSET);\
} while (0)

#define MTL_Q0ECR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0ECR_OFFSET);\
} while (0)


#define  MTL_Q0ECR_MASK_25 (ULONG)(0x7f)


#define MTL_Q0ECR_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define  MTL_Q0ECR_MASK_0 (ULONG)(0xffffff)


#define MTL_Q0ECR_RES_WR_MASK_0 (ULONG)(0xff000000)


#define MTL_Q0ECR_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_Q0ECR_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_Q0ECR_ABPSSIE_WR(data) do {\
	ULONG v = 0; \
	v = (v & (MTL_Q0ECR_RES_WR_MASK_25))\
	|(((0) & (MTL_Q0ECR_MASK_25))<<25);\
	v = (v & (MTL_Q0ECR_RES_WR_MASK_0))\
	|(((0) & (MTL_Q0ECR_MASK_0))<<0);\
	(v) = ((v & MTL_Q0ECR_ABPSSIE_WR_MASK)\
	|((data & MTL_Q0ECR_ABPSSIE_MASK)<<24));\
	MTL_Q0ECR_WR(v);\
} while (0)

#define MTL_Q0ECR_ABPSSIE_RD(data) do {\
	MTL_Q0ECR_RD(data);\
	data = ((data >> 24) & MTL_Q0ECR_ABPSSIE_MASK);\
} while (0)

#define MTL_Q0UCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd04))

#define MTL_Q0UCR_WR(data) do {\
	iowrite32(data, (void *)MTL_Q0UCR_OFFSET);\
} while (0)

#define MTL_Q0UCR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0UCR_OFFSET);\
} while (0)


#define  MTL_Q0UCR_MASK_12 (ULONG)(0xfffff)


#define MTL_Q0UCR_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_Q0UCR_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_Q0UCR_UFCNTOVF_RD(data) do {\
	MTL_Q0UCR_RD(data);\
	data = ((data >> 11) & MTL_Q0UCR_UFCNTOVF_MASK);\
} while (0)


#define MTL_Q0UCR_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_Q0UCR_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_Q0UCR_UFPKTCNT_WR(data) do {\
	ULONG v;\
	MTL_Q0UCR_RD(v);\
	v = (v & (MTL_Q0UCR_RES_WR_MASK_12))\
	|(((0) & (MTL_Q0UCR_MASK_12))<<12);\
	v = ((v & MTL_Q0UCR_UFPKTCNT_WR_MASK)\
	|((data & MTL_Q0UCR_UFPKTCNT_MASK)<<0));\
	MTL_Q0UCR_WR(v);\
} while (0)

#define MTL_Q0UCR_UFPKTCNT_RD(data) do {\
	MTL_Q0UCR_RD(data);\
	data = ((data >> 0) & MTL_Q0UCR_UFPKTCNT_MASK);\
} while (0)

#define MTL_Q0TOMR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xd00))

#define MTL_Q0TOMR_WR(data) do {\
	iowrite32(data, (void *)MTL_Q0TOMR_OFFSET);\
} while (0)

#define MTL_Q0TOMR_RD(data) do {\
	(data) = ioread32((void *)MTL_Q0TOMR_OFFSET);\
} while (0)


#define  MTL_Q0TOMR_MASK_26 (ULONG)(0x3f)


#define MTL_Q0TOMR_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define  MTL_Q0TOMR_MASK_7 (ULONG)(0x1ff)


#define MTL_Q0TOMR_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define MTL_Q0TOMR_TQS_MASK (ULONG)(0x3ff)


#define MTL_Q0TOMR_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_Q0TOMR_TQS_WR(data) do {\
	ULONG v;\
	MTL_Q0TOMR_RD(v);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_Q0TOMR_MASK_26))<<26);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_Q0TOMR_MASK_7))<<7);\
	v = ((v & MTL_Q0TOMR_TQS_WR_MASK)\
	|((data & MTL_Q0TOMR_TQS_MASK)<<16));\
	MTL_Q0TOMR_WR(v);\
} while (0)

#define MTL_Q0TOMR_TQS_RD(data) do {\
	MTL_Q0TOMR_RD(data);\
	data = ((data >> 16) & MTL_Q0TOMR_TQS_MASK);\
} while (0)


#define MTL_Q0TOMR_TTC_MASK (ULONG)(0x7)


#define MTL_Q0TOMR_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_Q0TOMR_TTC_WR(data) do {\
	ULONG v;\
	MTL_Q0TOMR_RD(v);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_Q0TOMR_MASK_26))<<26);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_Q0TOMR_MASK_7))<<7);\
	v = ((v & MTL_Q0TOMR_TTC_WR_MASK)\
	|((data & MTL_Q0TOMR_TTC_MASK)<<4));\
	MTL_Q0TOMR_WR(v);\
} while (0)

#define MTL_Q0TOMR_TTC_RD(data) do {\
	MTL_Q0TOMR_RD(data);\
	data = ((data >> 4) & MTL_Q0TOMR_TTC_MASK);\
} while (0)


#define MTL_Q0TOMR_TXQEN_MASK (ULONG)(0x3)


#define MTL_Q0TOMR_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_Q0TOMR_TXQEN_WR(data) do {\
	ULONG v;\
	MTL_Q0TOMR_RD(v);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_Q0TOMR_MASK_26))<<26);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_Q0TOMR_MASK_7))<<7);\
	v = ((v & MTL_Q0TOMR_TXQEN_WR_MASK)\
	|((data & MTL_Q0TOMR_TXQEN_MASK)<<2));\
	MTL_Q0TOMR_WR(v);\
} while (0)

#define MTL_Q0TOMR_TXQEN_RD(data) do {\
	MTL_Q0TOMR_RD(data);\
	data = ((data >> 2) & MTL_Q0TOMR_TXQEN_MASK);\
} while (0)


#define MTL_Q0TOMR_TSF_MASK (ULONG)(0x1)


#define MTL_Q0TOMR_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_Q0TOMR_TSF_WR(data) do {\
	ULONG v;\
	MTL_Q0TOMR_RD(v);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_Q0TOMR_MASK_26))<<26);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_Q0TOMR_MASK_7))<<7);\
	v = ((v & MTL_Q0TOMR_TSF_WR_MASK)\
	|((data & MTL_Q0TOMR_TSF_MASK)<<1));\
	MTL_Q0TOMR_WR(v);\
} while (0)

#define MTL_Q0TOMR_TSF_RD(data) do {\
	MTL_Q0TOMR_RD(data);\
	data = ((data >> 1) & MTL_Q0TOMR_TSF_MASK);\
} while (0)


#define MTL_Q0TOMR_FTQ_MASK (ULONG)(0x1)


#define MTL_Q0TOMR_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_Q0TOMR_FTQ_WR(data) do {\
	ULONG v;\
	MTL_Q0TOMR_RD(v);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_Q0TOMR_MASK_26))<<26);\
	v = (v & (MTL_Q0TOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_Q0TOMR_MASK_7))<<7);\
	v = ((v & MTL_Q0TOMR_FTQ_WR_MASK)\
	|((data & MTL_Q0TOMR_FTQ_MASK)<<0));\
	MTL_Q0TOMR_WR(v);\
} while (0)

#define MTL_Q0TOMR_FTQ_RD(data) do {\
	MTL_Q0TOMR_RD(data);\
	data = ((data >> 0) & MTL_Q0TOMR_FTQ_MASK);\
} while (0)

#define MTL_RQDCM1R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc34))

#define MTL_RQDCM1R_WR(data) do {\
	iowrite32(data, (void *)MTL_RQDCM1R_OFFSET);\
} while (0)

#define MTL_RQDCM1R_RD(data) do {\
	(data) = ioread32((void *)MTL_RQDCM1R_OFFSET);\
} while (0)


#define  MTL_RQDCM1R_MASK_29 (ULONG)(0x7)


#define MTL_RQDCM1R_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define  MTL_RQDCM1R_MASK_27 (ULONG)(0x1)


#define MTL_RQDCM1R_RES_WR_MASK_27 (ULONG)(0xf7ffffff)


#define  MTL_RQDCM1R_MASK_21 (ULONG)(0x7)


#define MTL_RQDCM1R_RES_WR_MASK_21 (ULONG)(0xff1fffff)


#define  MTL_RQDCM1R_MASK_19 (ULONG)(0x1)


#define MTL_RQDCM1R_RES_WR_MASK_19 (ULONG)(0xfff7ffff)


#define  MTL_RQDCM1R_MASK_13 (ULONG)(0x7)


#define MTL_RQDCM1R_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  MTL_RQDCM1R_MASK_11 (ULONG)(0x1)


#define MTL_RQDCM1R_RES_WR_MASK_11 (ULONG)(0xfffff7ff)


#define  MTL_RQDCM1R_MASK_5 (ULONG)(0x7)


#define MTL_RQDCM1R_RES_WR_MASK_5 (ULONG)(0xffffff1f)


#define  MTL_RQDCM1R_MASK_3 (ULONG)(0x1)


#define MTL_RQDCM1R_RES_WR_MASK_3 (ULONG)(0xfffffff7)


#define MTL_RQDCM1R_RXQ7DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM1R_RXQ7DADMACH_WR_MASK (ULONG)(0xefffffff)

#define MTL_RQDCM1R_RXQ7DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ7DADMACH_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ7DADMACH_MASK)<<28));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ7DADMACH_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 28) & MTL_RQDCM1R_RXQ7DADMACH_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ72DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM1R_RXQ72DMA_WR_MASK (ULONG)(0xf8ffffff)

#define MTL_RQDCM1R_RXQ72DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ72DMA_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ72DMA_MASK)<<24));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ72DMA_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 24) & MTL_RQDCM1R_RXQ72DMA_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ6DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM1R_RXQ6DADMACH_WR_MASK (ULONG)(0xffefffff)

#define MTL_RQDCM1R_RXQ6DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ6DADMACH_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ6DADMACH_MASK)<<20));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ6DADMACH_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 20) & MTL_RQDCM1R_RXQ6DADMACH_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ26DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM1R_RXQ26DMA_WR_MASK (ULONG)(0xfff8ffff)

#define MTL_RQDCM1R_RXQ26DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ26DMA_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ26DMA_MASK)<<16));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ26DMA_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 16) & MTL_RQDCM1R_RXQ26DMA_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ5DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM1R_RXQ5DADMACH_WR_MASK (ULONG)(0xffffefff)

#define MTL_RQDCM1R_RXQ5DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ5DADMACH_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ5DADMACH_MASK)<<12));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ5DADMACH_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 12) & MTL_RQDCM1R_RXQ5DADMACH_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ25DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM1R_RXQ25DMA_WR_MASK (ULONG)(0xfffff8ff)

#define MTL_RQDCM1R_RXQ25DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ25DMA_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ25DMA_MASK)<<8));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ25DMA_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 8) & MTL_RQDCM1R_RXQ25DMA_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ4DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM1R_RXQ4DADMACH_WR_MASK (ULONG)(0xffffffef)

#define MTL_RQDCM1R_RXQ4DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ4DADMACH_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ4DADMACH_MASK)<<4));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ4DADMACH_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 4) & MTL_RQDCM1R_RXQ4DADMACH_MASK);\
} while (0)


#define MTL_RQDCM1R_RXQ42DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM1R_RXQ42DMA_WR_MASK (ULONG)(0xfffffff8)

#define MTL_RQDCM1R_RXQ42DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM1R_RD(v);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM1R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM1R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM1R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM1R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM1R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM1R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM1R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM1R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM1R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM1R_RXQ42DMA_WR_MASK)\
	|((data & MTL_RQDCM1R_RXQ42DMA_MASK)<<0));\
	MTL_RQDCM1R_WR(v);\
} while (0)

#define MTL_RQDCM1R_RXQ42DMA_RD(data) do {\
	MTL_RQDCM1R_RD(data);\
	data = ((data >> 0) & MTL_RQDCM1R_RXQ42DMA_MASK);\
} while (0)

#define MTL_RQDCM0R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc30))

#define MTL_RQDCM0R_WR(data) do {\
	iowrite32(data, (void *)MTL_RQDCM0R_OFFSET);\
} while (0)

#define MTL_RQDCM0R_RD(data) do {\
	(data) = ioread32((void *)MTL_RQDCM0R_OFFSET);\
} while (0)


#define  MTL_RQDCM0R_MASK_29 (ULONG)(0x7)


#define MTL_RQDCM0R_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define  MTL_RQDCM0R_MASK_27 (ULONG)(0x1)


#define MTL_RQDCM0R_RES_WR_MASK_27 (ULONG)(0xf7ffffff)


#define  MTL_RQDCM0R_MASK_21 (ULONG)(0x7)


#define MTL_RQDCM0R_RES_WR_MASK_21 (ULONG)(0xff1fffff)


#define  MTL_RQDCM0R_MASK_19 (ULONG)(0x1)


#define MTL_RQDCM0R_RES_WR_MASK_19 (ULONG)(0xfff7ffff)


#define  MTL_RQDCM0R_MASK_13 (ULONG)(0x7)


#define MTL_RQDCM0R_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  MTL_RQDCM0R_MASK_11 (ULONG)(0x1)


#define MTL_RQDCM0R_RES_WR_MASK_11 (ULONG)(0xfffff7ff)


#define  MTL_RQDCM0R_MASK_5 (ULONG)(0x7)


#define MTL_RQDCM0R_RES_WR_MASK_5 (ULONG)(0xffffff1f)


#define  MTL_RQDCM0R_MASK_3 (ULONG)(0x1)


#define MTL_RQDCM0R_RES_WR_MASK_3 (ULONG)(0xfffffff7)


#define MTL_RQDCM0R_RXQ3DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM0R_RXQ3DADMACH_WR_MASK (ULONG)(0xefffffff)

#define MTL_RQDCM0R_RXQ3DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ3DADMACH_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ3DADMACH_MASK)<<28));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ3DADMACH_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 28) & MTL_RQDCM0R_RXQ3DADMACH_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ32DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM0R_RXQ32DMA_WR_MASK (ULONG)(0xf8ffffff)

#define MTL_RQDCM0R_RXQ32DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ32DMA_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ32DMA_MASK)<<24));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ32DMA_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 24) & MTL_RQDCM0R_RXQ32DMA_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ2DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM0R_RXQ2DADMACH_WR_MASK (ULONG)(0xffefffff)

#define MTL_RQDCM0R_RXQ2DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ2DADMACH_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ2DADMACH_MASK)<<20));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ2DADMACH_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 20) & MTL_RQDCM0R_RXQ2DADMACH_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ22DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM0R_RXQ22DMA_WR_MASK (ULONG)(0xfff8ffff)

#define MTL_RQDCM0R_RXQ22DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ22DMA_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ22DMA_MASK)<<16));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ22DMA_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 16) & MTL_RQDCM0R_RXQ22DMA_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ1DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM0R_RXQ1DADMACH_WR_MASK (ULONG)(0xffffefff)

#define MTL_RQDCM0R_RXQ1DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ1DADMACH_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ1DADMACH_MASK)<<12));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ1DADMACH_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 12) & MTL_RQDCM0R_RXQ1DADMACH_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ12DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM0R_RXQ12DMA_WR_MASK (ULONG)(0xfffff8ff)

#define MTL_RQDCM0R_RXQ12DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ12DMA_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ12DMA_MASK)<<8));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ12DMA_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 8) & MTL_RQDCM0R_RXQ12DMA_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ0DADMACH_MASK (ULONG)(0x1)


#define MTL_RQDCM0R_RXQ0DADMACH_WR_MASK (ULONG)(0xffffffef)

#define MTL_RQDCM0R_RXQ0DADMACH_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ0DADMACH_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ0DADMACH_MASK)<<4));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ0DADMACH_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 4) & MTL_RQDCM0R_RXQ0DADMACH_MASK);\
} while (0)


#define MTL_RQDCM0R_RXQ02DMA_MASK (ULONG)(0x7)


#define MTL_RQDCM0R_RXQ02DMA_WR_MASK (ULONG)(0xfffffff8)

#define MTL_RQDCM0R_RXQ02DMA_WR(data) do {\
	ULONG v;\
	MTL_RQDCM0R_RD(v);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_29))\
	|(((0) & (MTL_RQDCM0R_MASK_29))<<29);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_27))\
	|(((0) & (MTL_RQDCM0R_MASK_27))<<27);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_21))\
	|(((0) & (MTL_RQDCM0R_MASK_21))<<21);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_19))\
	|(((0) & (MTL_RQDCM0R_MASK_19))<<19);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_13))\
	|(((0) & (MTL_RQDCM0R_MASK_13))<<13);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_11))\
	|(((0) & (MTL_RQDCM0R_MASK_11))<<11);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_5))\
	|(((0) & (MTL_RQDCM0R_MASK_5))<<5);\
	v = (v & (MTL_RQDCM0R_RES_WR_MASK_3))\
	|(((0) & (MTL_RQDCM0R_MASK_3))<<3);\
	v = ((v & MTL_RQDCM0R_RXQ02DMA_WR_MASK)\
	|((data & MTL_RQDCM0R_RXQ02DMA_MASK)<<0));\
	MTL_RQDCM0R_WR(v);\
} while (0)

#define MTL_RQDCM0R_RXQ02DMA_RD(data) do {\
	MTL_RQDCM0R_RD(data);\
	data = ((data >> 0) & MTL_RQDCM0R_RXQ02DMA_MASK);\
} while (0)

#define MTL_FDDR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc10))

#define MTL_FDDR_WR(data) do {\
	iowrite32(data, (void *)MTL_FDDR_OFFSET);\
} while (0)

#define MTL_FDDR_RD(data) do {\
	(data) = ioread32((void *)MTL_FDDR_OFFSET);\
} while (0)

#define MTL_FDDR_FDBGDATA_WR(data) do {\
	MTL_FDDR_WR(data);\
} while (0)

#define MTL_FDDR_FDBGDATA_RD(data) do {\
	MTL_FDDR_RD(data);\
} while (0)

#define MTL_FDACS_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc08))

#define MTL_FDACS_WR(data) do {\
	iowrite32(data, (void *)MTL_FDACS_OFFSET);\
} while (0)

#define MTL_FDACS_RD(data) do {\
	(data) = ioread32((void *)MTL_FDACS_OFFSET);\
} while (0)


#define  MTL_FDACS_MASK_16 (ULONG)(0xffff)


#define MTL_FDACS_RES_WR_MASK_16 (ULONG)(0xffff)


#define  MTL_FDACS_MASK_7 (ULONG)(0x1)


#define MTL_FDACS_RES_WR_MASK_7 (ULONG)(0xffffff7f)


#define  MTL_FDACS_MASK_4 (ULONG)(0x1)


#define MTL_FDACS_RES_WR_MASK_4 (ULONG)(0xffffffef)


#define MTL_FDACS_STSE_MASK (ULONG)(0x1)


#define MTL_FDACS_STSE_WR_MASK (ULONG)(0xffff7fff)

#define MTL_FDACS_STSE_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_STSE_WR_MASK)\
	|((data & MTL_FDACS_STSE_MASK)<<15));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_STSE_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 15) & MTL_FDACS_STSE_MASK);\
} while (0)


#define MTL_FDACS_PKTE_MASK (ULONG)(0x1)


#define MTL_FDACS_PKTE_WR_MASK (ULONG)(0xffffbfff)

#define MTL_FDACS_PKTE_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_PKTE_WR_MASK)\
	|((data & MTL_FDACS_PKTE_MASK)<<14));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_PKTE_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 14) & MTL_FDACS_PKTE_MASK);\
} while (0)


#define MTL_FDACS_FIFOSEL_MASK (ULONG)(0x3)


#define MTL_FDACS_FIFOSEL_WR_MASK (ULONG)(0xffffcfff)

#define MTL_FDACS_FIFOSEL_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_FIFOSEL_WR_MASK)\
	|((data & MTL_FDACS_FIFOSEL_MASK)<<12));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_FIFOSEL_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 12) & MTL_FDACS_FIFOSEL_MASK);\
} while (0)


#define MTL_FDACS_FIFOWREN_MASK (ULONG)(0x1)


#define MTL_FDACS_FIFOWREN_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_FDACS_FIFOWREN_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_FIFOWREN_WR_MASK)\
	|((data & MTL_FDACS_FIFOWREN_MASK)<<11));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_FIFOWREN_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 11) & MTL_FDACS_FIFOWREN_MASK);\
} while (0)


#define MTL_FDACS_FIFORDEN_MASK (ULONG)(0x1)


#define MTL_FDACS_FIFORDEN_WR_MASK (ULONG)(0xfffffbff)

#define MTL_FDACS_FIFORDEN_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_FIFORDEN_WR_MASK)\
	|((data & MTL_FDACS_FIFORDEN_MASK)<<10));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_FIFORDEN_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 10) & MTL_FDACS_FIFORDEN_MASK);\
} while (0)


#define MTL_FDACS_RSTSEL_MASK (ULONG)(0x1)


#define MTL_FDACS_RSTSEL_WR_MASK (ULONG)(0xfffffdff)

#define MTL_FDACS_RSTSEL_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_RSTSEL_WR_MASK)\
	|((data & MTL_FDACS_RSTSEL_MASK)<<9));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_RSTSEL_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 9) & MTL_FDACS_RSTSEL_MASK);\
} while (0)


#define MTL_FDACS_RSTALL_MASK (ULONG)(0x1)


#define MTL_FDACS_RSTALL_WR_MASK (ULONG)(0xfffffeff)

#define MTL_FDACS_RSTALL_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_RSTALL_WR_MASK)\
	|((data & MTL_FDACS_RSTALL_MASK)<<8));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_RSTALL_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 8) & MTL_FDACS_RSTALL_MASK);\
} while (0)


#define MTL_FDACS_PKTSTATE_MASK (ULONG)(0x3)


#define MTL_FDACS_PKTSTATE_WR_MASK (ULONG)(0xffffff9f)

#define MTL_FDACS_PKTSTATE_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_PKTSTATE_WR_MASK)\
	|((data & MTL_FDACS_PKTSTATE_MASK)<<5));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_PKTSTATE_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 5) & MTL_FDACS_PKTSTATE_MASK);\
} while (0)


#define MTL_FDACS_BYTEEN_MASK (ULONG)(0x3)


#define MTL_FDACS_BYTEEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_FDACS_BYTEEN_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_BYTEEN_WR_MASK)\
	|((data & MTL_FDACS_BYTEEN_MASK)<<2));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_BYTEEN_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 2) & MTL_FDACS_BYTEEN_MASK);\
} while (0)


#define MTL_FDACS_DEGMOD_MASK (ULONG)(0x1)


#define MTL_FDACS_DEGMOD_WR_MASK (ULONG)(0xfffffffd)

#define MTL_FDACS_DEGMOD_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_DEGMOD_WR_MASK)\
	|((data & MTL_FDACS_DEGMOD_MASK)<<1));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_DEGMOD_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 1) & MTL_FDACS_DEGMOD_MASK);\
} while (0)


#define MTL_FDACS_FDBGEN_MASK (ULONG)(0x1)


#define MTL_FDACS_FDBGEN_WR_MASK (ULONG)(0xfffffffe)

#define MTL_FDACS_FDBGEN_WR(data) do {\
	ULONG v;\
	MTL_FDACS_RD(v);\
	v = (v & (MTL_FDACS_RES_WR_MASK_16))\
	|(((0) & (MTL_FDACS_MASK_16))<<16);\
	v = (v & (MTL_FDACS_RES_WR_MASK_7))\
	|(((0) & (MTL_FDACS_MASK_7))<<7);\
	v = (v & (MTL_FDACS_RES_WR_MASK_4))\
	|(((0) & (MTL_FDACS_MASK_4))<<4);\
	v = ((v & MTL_FDACS_FDBGEN_WR_MASK)\
	|((data & MTL_FDACS_FDBGEN_MASK)<<0));\
	MTL_FDACS_WR(v);\
} while (0)

#define MTL_FDACS_FDBGEN_RD(data) do {\
	MTL_FDACS_RD(data);\
	data = ((data >> 0) & MTL_FDACS_FDBGEN_MASK);\
} while (0)

#define MTL_OMR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc00))

#define MTL_OMR_WR(data) do {\
	iowrite32(data, (void *)MTL_OMR_OFFSET);\
} while (0)

#define MTL_OMR_RD(data) do {\
	(data) = ioread32((void *)MTL_OMR_OFFSET);\
} while (0)


#define  MTL_OMR_MASK_7 (ULONG)(0x1ffffff)


#define MTL_OMR_RES_WR_MASK_7 (ULONG)(0x7f)


#define  MTL_OMR_MASK_0 (ULONG)(0x1)


#define MTL_OMR_RES_WR_MASK_0 (ULONG)(0xfffffffe)


#define MTL_OMR_SCHALG_MASK (ULONG)(0x3)


#define MTL_OMR_SCHALG_WR_MASK (ULONG)(0xffffff9f)

#define MTL_OMR_SCHALG_WR(data) do {\
	ULONG v;\
	MTL_OMR_RD(v);\
	v = (v & (MTL_OMR_RES_WR_MASK_7))\
	|(((0) & (MTL_OMR_MASK_7))<<7);\
	v = (v & (MTL_OMR_RES_WR_MASK_0))\
	|(((0) & (MTL_OMR_MASK_0))<<0);\
	v = ((v & MTL_OMR_SCHALG_WR_MASK)\
	|((data & MTL_OMR_SCHALG_MASK)<<5));\
	MTL_OMR_WR(v);\
} while (0)

#define MTL_OMR_SCHALG_RD(data) do {\
	MTL_OMR_RD(data);\
	data = ((data >> 5) & MTL_OMR_SCHALG_MASK);\
} while (0)


#define MTL_OMR_RAA_MASK (ULONG)(0x7)


#define MTL_OMR_RAA_WR_MASK (ULONG)(0xffffffe3)

#define MTL_OMR_RAA_WR(data) do {\
	ULONG v;\
	MTL_OMR_RD(v);\
	v = (v & (MTL_OMR_RES_WR_MASK_7))\
	|(((0) & (MTL_OMR_MASK_7))<<7);\
	v = (v & (MTL_OMR_RES_WR_MASK_0))\
	|(((0) & (MTL_OMR_MASK_0))<<0);\
	v = ((v & MTL_OMR_RAA_WR_MASK)\
	|((data & MTL_OMR_RAA_MASK)<<2));\
	MTL_OMR_WR(v);\
} while (0)

#define MTL_OMR_RAA_RD(data) do {\
	MTL_OMR_RD(data);\
	data = ((data >> 2) & MTL_OMR_RAA_MASK);\
} while (0)


#define MTL_OMR_DTXSTS_MASK (ULONG)(0x1)


#define MTL_OMR_DTXSTS_WR_MASK (ULONG)(0xfffffffd)

#define MTL_OMR_DTXSTS_WR(data) do {\
	ULONG v;\
	MTL_OMR_RD(v);\
	v = (v & (MTL_OMR_RES_WR_MASK_7))\
	|(((0) & (MTL_OMR_MASK_7))<<7);\
	v = (v & (MTL_OMR_RES_WR_MASK_0))\
	|(((0) & (MTL_OMR_MASK_0))<<0);\
	v = ((v & MTL_OMR_DTXSTS_WR_MASK)\
	|((data & MTL_OMR_DTXSTS_MASK)<<1));\
	MTL_OMR_WR(v);\
} while (0)

#define MTL_OMR_DTXSTS_RD(data) do {\
	MTL_OMR_RD(data);\
	data = ((data >> 1) & MTL_OMR_DTXSTS_MASK);\
} while (0)

#define MAC_RQC3R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xac))

#define MAC_RQC3R_WR(data) do {\
	iowrite32(data, (void *)MAC_RQC3R_OFFSET);\
} while (0)

#define MAC_RQC3R_RD(data) do {\
	(data) = ioread32((void *)MAC_RQC3R_OFFSET);\
} while (0)


#define MAC_RQC3R_PSRQ7_MASK (ULONG)(0xff)


#define MAC_RQC3R_PSRQ7_WR_MASK (ULONG)(0xffffff)

#define MAC_RQC3R_PSRQ7_WR(data) do {\
	ULONG v;\
	MAC_RQC3R_RD(v);\
	v = ((v & MAC_RQC3R_PSRQ7_WR_MASK)\
	|((data & MAC_RQC3R_PSRQ7_MASK)<<24));\
	MAC_RQC3R_WR(v);\
} while (0)

#define MAC_RQC3R_PSRQ7_RD(data) do {\
	MAC_RQC3R_RD(data);\
	data = ((data >> 24) & MAC_RQC3R_PSRQ7_MASK);\
} while (0)


#define MAC_RQC3R_PSRQ6_MASK (ULONG)(0xff)


#define MAC_RQC3R_PSRQ6_WR_MASK (ULONG)(0xff00ffff)

#define MAC_RQC3R_PSRQ6_WR(data) do {\
	ULONG v;\
	MAC_RQC3R_RD(v);\
	v = ((v & MAC_RQC3R_PSRQ6_WR_MASK)\
	|((data & MAC_RQC3R_PSRQ6_MASK)<<16));\
	MAC_RQC3R_WR(v);\
} while (0)

#define MAC_RQC3R_PSRQ6_RD(data) do {\
	MAC_RQC3R_RD(data);\
	data = ((data >> 16) & MAC_RQC3R_PSRQ6_MASK);\
} while (0)


#define MAC_RQC3R_PSRQ5_MASK (ULONG)(0xff)


#define MAC_RQC3R_PSRQ5_WR_MASK (ULONG)(0xffff00ff)

#define MAC_RQC3R_PSRQ5_WR(data) do {\
	ULONG v;\
	MAC_RQC3R_RD(v);\
	v = ((v & MAC_RQC3R_PSRQ5_WR_MASK)\
	|((data & MAC_RQC3R_PSRQ5_MASK)<<8));\
	MAC_RQC3R_WR(v);\
} while (0)

#define MAC_RQC3R_PSRQ5_RD(data) do {\
	MAC_RQC3R_RD(data);\
	data = ((data >> 8) & MAC_RQC3R_PSRQ5_MASK);\
} while (0)


#define MAC_RQC3R_PSRQ4_MASK (ULONG)(0xff)


#define MAC_RQC3R_PSRQ4_WR_MASK (ULONG)(0xffffff00)

#define MAC_RQC3R_PSRQ4_WR(data) do {\
	ULONG v;\
	MAC_RQC3R_RD(v);\
	v = ((v & MAC_RQC3R_PSRQ4_WR_MASK)\
	|((data & MAC_RQC3R_PSRQ4_MASK)<<0));\
	MAC_RQC3R_WR(v);\
} while (0)

#define MAC_RQC3R_PSRQ4_RD(data) do {\
	MAC_RQC3R_RD(data);\
	data = ((data >> 0) & MAC_RQC3R_PSRQ4_MASK);\
} while (0)

#define MAC_RQC2R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa8))

#define MAC_RQC2R_WR(data) do {\
	iowrite32(data, (void *)MAC_RQC2R_OFFSET);\
} while (0)

#define MAC_RQC2R_RD(data) do {\
	(data) = ioread32((void *)MAC_RQC2R_OFFSET);\
} while (0)


#define MAC_RQC2R_PSRQ3_MASK (ULONG)(0xff)


#define MAC_RQC2R_PSRQ3_WR_MASK (ULONG)(0xffffff)

#define MAC_RQC2R_PSRQ3_WR(data) do {\
	ULONG v;\
	MAC_RQC2R_RD(v);\
	v = ((v & MAC_RQC2R_PSRQ3_WR_MASK)\
	|((data & MAC_RQC2R_PSRQ3_MASK)<<24));\
	MAC_RQC2R_WR(v);\
} while (0)

#define MAC_RQC2R_PSRQ3_RD(data) do {\
	MAC_RQC2R_RD(data);\
	data = ((data >> 24) & MAC_RQC2R_PSRQ3_MASK);\
} while (0)


#define MAC_RQC2R_PSRQ2_MASK (ULONG)(0xff)


#define MAC_RQC2R_PSRQ2_WR_MASK (ULONG)(0xff00ffff)

#define MAC_RQC2R_PSRQ2_WR(data) do {\
	ULONG v;\
	MAC_RQC2R_RD(v);\
	v = ((v & MAC_RQC2R_PSRQ2_WR_MASK)\
	|((data & MAC_RQC2R_PSRQ2_MASK)<<16));\
	MAC_RQC2R_WR(v);\
} while (0)

#define MAC_RQC2R_PSRQ2_RD(data) do {\
	MAC_RQC2R_RD(data);\
	data = ((data >> 16) & MAC_RQC2R_PSRQ2_MASK);\
} while (0)


#define MAC_RQC2R_PSRQ1_MASK (ULONG)(0xff)


#define MAC_RQC2R_PSRQ1_WR_MASK (ULONG)(0xffff00ff)

#define MAC_RQC2R_PSRQ1_WR(data) do {\
	ULONG v;\
	MAC_RQC2R_RD(v);\
	v = ((v & MAC_RQC2R_PSRQ1_WR_MASK)\
	|((data & MAC_RQC2R_PSRQ1_MASK)<<8));\
	MAC_RQC2R_WR(v);\
} while (0)

#define MAC_RQC2R_PSRQ1_RD(data) do {\
	MAC_RQC2R_RD(data);\
	data = ((data >> 8) & MAC_RQC2R_PSRQ1_MASK);\
} while (0)


#define MAC_RQC2R_PSRQ0_MASK (ULONG)(0xff)


#define MAC_RQC2R_PSRQ0_WR_MASK (ULONG)(0xffffff00)

#define MAC_RQC2R_PSRQ0_WR(data) do {\
	ULONG v;\
	MAC_RQC2R_RD(v);\
	v = ((v & MAC_RQC2R_PSRQ0_WR_MASK)\
	|((data & MAC_RQC2R_PSRQ0_MASK)<<0));\
	MAC_RQC2R_WR(v);\
} while (0)

#define MAC_RQC2R_PSRQ0_RD(data) do {\
	MAC_RQC2R_RD(data);\
	data = ((data >> 0) & MAC_RQC2R_PSRQ0_MASK);\
} while (0)

#define MAC_RQC1R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa4))

#define MAC_RQC1R_WR(data) do {\
	iowrite32(data, (void *)MAC_RQC1R_OFFSET);\
} while (0)

#define MAC_RQC1R_RD(data) do {\
	(data) = ioread32((void *)MAC_RQC1R_OFFSET);\
} while (0)


#define  MAC_RQC1R_MASK_11 (ULONG)(0x1fffff)


#define MAC_RQC1R_RES_WR_MASK_11 (ULONG)(0x7ff)


#define  MAC_RQC1R_MASK_7 (ULONG)(0x1)


#define MAC_RQC1R_RES_WR_MASK_7 (ULONG)(0xffffff7f)


#define  MAC_RQC1R_MASK_3 (ULONG)(0x1)


#define MAC_RQC1R_RES_WR_MASK_3 (ULONG)(0xfffffff7)


#define MAC_RQC1R_DCBCPQ_MASK (ULONG)(0x7)


#define MAC_RQC1R_DCBCPQ_WR_MASK (ULONG)(0xfffff8ff)

#define MAC_RQC1R_DCBCPQ_WR(data) do {\
	ULONG v;\
	MAC_RQC1R_RD(v);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_11))\
	|(((0) & (MAC_RQC1R_MASK_11))<<11);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_7))\
	|(((0) & (MAC_RQC1R_MASK_7))<<7);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_3))\
	|(((0) & (MAC_RQC1R_MASK_3))<<3);\
	v = ((v & MAC_RQC1R_DCBCPQ_WR_MASK)\
	|((data & MAC_RQC1R_DCBCPQ_MASK)<<8));\
	MAC_RQC1R_WR(v);\
} while (0)

#define MAC_RQC1R_DCBCPQ_RD(data) do {\
	MAC_RQC1R_RD(data);\
	data = ((data >> 8) & MAC_RQC1R_DCBCPQ_MASK);\
} while (0)


#define MAC_RQC1R_AVPTPQ_MASK (ULONG)(0x7)


#define MAC_RQC1R_AVPTPQ_WR_MASK (ULONG)(0xffffff8f)

#define MAC_RQC1R_AVPTPQ_WR(data) do {\
	ULONG v;\
	MAC_RQC1R_RD(v);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_11))\
	|(((0) & (MAC_RQC1R_MASK_11))<<11);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_7))\
	|(((0) & (MAC_RQC1R_MASK_7))<<7);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_3))\
	|(((0) & (MAC_RQC1R_MASK_3))<<3);\
	v = ((v & MAC_RQC1R_AVPTPQ_WR_MASK)\
	|((data & MAC_RQC1R_AVPTPQ_MASK)<<4));\
	MAC_RQC1R_WR(v);\
} while (0)

#define MAC_RQC1R_AVPTPQ_RD(data) do {\
	MAC_RQC1R_RD(data);\
	data = ((data >> 4) & MAC_RQC1R_AVPTPQ_MASK);\
} while (0)


#define MAC_RQC1R_AVUCPQ_MASK (ULONG)(0x7)


#define MAC_RQC1R_AVUCPQ_WR_MASK (ULONG)(0xfffffff8)

#define MAC_RQC1R_AVUCPQ_WR(data) do {\
	ULONG v;\
	MAC_RQC1R_RD(v);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_11))\
	|(((0) & (MAC_RQC1R_MASK_11))<<11);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_7))\
	|(((0) & (MAC_RQC1R_MASK_7))<<7);\
	v = (v & (MAC_RQC1R_RES_WR_MASK_3))\
	|(((0) & (MAC_RQC1R_MASK_3))<<3);\
	v = ((v & MAC_RQC1R_AVUCPQ_WR_MASK)\
	|((data & MAC_RQC1R_AVUCPQ_MASK)<<0));\
	MAC_RQC1R_WR(v);\
} while (0)

#define MAC_RQC1R_AVUCPQ_RD(data) do {\
	MAC_RQC1R_RD(data);\
	data = ((data >> 0) & MAC_RQC1R_AVUCPQ_MASK);\
} while (0)

#define MAC_RQC0R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xa0))

#define MAC_RQC0R_WR(data) do {\
	iowrite32(data, (void *)MAC_RQC0R_OFFSET);\
} while (0)

#define MAC_RQC0R_RD(data) do {\
	(data) = ioread32((void *)MAC_RQC0R_OFFSET);\
} while (0)


#define  MAC_RQC0R_MASK_16 (ULONG)(0xffff)


#define MAC_RQC0R_RES_WR_MASK_16 (ULONG)(0xffff)


#define MAC_RQC0R_RXQEN7_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN7_WR_MASK (ULONG)(0xffff3fff)

#define MAC_RQC0R_RXQEN7_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN7_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN7_MASK)<<14));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN7_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 14) & MAC_RQC0R_RXQEN7_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN6_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN6_WR_MASK (ULONG)(0xffffcfff)

#define MAC_RQC0R_RXQEN6_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN6_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN6_MASK)<<12));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN6_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 12) & MAC_RQC0R_RXQEN6_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN5_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN5_WR_MASK (ULONG)(0xfffff3ff)

#define MAC_RQC0R_RXQEN5_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN5_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN5_MASK)<<10));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN5_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 10) & MAC_RQC0R_RXQEN5_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN4_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN4_WR_MASK (ULONG)(0xfffffcff)

#define MAC_RQC0R_RXQEN4_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN4_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN4_MASK)<<8));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN4_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 8) & MAC_RQC0R_RXQEN4_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN3_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN3_WR_MASK (ULONG)(0xffffff3f)

#define MAC_RQC0R_RXQEN3_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN3_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN3_MASK)<<6));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN3_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 6) & MAC_RQC0R_RXQEN3_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN2_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN2_WR_MASK (ULONG)(0xffffffcf)

#define MAC_RQC0R_RXQEN2_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN2_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN2_MASK)<<4));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN2_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 4) & MAC_RQC0R_RXQEN2_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN1_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN1_WR_MASK (ULONG)(0xfffffff3)

#define MAC_RQC0R_RXQEN1_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN1_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN1_MASK)<<2));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN1_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 2) & MAC_RQC0R_RXQEN1_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN0_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN0_WR_MASK (ULONG)(0xfffffffc)

#define MAC_RQC0R_RXQEN0_WR(data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN0_WR_MASK)\
	|((data & MAC_RQC0R_RXQEN0_MASK)<<0));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN0_RD(data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> 0) & MAC_RQC0R_RXQEN0_MASK);\
} while (0)


#define MAC_RQC0R_RXQEN_MASK (ULONG)(0x3)


#define MAC_RQC0R_RXQEN_WR_MASK(i)  (ULONG)(~((~(~0 << (2))) << (0 + (i * 2))))

#define MAC_RQC0R_RXQEN_WR(i, data) do {\
	ULONG v;\
	MAC_RQC0R_RD(v);\
	v = (v & (MAC_RQC0R_RES_WR_MASK_16))\
	|(((0) & (MAC_RQC0R_MASK_16))<<16);\
	v = ((v & MAC_RQC0R_RXQEN_WR_MASK(i))\
	|((data & MAC_RQC0R_RXQEN_MASK)<<(0 + i*2)));\
	MAC_RQC0R_WR(v);\
} while (0)

#define MAC_RQC0R_RXQEN_RD(i, data) do {\
	MAC_RQC0R_RD(data);\
	data = ((data >> (0 + (i*2))) & MAC_RQC0R_RXQEN_MASK);\
} while (0)

#define MAC_TQPM1R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x9c))

#define MAC_TQPM1R_WR(data) do {\
	iowrite32(data, (void *)MAC_TQPM1R_OFFSET);\
} while (0)

#define MAC_TQPM1R_RD(data) do {\
	(data) = ioread32((void *)MAC_TQPM1R_OFFSET);\
} while (0)


#define MAC_TQPM1R_PSTQ7_MASK (ULONG)(0xff)


#define MAC_TQPM1R_PSTQ7_WR_MASK (ULONG)(0xffffff)

#define MAC_TQPM1R_PSTQ7_WR(data) do {\
	ULONG v;\
	MAC_TQPM1R_RD(v);\
	v = ((v & MAC_TQPM1R_PSTQ7_WR_MASK)\
	|((data & MAC_TQPM1R_PSTQ7_MASK)<<24));\
	MAC_TQPM1R_WR(v);\
} while (0)

#define MAC_TQPM1R_PSTQ7_RD(data) do {\
	MAC_TQPM1R_RD(data);\
	data = ((data >> 24) & MAC_TQPM1R_PSTQ7_MASK);\
} while (0)


#define MAC_TQPM1R_PSTQ6_MASK (ULONG)(0xff)


#define MAC_TQPM1R_PSTQ6_WR_MASK (ULONG)(0xff00ffff)

#define MAC_TQPM1R_PSTQ6_WR(data) do {\
	ULONG v;\
	MAC_TQPM1R_RD(v);\
	v = ((v & MAC_TQPM1R_PSTQ6_WR_MASK)\
	|((data & MAC_TQPM1R_PSTQ6_MASK)<<16));\
	MAC_TQPM1R_WR(v);\
} while (0)

#define MAC_TQPM1R_PSTQ6_RD(data) do {\
	MAC_TQPM1R_RD(data);\
	data = ((data >> 16) & MAC_TQPM1R_PSTQ6_MASK);\
} while (0)


#define MAC_TQPM1R_PSTQ5_MASK (ULONG)(0xff)


#define MAC_TQPM1R_PSTQ5_WR_MASK (ULONG)(0xffff00ff)

#define MAC_TQPM1R_PSTQ5_WR(data) do {\
	ULONG v;\
	MAC_TQPM1R_RD(v);\
	v = ((v & MAC_TQPM1R_PSTQ5_WR_MASK)\
	|((data & MAC_TQPM1R_PSTQ5_MASK)<<8));\
	MAC_TQPM1R_WR(v);\
} while (0)

#define MAC_TQPM1R_PSTQ5_RD(data) do {\
	MAC_TQPM1R_RD(data);\
	data = ((data >> 8) & MAC_TQPM1R_PSTQ5_MASK);\
} while (0)


#define MAC_TQPM1R_PSTQ4_MASK (ULONG)(0xff)


#define MAC_TQPM1R_PSTQ4_WR_MASK (ULONG)(0xffffff00)

#define MAC_TQPM1R_PSTQ4_WR(data) do {\
	ULONG v;\
	MAC_TQPM1R_RD(v);\
	v = ((v & MAC_TQPM1R_PSTQ4_WR_MASK)\
	|((data & MAC_TQPM1R_PSTQ4_MASK)<<0));\
	MAC_TQPM1R_WR(v);\
} while (0)

#define MAC_TQPM1R_PSTQ4_RD(data) do {\
	MAC_TQPM1R_RD(data);\
	data = ((data >> 0) & MAC_TQPM1R_PSTQ4_MASK);\
} while (0)

#define MAC_TQPM0R_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x98))

#define MAC_TQPM0R_WR(data) do {\
	iowrite32(data, (void *)MAC_TQPM0R_OFFSET);\
} while (0)

#define MAC_TQPM0R_RD(data) do {\
	(data) = ioread32((void *)MAC_TQPM0R_OFFSET);\
} while (0)


#define MAC_TQPM0R_PSTQ3_MASK (ULONG)(0xff)


#define MAC_TQPM0R_PSTQ3_WR_MASK (ULONG)(0xffffff)

#define MAC_TQPM0R_PSTQ3_WR(data) do {\
	ULONG v;\
	MAC_TQPM0R_RD(v);\
	v = ((v & MAC_TQPM0R_PSTQ3_WR_MASK)\
	|((data & MAC_TQPM0R_PSTQ3_MASK)<<24));\
	MAC_TQPM0R_WR(v);\
} while (0)

#define MAC_TQPM0R_PSTQ3_RD(data) do {\
	MAC_TQPM0R_RD(data);\
	data = ((data >> 24) & MAC_TQPM0R_PSTQ3_MASK);\
} while (0)


#define MAC_TQPM0R_PSTQ2_MASK (ULONG)(0xff)


#define MAC_TQPM0R_PSTQ2_WR_MASK (ULONG)(0xff00ffff)

#define MAC_TQPM0R_PSTQ2_WR(data) do {\
	ULONG v;\
	MAC_TQPM0R_RD(v);\
	v = ((v & MAC_TQPM0R_PSTQ2_WR_MASK)\
	|((data & MAC_TQPM0R_PSTQ2_MASK)<<16));\
	MAC_TQPM0R_WR(v);\
} while (0)

#define MAC_TQPM0R_PSTQ2_RD(data) do {\
	MAC_TQPM0R_RD(data);\
	data = ((data >> 16) & MAC_TQPM0R_PSTQ2_MASK);\
} while (0)


#define MAC_TQPM0R_PSTQ1_MASK (ULONG)(0xff)


#define MAC_TQPM0R_PSTQ1_WR_MASK (ULONG)(0xffff00ff)

#define MAC_TQPM0R_PSTQ1_WR(data) do {\
	ULONG v;\
	MAC_TQPM0R_RD(v);\
	v = ((v & MAC_TQPM0R_PSTQ1_WR_MASK)\
	|((data & MAC_TQPM0R_PSTQ1_MASK)<<8));\
	MAC_TQPM0R_WR(v);\
} while (0)

#define MAC_TQPM0R_PSTQ1_RD(data) do {\
	MAC_TQPM0R_RD(data);\
	data = ((data >> 8) & MAC_TQPM0R_PSTQ1_MASK);\
} while (0)


#define MAC_TQPM0R_PSTQ0_MASK (ULONG)(0xff)


#define MAC_TQPM0R_PSTQ0_WR_MASK (ULONG)(0xffffff00)

#define MAC_TQPM0R_PSTQ0_WR(data) do {\
	ULONG v;\
	MAC_TQPM0R_RD(v);\
	v = ((v & MAC_TQPM0R_PSTQ0_WR_MASK)\
	|((data & MAC_TQPM0R_PSTQ0_MASK)<<0));\
	MAC_TQPM0R_WR(v);\
} while (0)

#define MAC_TQPM0R_PSTQ0_RD(data) do {\
	MAC_TQPM0R_RD(data);\
	data = ((data >> 0) & MAC_TQPM0R_PSTQ0_MASK);\
} while (0)

#define MAC_RFCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x90))

#define MAC_RFCR_WR(data) do {\
	iowrite32(data, (void *)MAC_RFCR_OFFSET);\
} while (0)

#define MAC_RFCR_RD(data) do {\
	(data) = ioread32((void *)MAC_RFCR_OFFSET);\
} while (0)


#define  MAC_RFCR_MASK_9 (ULONG)(0x7fffff)


#define MAC_RFCR_RES_WR_MASK_9 (ULONG)(0x1ff)


#define  MAC_RFCR_MASK_2 (ULONG)(0x3f)


#define MAC_RFCR_RES_WR_MASK_2 (ULONG)(0xffffff03)


#define MAC_RFCR_PFCE_MASK (ULONG)(0x1)


#define MAC_RFCR_PFCE_WR_MASK (ULONG)(0xfffffeff)

#define MAC_RFCR_PFCE_WR(data) do {\
	ULONG v;\
	MAC_RFCR_RD(v);\
	v = (v & (MAC_RFCR_RES_WR_MASK_9))\
	|(((0) & (MAC_RFCR_MASK_9))<<9);\
	v = (v & (MAC_RFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_RFCR_MASK_2))<<2);\
	v = ((v & MAC_RFCR_PFCE_WR_MASK)\
	|((data & MAC_RFCR_PFCE_MASK)<<8));\
	MAC_RFCR_WR(v);\
} while (0)

#define MAC_RFCR_PFCE_RD(data) do {\
	MAC_RFCR_RD(data);\
	data = ((data >> 8) & MAC_RFCR_PFCE_MASK);\
} while (0)


#define MAC_RFCR_UP_MASK (ULONG)(0x1)


#define MAC_RFCR_UP_WR_MASK (ULONG)(0xfffffffd)

#define MAC_RFCR_UP_WR(data) do {\
	ULONG v;\
	MAC_RFCR_RD(v);\
	v = (v & (MAC_RFCR_RES_WR_MASK_9))\
	|(((0) & (MAC_RFCR_MASK_9))<<9);\
	v = (v & (MAC_RFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_RFCR_MASK_2))<<2);\
	v = ((v & MAC_RFCR_UP_WR_MASK)\
	|((data & MAC_RFCR_UP_MASK)<<1));\
	MAC_RFCR_WR(v);\
} while (0)

#define MAC_RFCR_UP_RD(data) do {\
	MAC_RFCR_RD(data);\
	data = ((data >> 1) & MAC_RFCR_UP_MASK);\
} while (0)


#define MAC_RFCR_RFE_MASK (ULONG)(0x1)


#define MAC_RFCR_RFE_WR_MASK (ULONG)(0xfffffffe)

#define MAC_RFCR_RFE_WR(data) do {\
	ULONG v;\
	MAC_RFCR_RD(v);\
	v = (v & (MAC_RFCR_RES_WR_MASK_9))\
	|(((0) & (MAC_RFCR_MASK_9))<<9);\
	v = (v & (MAC_RFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_RFCR_MASK_2))<<2);\
	v = ((v & MAC_RFCR_RFE_WR_MASK)\
	|((data & MAC_RFCR_RFE_MASK)<<0));\
	MAC_RFCR_WR(v);\
} while (0)

#define MAC_RFCR_RFE_RD(data) do {\
	MAC_RFCR_RD(data);\
	data = ((data >> 0) & MAC_RFCR_RFE_MASK);\
} while (0)

#define MAC_QTFCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x8c))

#define MAC_QTFCR7_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR7_OFFSET);\
} while (0)

#define MAC_QTFCR7_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR7_OFFSET);\
} while (0)


#define  MAC_QTFCR7_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR7_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR7_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR7_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR7_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR7_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR7_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR7_RD(v);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR7_MASK_8))<<8);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR7_MASK_2))<<2);\
	v = ((v & MAC_QTFCR7_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR7_FCB_BPA_MASK)<<0));\
	MAC_QTFCR7_WR(v);\
} while (0)

#define MAC_QTFCR7_FCB_BPA_RD(data) do {\
	MAC_QTFCR7_RD(data);\
	data = ((data >> 0) & MAC_QTFCR7_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR7_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR7_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR7_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR7_RD(v);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR7_MASK_8))<<8);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR7_MASK_2))<<2);\
	v = ((v & MAC_QTFCR7_TFE_WR_MASK)\
	|((data & MAC_QTFCR7_TFE_MASK)<<1));\
	MAC_QTFCR7_WR(v);\
} while (0)

#define MAC_QTFCR7_TFE_RD(data) do {\
	MAC_QTFCR7_RD(data);\
	data = ((data >> 1) & MAC_QTFCR7_TFE_MASK);\
} while (0)


#define MAC_QTFCR7_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR7_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR7_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR7_RD(v);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR7_MASK_8))<<8);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR7_MASK_2))<<2);\
	v = ((v & MAC_QTFCR7_PLT_WR_MASK)\
	|((data & MAC_QTFCR7_PLT_MASK)<<4));\
	MAC_QTFCR7_WR(v);\
} while (0)

#define MAC_QTFCR7_PLT_RD(data) do {\
	MAC_QTFCR7_RD(data);\
	data = ((data >> 4) & MAC_QTFCR7_PLT_MASK);\
} while (0)


#define MAC_QTFCR7_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR7_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR7_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR7_RD(v);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR7_MASK_8))<<8);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR7_MASK_2))<<2);\
	v = ((v & MAC_QTFCR7_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR7_DZPQ_MASK)<<7));\
	MAC_QTFCR7_WR(v);\
} while (0)

#define MAC_QTFCR7_DZPQ_RD(data) do {\
	MAC_QTFCR7_RD(data);\
	data = ((data >> 7) & MAC_QTFCR7_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR7_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR7_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR7_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR7_RD(v);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR7_MASK_8))<<8);\
	v = (v & (MAC_QTFCR7_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR7_MASK_2))<<2);\
	v = ((v & MAC_QTFCR7_PT_WR_MASK)\
	|((data & MAC_QTFCR7_PT_MASK)<<16));\
	MAC_QTFCR7_WR(v);\
} while (0)

#define MAC_QTFCR7_PT_RD(data) do {\
	MAC_QTFCR7_RD(data);\
	data = ((data >> 16) & MAC_QTFCR7_PT_MASK);\
} while (0)

#define MAC_QTFCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x88))

#define MAC_QTFCR6_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR6_OFFSET);\
} while (0)

#define MAC_QTFCR6_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR6_OFFSET);\
} while (0)


#define  MAC_QTFCR6_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR6_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR6_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR6_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR6_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR6_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR6_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR6_RD(v);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR6_MASK_8))<<8);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR6_MASK_2))<<2);\
	v = ((v & MAC_QTFCR6_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR6_FCB_BPA_MASK)<<0));\
	MAC_QTFCR6_WR(v);\
} while (0)

#define MAC_QTFCR6_FCB_BPA_RD(data) do {\
	MAC_QTFCR6_RD(data);\
	data = ((data >> 0) & MAC_QTFCR6_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR6_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR6_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR6_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR6_RD(v);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR6_MASK_8))<<8);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR6_MASK_2))<<2);\
	v = ((v & MAC_QTFCR6_TFE_WR_MASK)\
	|((data & MAC_QTFCR6_TFE_MASK)<<1));\
	MAC_QTFCR6_WR(v);\
} while (0)

#define MAC_QTFCR6_TFE_RD(data) do {\
	MAC_QTFCR6_RD(data);\
	data = ((data >> 1) & MAC_QTFCR6_TFE_MASK);\
} while (0)


#define MAC_QTFCR6_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR6_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR6_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR6_RD(v);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR6_MASK_8))<<8);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR6_MASK_2))<<2);\
	v = ((v & MAC_QTFCR6_PLT_WR_MASK)\
	|((data & MAC_QTFCR6_PLT_MASK)<<4));\
	MAC_QTFCR6_WR(v);\
} while (0)

#define MAC_QTFCR6_PLT_RD(data) do {\
	MAC_QTFCR6_RD(data);\
	data = ((data >> 4) & MAC_QTFCR6_PLT_MASK);\
} while (0)


#define MAC_QTFCR6_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR6_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR6_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR6_RD(v);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR6_MASK_8))<<8);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR6_MASK_2))<<2);\
	v = ((v & MAC_QTFCR6_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR6_DZPQ_MASK)<<7));\
	MAC_QTFCR6_WR(v);\
} while (0)

#define MAC_QTFCR6_DZPQ_RD(data) do {\
	MAC_QTFCR6_RD(data);\
	data = ((data >> 7) & MAC_QTFCR6_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR6_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR6_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR6_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR6_RD(v);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR6_MASK_8))<<8);\
	v = (v & (MAC_QTFCR6_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR6_MASK_2))<<2);\
	v = ((v & MAC_QTFCR6_PT_WR_MASK)\
	|((data & MAC_QTFCR6_PT_MASK)<<16));\
	MAC_QTFCR6_WR(v);\
} while (0)

#define MAC_QTFCR6_PT_RD(data) do {\
	MAC_QTFCR6_RD(data);\
	data = ((data >> 16) & MAC_QTFCR6_PT_MASK);\
} while (0)

#define MAC_QTFCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x84))

#define MAC_QTFCR5_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR5_OFFSET);\
} while (0)

#define MAC_QTFCR5_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR5_OFFSET);\
} while (0)


#define  MAC_QTFCR5_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR5_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR5_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR5_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR5_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR5_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR5_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR5_RD(v);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR5_MASK_8))<<8);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR5_MASK_2))<<2);\
	v = ((v & MAC_QTFCR5_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR5_FCB_BPA_MASK)<<0));\
	MAC_QTFCR5_WR(v);\
} while (0)

#define MAC_QTFCR5_FCB_BPA_RD(data) do {\
	MAC_QTFCR5_RD(data);\
	data = ((data >> 0) & MAC_QTFCR5_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR5_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR5_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR5_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR5_RD(v);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR5_MASK_8))<<8);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR5_MASK_2))<<2);\
	v = ((v & MAC_QTFCR5_TFE_WR_MASK)\
	|((data & MAC_QTFCR5_TFE_MASK)<<1));\
	MAC_QTFCR5_WR(v);\
} while (0)

#define MAC_QTFCR5_TFE_RD(data) do {\
	MAC_QTFCR5_RD(data);\
	data = ((data >> 1) & MAC_QTFCR5_TFE_MASK);\
} while (0)


#define MAC_QTFCR5_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR5_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR5_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR5_RD(v);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR5_MASK_8))<<8);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR5_MASK_2))<<2);\
	v = ((v & MAC_QTFCR5_PLT_WR_MASK)\
	|((data & MAC_QTFCR5_PLT_MASK)<<4));\
	MAC_QTFCR5_WR(v);\
} while (0)

#define MAC_QTFCR5_PLT_RD(data) do {\
	MAC_QTFCR5_RD(data);\
	data = ((data >> 4) & MAC_QTFCR5_PLT_MASK);\
} while (0)


#define MAC_QTFCR5_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR5_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR5_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR5_RD(v);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR5_MASK_8))<<8);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR5_MASK_2))<<2);\
	v = ((v & MAC_QTFCR5_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR5_DZPQ_MASK)<<7));\
	MAC_QTFCR5_WR(v);\
} while (0)

#define MAC_QTFCR5_DZPQ_RD(data) do {\
	MAC_QTFCR5_RD(data);\
	data = ((data >> 7) & MAC_QTFCR5_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR5_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR5_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR5_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR5_RD(v);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR5_MASK_8))<<8);\
	v = (v & (MAC_QTFCR5_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR5_MASK_2))<<2);\
	v = ((v & MAC_QTFCR5_PT_WR_MASK)\
	|((data & MAC_QTFCR5_PT_MASK)<<16));\
	MAC_QTFCR5_WR(v);\
} while (0)

#define MAC_QTFCR5_PT_RD(data) do {\
	MAC_QTFCR5_RD(data);\
	data = ((data >> 16) & MAC_QTFCR5_PT_MASK);\
} while (0)

#define MAC_QTFCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x80))

#define MAC_QTFCR4_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR4_OFFSET);\
} while (0)

#define MAC_QTFCR4_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR4_OFFSET);\
} while (0)


#define  MAC_QTFCR4_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR4_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR4_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR4_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR4_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR4_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR4_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR4_RD(v);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR4_MASK_8))<<8);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR4_MASK_2))<<2);\
	v = ((v & MAC_QTFCR4_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR4_FCB_BPA_MASK)<<0));\
	MAC_QTFCR4_WR(v);\
} while (0)

#define MAC_QTFCR4_FCB_BPA_RD(data) do {\
	MAC_QTFCR4_RD(data);\
	data = ((data >> 0) & MAC_QTFCR4_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR4_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR4_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR4_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR4_RD(v);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR4_MASK_8))<<8);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR4_MASK_2))<<2);\
	v = ((v & MAC_QTFCR4_TFE_WR_MASK)\
	|((data & MAC_QTFCR4_TFE_MASK)<<1));\
	MAC_QTFCR4_WR(v);\
} while (0)

#define MAC_QTFCR4_TFE_RD(data) do {\
	MAC_QTFCR4_RD(data);\
	data = ((data >> 1) & MAC_QTFCR4_TFE_MASK);\
} while (0)


#define MAC_QTFCR4_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR4_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR4_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR4_RD(v);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR4_MASK_8))<<8);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR4_MASK_2))<<2);\
	v = ((v & MAC_QTFCR4_PLT_WR_MASK)\
	|((data & MAC_QTFCR4_PLT_MASK)<<4));\
	MAC_QTFCR4_WR(v);\
} while (0)

#define MAC_QTFCR4_PLT_RD(data) do {\
	MAC_QTFCR4_RD(data);\
	data = ((data >> 4) & MAC_QTFCR4_PLT_MASK);\
} while (0)


#define MAC_QTFCR4_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR4_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR4_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR4_RD(v);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR4_MASK_8))<<8);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR4_MASK_2))<<2);\
	v = ((v & MAC_QTFCR4_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR4_DZPQ_MASK)<<7));\
	MAC_QTFCR4_WR(v);\
} while (0)

#define MAC_QTFCR4_DZPQ_RD(data) do {\
	MAC_QTFCR4_RD(data);\
	data = ((data >> 7) & MAC_QTFCR4_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR4_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR4_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR4_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR4_RD(v);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR4_MASK_8))<<8);\
	v = (v & (MAC_QTFCR4_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR4_MASK_2))<<2);\
	v = ((v & MAC_QTFCR4_PT_WR_MASK)\
	|((data & MAC_QTFCR4_PT_MASK)<<16));\
	MAC_QTFCR4_WR(v);\
} while (0)

#define MAC_QTFCR4_PT_RD(data) do {\
	MAC_QTFCR4_RD(data);\
	data = ((data >> 16) & MAC_QTFCR4_PT_MASK);\
} while (0)

#define MAC_QTFCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x7c))

#define MAC_QTFCR3_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR3_OFFSET);\
} while (0)

#define MAC_QTFCR3_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR3_OFFSET);\
} while (0)


#define  MAC_QTFCR3_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR3_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR3_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR3_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR3_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR3_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR3_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR3_RD(v);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR3_MASK_8))<<8);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR3_MASK_2))<<2);\
	v = ((v & MAC_QTFCR3_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR3_FCB_BPA_MASK)<<0));\
	MAC_QTFCR3_WR(v);\
} while (0)

#define MAC_QTFCR3_FCB_BPA_RD(data) do {\
	MAC_QTFCR3_RD(data);\
	data = ((data >> 0) & MAC_QTFCR3_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR3_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR3_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR3_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR3_RD(v);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR3_MASK_8))<<8);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR3_MASK_2))<<2);\
	v = ((v & MAC_QTFCR3_TFE_WR_MASK)\
	|((data & MAC_QTFCR3_TFE_MASK)<<1));\
	MAC_QTFCR3_WR(v);\
} while (0)

#define MAC_QTFCR3_TFE_RD(data) do {\
	MAC_QTFCR3_RD(data);\
	data = ((data >> 1) & MAC_QTFCR3_TFE_MASK);\
} while (0)


#define MAC_QTFCR3_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR3_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR3_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR3_RD(v);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR3_MASK_8))<<8);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR3_MASK_2))<<2);\
	v = ((v & MAC_QTFCR3_PLT_WR_MASK)\
	|((data & MAC_QTFCR3_PLT_MASK)<<4));\
	MAC_QTFCR3_WR(v);\
} while (0)

#define MAC_QTFCR3_PLT_RD(data) do {\
	MAC_QTFCR3_RD(data);\
	data = ((data >> 4) & MAC_QTFCR3_PLT_MASK);\
} while (0)


#define MAC_QTFCR3_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR3_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR3_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR3_RD(v);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR3_MASK_8))<<8);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR3_MASK_2))<<2);\
	v = ((v & MAC_QTFCR3_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR3_DZPQ_MASK)<<7));\
	MAC_QTFCR3_WR(v);\
} while (0)

#define MAC_QTFCR3_DZPQ_RD(data) do {\
	MAC_QTFCR3_RD(data);\
	data = ((data >> 7) & MAC_QTFCR3_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR3_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR3_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR3_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR3_RD(v);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR3_MASK_8))<<8);\
	v = (v & (MAC_QTFCR3_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR3_MASK_2))<<2);\
	v = ((v & MAC_QTFCR3_PT_WR_MASK)\
	|((data & MAC_QTFCR3_PT_MASK)<<16));\
	MAC_QTFCR3_WR(v);\
} while (0)

#define MAC_QTFCR3_PT_RD(data) do {\
	MAC_QTFCR3_RD(data);\
	data = ((data >> 16) & MAC_QTFCR3_PT_MASK);\
} while (0)

#define MAC_QTFCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x78))

#define MAC_QTFCR2_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR2_OFFSET);\
} while (0)

#define MAC_QTFCR2_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR2_OFFSET);\
} while (0)


#define  MAC_QTFCR2_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR2_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR2_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR2_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR2_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR2_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR2_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR2_RD(v);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR2_MASK_8))<<8);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR2_MASK_2))<<2);\
	v = ((v & MAC_QTFCR2_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR2_FCB_BPA_MASK)<<0));\
	MAC_QTFCR2_WR(v);\
} while (0)

#define MAC_QTFCR2_FCB_BPA_RD(data) do {\
	MAC_QTFCR2_RD(data);\
	data = ((data >> 0) & MAC_QTFCR2_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR2_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR2_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR2_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR2_RD(v);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR2_MASK_8))<<8);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR2_MASK_2))<<2);\
	v = ((v & MAC_QTFCR2_TFE_WR_MASK)\
	|((data & MAC_QTFCR2_TFE_MASK)<<1));\
	MAC_QTFCR2_WR(v);\
} while (0)

#define MAC_QTFCR2_TFE_RD(data) do {\
	MAC_QTFCR2_RD(data);\
	data = ((data >> 1) & MAC_QTFCR2_TFE_MASK);\
} while (0)


#define MAC_QTFCR2_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR2_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR2_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR2_RD(v);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR2_MASK_8))<<8);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR2_MASK_2))<<2);\
	v = ((v & MAC_QTFCR2_PLT_WR_MASK)\
	|((data & MAC_QTFCR2_PLT_MASK)<<4));\
	MAC_QTFCR2_WR(v);\
} while (0)

#define MAC_QTFCR2_PLT_RD(data) do {\
	MAC_QTFCR2_RD(data);\
	data = ((data >> 4) & MAC_QTFCR2_PLT_MASK);\
} while (0)


#define MAC_QTFCR2_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR2_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR2_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR2_RD(v);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR2_MASK_8))<<8);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR2_MASK_2))<<2);\
	v = ((v & MAC_QTFCR2_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR2_DZPQ_MASK)<<7));\
	MAC_QTFCR2_WR(v);\
} while (0)

#define MAC_QTFCR2_DZPQ_RD(data) do {\
	MAC_QTFCR2_RD(data);\
	data = ((data >> 7) & MAC_QTFCR2_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR2_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR2_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR2_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR2_RD(v);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR2_MASK_8))<<8);\
	v = (v & (MAC_QTFCR2_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR2_MASK_2))<<2);\
	v = ((v & MAC_QTFCR2_PT_WR_MASK)\
	|((data & MAC_QTFCR2_PT_MASK)<<16));\
	MAC_QTFCR2_WR(v);\
} while (0)

#define MAC_QTFCR2_PT_RD(data) do {\
	MAC_QTFCR2_RD(data);\
	data = ((data >> 16) & MAC_QTFCR2_PT_MASK);\
} while (0)

#define MAC_QTFCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x74))

#define MAC_QTFCR1_WR(data) do {\
	iowrite32(data, (void *)MAC_QTFCR1_OFFSET);\
} while (0)

#define MAC_QTFCR1_RD(data) do {\
	(data) = ioread32((void *)MAC_QTFCR1_OFFSET);\
} while (0)


#define  MAC_QTFCR1_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR1_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR1_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR1_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR1_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR1_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR1_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_QTFCR1_RD(v);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR1_MASK_8))<<8);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR1_MASK_2))<<2);\
	v = ((v & MAC_QTFCR1_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR1_FCB_BPA_MASK)<<0));\
	MAC_QTFCR1_WR(v);\
} while (0)

#define MAC_QTFCR1_FCB_BPA_RD(data) do {\
	MAC_QTFCR1_RD(data);\
	data = ((data >> 0) & MAC_QTFCR1_FCB_BPA_MASK);\
} while (0)


#define MAC_QTFCR1_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR1_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR1_TFE_WR(data) do {\
	ULONG v;\
	MAC_QTFCR1_RD(v);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR1_MASK_8))<<8);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR1_MASK_2))<<2);\
	v = ((v & MAC_QTFCR1_TFE_WR_MASK)\
	|((data & MAC_QTFCR1_TFE_MASK)<<1));\
	MAC_QTFCR1_WR(v);\
} while (0)

#define MAC_QTFCR1_TFE_RD(data) do {\
	MAC_QTFCR1_RD(data);\
	data = ((data >> 1) & MAC_QTFCR1_TFE_MASK);\
} while (0)


#define MAC_QTFCR1_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR1_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR1_PLT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR1_RD(v);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR1_MASK_8))<<8);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR1_MASK_2))<<2);\
	v = ((v & MAC_QTFCR1_PLT_WR_MASK)\
	|((data & MAC_QTFCR1_PLT_MASK)<<4));\
	MAC_QTFCR1_WR(v);\
} while (0)

#define MAC_QTFCR1_PLT_RD(data) do {\
	MAC_QTFCR1_RD(data);\
	data = ((data >> 4) & MAC_QTFCR1_PLT_MASK);\
} while (0)


#define MAC_QTFCR1_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR1_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR1_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_QTFCR1_RD(v);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR1_MASK_8))<<8);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR1_MASK_2))<<2);\
	v = ((v & MAC_QTFCR1_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR1_DZPQ_MASK)<<7));\
	MAC_QTFCR1_WR(v);\
} while (0)

#define MAC_QTFCR1_DZPQ_RD(data) do {\
	MAC_QTFCR1_RD(data);\
	data = ((data >> 7) & MAC_QTFCR1_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR1_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR1_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR1_PT_WR(data) do {\
	ULONG v;\
	MAC_QTFCR1_RD(v);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR1_MASK_8))<<8);\
	v = (v & (MAC_QTFCR1_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR1_MASK_2))<<2);\
	v = ((v & MAC_QTFCR1_PT_WR_MASK)\
	|((data & MAC_QTFCR1_PT_MASK)<<16));\
	MAC_QTFCR1_WR(v);\
} while (0)

#define MAC_QTFCR1_PT_RD(data) do {\
	MAC_QTFCR1_RD(data);\
	data = ((data >> 16) & MAC_QTFCR1_PT_MASK);\
} while (0)

#define MAC_Q0TFCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x70))

#define MAC_Q0TFCR_WR(data) do {\
	iowrite32(data, (void *)MAC_Q0TFCR_OFFSET);\
} while (0)

#define MAC_Q0TFCR_RD(data) do {\
	(data) = ioread32((void *)MAC_Q0TFCR_OFFSET);\
} while (0)


#define  MAC_Q0TFCR_MASK_8 (ULONG)(0xff)


#define MAC_Q0TFCR_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_Q0TFCR_MASK_2 (ULONG)(0x3)


#define MAC_Q0TFCR_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_Q0TFCR_PT_MASK (ULONG)(0xffff)


#define MAC_Q0TFCR_PT_WR_MASK (ULONG)(0xffff)

#define MAC_Q0TFCR_PT_WR(data) do {\
	ULONG v;\
	MAC_Q0TFCR_RD(v);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_Q0TFCR_MASK_8))<<8);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_Q0TFCR_MASK_2))<<2);\
	v = ((v & MAC_Q0TFCR_PT_WR_MASK)\
	|((data & MAC_Q0TFCR_PT_MASK)<<16));\
	MAC_Q0TFCR_WR(v);\
} while (0)

#define MAC_Q0TFCR_PT_RD(data) do {\
	MAC_Q0TFCR_RD(data);\
	data = ((data >> 16) & MAC_Q0TFCR_PT_MASK);\
} while (0)


#define MAC_Q0TFCR_DZPQ_MASK (ULONG)(0x1)


#define MAC_Q0TFCR_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_Q0TFCR_DZPQ_WR(data) do {\
	ULONG v;\
	MAC_Q0TFCR_RD(v);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_Q0TFCR_MASK_8))<<8);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_Q0TFCR_MASK_2))<<2);\
	v = ((v & MAC_Q0TFCR_DZPQ_WR_MASK)\
	|((data & MAC_Q0TFCR_DZPQ_MASK)<<7));\
	MAC_Q0TFCR_WR(v);\
} while (0)

#define MAC_Q0TFCR_DZPQ_RD(data) do {\
	MAC_Q0TFCR_RD(data);\
	data = ((data >> 7) & MAC_Q0TFCR_DZPQ_MASK);\
} while (0)


#define MAC_Q0TFCR_PLT_MASK (ULONG)(0x7)


#define MAC_Q0TFCR_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_Q0TFCR_PLT_WR(data) do {\
	ULONG v;\
	MAC_Q0TFCR_RD(v);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_Q0TFCR_MASK_8))<<8);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_Q0TFCR_MASK_2))<<2);\
	v = ((v & MAC_Q0TFCR_PLT_WR_MASK)\
	|((data & MAC_Q0TFCR_PLT_MASK)<<4));\
	MAC_Q0TFCR_WR(v);\
} while (0)

#define MAC_Q0TFCR_PLT_RD(data) do {\
	MAC_Q0TFCR_RD(data);\
	data = ((data >> 4) & MAC_Q0TFCR_PLT_MASK);\
} while (0)


#define MAC_Q0TFCR_TFE_MASK (ULONG)(0x1)


#define MAC_Q0TFCR_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_Q0TFCR_TFE_WR(data) do {\
	ULONG v;\
	MAC_Q0TFCR_RD(v);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_Q0TFCR_MASK_8))<<8);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_Q0TFCR_MASK_2))<<2);\
	v = ((v & MAC_Q0TFCR_TFE_WR_MASK)\
	|((data & MAC_Q0TFCR_TFE_MASK)<<1));\
	MAC_Q0TFCR_WR(v);\
} while (0)

#define MAC_Q0TFCR_TFE_RD(data) do {\
	MAC_Q0TFCR_RD(data);\
	data = ((data >> 1) & MAC_Q0TFCR_TFE_MASK);\
} while (0)


#define MAC_Q0TFCR_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_Q0TFCR_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_Q0TFCR_FCB_BPA_WR(data) do {\
	ULONG v;\
	MAC_Q0TFCR_RD(v);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_Q0TFCR_MASK_8))<<8);\
	v = (v & (MAC_Q0TFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_Q0TFCR_MASK_2))<<2);\
	v = ((v & MAC_Q0TFCR_FCB_BPA_WR_MASK)\
	|((data & MAC_Q0TFCR_FCB_BPA_MASK)<<0));\
	MAC_Q0TFCR_WR(v);\
} while (0)

#define MAC_Q0TFCR_FCB_BPA_RD(data) do {\
	MAC_Q0TFCR_RD(data);\
	data = ((data >> 0) & MAC_Q0TFCR_FCB_BPA_MASK);\
} while (0)

#define DMA_AXI4CR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x14e4))

#define DMA_AXI4CR7_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR7_OFFSET);\
} while (0)

#define DMA_AXI4CR7_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR7_OFFSET);\
} while (0)


#define  DMA_AXI4CR7_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR7_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR7_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR7_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR7_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR7_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR7_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR7_RD(v);\
	v = (v & (DMA_AXI4CR7_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR7_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR7_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR7_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR7_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR7_AWQOS_MASK)<<0));\
	DMA_AXI4CR7_WR(v);\
} while (0)

#define DMA_AXI4CR7_AWQOS_RD(data) do {\
	DMA_AXI4CR7_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR7_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR7_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR7_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR7_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR7_RD(v);\
	v = (v & (DMA_AXI4CR7_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR7_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR7_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR7_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR7_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR7_ARQOS_MASK)<<16));\
	DMA_AXI4CR7_WR(v);\
} while (0)

#define DMA_AXI4CR7_ARQOS_RD(data) do {\
	DMA_AXI4CR7_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR7_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1464))

#define DMA_AXI4CR6_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR6_OFFSET);\
} while (0)

#define DMA_AXI4CR6_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR6_OFFSET);\
} while (0)


#define  DMA_AXI4CR6_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR6_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR6_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR6_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR6_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR6_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR6_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR6_RD(v);\
	v = (v & (DMA_AXI4CR6_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR6_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR6_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR6_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR6_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR6_AWQOS_MASK)<<0));\
	DMA_AXI4CR6_WR(v);\
} while (0)

#define DMA_AXI4CR6_AWQOS_RD(data) do {\
	DMA_AXI4CR6_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR6_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR6_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR6_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR6_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR6_RD(v);\
	v = (v & (DMA_AXI4CR6_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR6_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR6_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR6_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR6_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR6_ARQOS_MASK)<<16));\
	DMA_AXI4CR6_WR(v);\
} while (0)

#define DMA_AXI4CR6_ARQOS_RD(data) do {\
	DMA_AXI4CR6_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR6_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x13e4))

#define DMA_AXI4CR5_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR5_OFFSET);\
} while (0)

#define DMA_AXI4CR5_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR5_OFFSET);\
} while (0)


#define  DMA_AXI4CR5_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR5_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR5_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR5_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR5_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR5_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR5_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR5_RD(v);\
	v = (v & (DMA_AXI4CR5_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR5_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR5_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR5_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR5_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR5_AWQOS_MASK)<<0));\
	DMA_AXI4CR5_WR(v);\
} while (0)

#define DMA_AXI4CR5_AWQOS_RD(data) do {\
	DMA_AXI4CR5_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR5_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR5_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR5_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR5_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR5_RD(v);\
	v = (v & (DMA_AXI4CR5_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR5_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR5_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR5_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR5_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR5_ARQOS_MASK)<<16));\
	DMA_AXI4CR5_WR(v);\
} while (0)

#define DMA_AXI4CR5_ARQOS_RD(data) do {\
	DMA_AXI4CR5_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR5_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1364))

#define DMA_AXI4CR4_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR4_OFFSET);\
} while (0)

#define DMA_AXI4CR4_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR4_OFFSET);\
} while (0)


#define  DMA_AXI4CR4_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR4_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR4_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR4_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR4_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR4_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR4_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR4_RD(v);\
	v = (v & (DMA_AXI4CR4_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR4_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR4_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR4_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR4_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR4_AWQOS_MASK)<<0));\
	DMA_AXI4CR4_WR(v);\
} while (0)

#define DMA_AXI4CR4_AWQOS_RD(data) do {\
	DMA_AXI4CR4_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR4_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR4_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR4_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR4_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR4_RD(v);\
	v = (v & (DMA_AXI4CR4_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR4_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR4_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR4_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR4_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR4_ARQOS_MASK)<<16));\
	DMA_AXI4CR4_WR(v);\
} while (0)

#define DMA_AXI4CR4_ARQOS_RD(data) do {\
	DMA_AXI4CR4_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR4_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x12e4))

#define DMA_AXI4CR3_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR3_OFFSET);\
} while (0)

#define DMA_AXI4CR3_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR3_OFFSET);\
} while (0)


#define  DMA_AXI4CR3_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR3_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR3_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR3_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR3_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR3_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR3_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR3_RD(v);\
	v = (v & (DMA_AXI4CR3_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR3_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR3_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR3_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR3_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR3_AWQOS_MASK)<<0));\
	DMA_AXI4CR3_WR(v);\
} while (0)

#define DMA_AXI4CR3_AWQOS_RD(data) do {\
	DMA_AXI4CR3_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR3_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR3_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR3_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR3_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR3_RD(v);\
	v = (v & (DMA_AXI4CR3_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR3_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR3_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR3_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR3_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR3_ARQOS_MASK)<<16));\
	DMA_AXI4CR3_WR(v);\
} while (0)

#define DMA_AXI4CR3_ARQOS_RD(data) do {\
	DMA_AXI4CR3_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR3_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1264))

#define DMA_AXI4CR2_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR2_OFFSET);\
} while (0)

#define DMA_AXI4CR2_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR2_OFFSET);\
} while (0)


#define  DMA_AXI4CR2_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR2_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR2_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR2_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR2_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR2_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR2_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR2_RD(v);\
	v = (v & (DMA_AXI4CR2_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR2_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR2_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR2_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR2_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR2_AWQOS_MASK)<<0));\
	DMA_AXI4CR2_WR(v);\
} while (0)

#define DMA_AXI4CR2_AWQOS_RD(data) do {\
	DMA_AXI4CR2_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR2_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR2_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR2_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR2_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR2_RD(v);\
	v = (v & (DMA_AXI4CR2_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR2_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR2_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR2_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR2_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR2_ARQOS_MASK)<<16));\
	DMA_AXI4CR2_WR(v);\
} while (0)

#define DMA_AXI4CR2_ARQOS_RD(data) do {\
	DMA_AXI4CR2_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR2_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x11e4))

#define DMA_AXI4CR1_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR1_OFFSET);\
} while (0)

#define DMA_AXI4CR1_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR1_OFFSET);\
} while (0)


#define  DMA_AXI4CR1_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR1_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR1_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR1_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR1_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR1_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR1_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR1_RD(v);\
	v = (v & (DMA_AXI4CR1_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR1_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR1_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR1_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR1_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR1_AWQOS_MASK)<<0));\
	DMA_AXI4CR1_WR(v);\
} while (0)

#define DMA_AXI4CR1_AWQOS_RD(data) do {\
	DMA_AXI4CR1_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR1_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR1_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR1_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR1_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR1_RD(v);\
	v = (v & (DMA_AXI4CR1_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR1_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR1_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR1_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR1_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR1_ARQOS_MASK)<<16));\
	DMA_AXI4CR1_WR(v);\
} while (0)

#define DMA_AXI4CR1_ARQOS_RD(data) do {\
	DMA_AXI4CR1_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR1_ARQOS_MASK);\
} while (0)

#define DMA_AXI4CR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1164))

#define DMA_AXI4CR0_WR(data) do {\
	iowrite32(data, (void *)DMA_AXI4CR0_OFFSET);\
} while (0)

#define DMA_AXI4CR0_RD(data) do {\
	(data) = ioread32((void *)DMA_AXI4CR0_OFFSET);\
} while (0)


#define  DMA_AXI4CR0_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR0_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define  DMA_AXI4CR0_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR0_RES_WR_MASK_20 (ULONG)(0xfffff)


#define DMA_AXI4CR0_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR0_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR0_AWQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR0_RD(v);\
	v = (v & (DMA_AXI4CR0_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR0_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR0_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR0_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR0_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR0_AWQOS_MASK)<<0));\
	DMA_AXI4CR0_WR(v);\
} while (0)

#define DMA_AXI4CR0_AWQOS_RD(data) do {\
	DMA_AXI4CR0_RD(data);\
	data = ((data >> 0) & DMA_AXI4CR0_AWQOS_MASK);\
} while (0)


#define DMA_AXI4CR0_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR0_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR0_ARQOS_WR(data) do {\
	ULONG v;\
	DMA_AXI4CR0_RD(v);\
	v = (v & (DMA_AXI4CR0_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR0_MASK_4))<<4);\
	v = (v & (DMA_AXI4CR0_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR0_MASK_20))<<20);\
	v = ((v & DMA_AXI4CR0_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR0_ARQOS_MASK)<<16));\
	DMA_AXI4CR0_WR(v);\
} while (0)

#define DMA_AXI4CR0_ARQOS_RD(data) do {\
	DMA_AXI4CR0_RD(data);\
	data = ((data >> 16) & DMA_AXI4CR0_ARQOS_MASK);\
} while (0)

#define DMA_RCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1488))

#define DMA_RCR7_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR7_OFFSET);\
} while (0)

#define DMA_RCR7_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR7_OFFSET);\
} while (0)


#define  DMA_RCR7_MASK_15 (ULONG)(0x1)


#define DMA_RCR7_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR7_MASK_22 (ULONG)(0x7)


#define DMA_RCR7_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR7_MASK_28 (ULONG)(0xf)


#define DMA_RCR7_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR7_ST_MASK (ULONG)(0x1)


#define DMA_RCR7_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR7_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR7_RD(v);\
	v = (v & (DMA_RCR7_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR7_MASK_15))<<15);\
	v = (v & (DMA_RCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR7_MASK_22))<<22);\
	v = (v & (DMA_RCR7_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR7_MASK_28))<<28);\
	v = ((v & DMA_RCR7_ST_WR_MASK)\
	|((data & DMA_RCR7_ST_MASK)<<0));\
	DMA_RCR7_WR(v);\
} while (0)

#define DMA_RCR7_ST_RD(data) do {\
	DMA_RCR7_RD(data);\
	data = ((data >> 0) & DMA_RCR7_ST_MASK);\
} while (0)


#define DMA_RCR7_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR7_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR7_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR7_RD(v);\
	v = (v & (DMA_RCR7_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR7_MASK_15))<<15);\
	v = (v & (DMA_RCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR7_MASK_22))<<22);\
	v = (v & (DMA_RCR7_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR7_MASK_28))<<28);\
	v = ((v & DMA_RCR7_RBSZ_WR_MASK)\
	|((data & DMA_RCR7_RBSZ_MASK)<<1));\
	DMA_RCR7_WR(v);\
} while (0)

#define DMA_RCR7_RBSZ_RD(data) do {\
	DMA_RCR7_RD(data);\
	data = ((data >> 1) & DMA_RCR7_RBSZ_MASK);\
} while (0)


#define DMA_RCR7_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR7_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR7_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR7_RD(v);\
	v = (v & (DMA_RCR7_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR7_MASK_15))<<15);\
	v = (v & (DMA_RCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR7_MASK_22))<<22);\
	v = (v & (DMA_RCR7_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR7_MASK_28))<<28);\
	v = ((v & DMA_RCR7_PBL_WR_MASK)\
	|((data & DMA_RCR7_PBL_MASK)<<16));\
	DMA_RCR7_WR(v);\
} while (0)

#define DMA_RCR7_PBL_RD(data) do {\
	DMA_RCR7_RD(data);\
	data = ((data >> 16) & DMA_RCR7_PBL_MASK);\
} while (0)


#define DMA_RCR7_RES_MASK (ULONG)(0x1)


#define DMA_RCR7_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR7_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR7_RD(v);\
	v = (v & (DMA_RCR7_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR7_MASK_15))<<15);\
	v = (v & (DMA_RCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR7_MASK_22))<<22);\
	v = (v & (DMA_RCR7_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR7_MASK_28))<<28);\
	v = ((v & DMA_RCR7_RES_WR_MASK)\
	|((data & DMA_RCR7_RES_MASK)<<25));\
	DMA_RCR7_WR(v);\
} while (0)

#define DMA_RCR7_RES_RD(data) do {\
	DMA_RCR7_RD(data);\
	data = ((data >> 25) & DMA_RCR7_RES_MASK);\
} while (0)


#define DMA_RCR7_DFF_MASK (ULONG)(0x1)


#define DMA_RCR7_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR7_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR7_RD(v);\
	v = (v & (DMA_RCR7_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR7_MASK_15))<<15);\
	v = (v & (DMA_RCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR7_MASK_22))<<22);\
	v = (v & (DMA_RCR7_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR7_MASK_28))<<28);\
	v = ((v & DMA_RCR7_DFF_WR_MASK)\
	|((data & DMA_RCR7_DFF_MASK)<<26));\
	DMA_RCR7_WR(v);\
} while (0)

#define DMA_RCR7_DFF_RD(data) do {\
	DMA_RCR7_RD(data);\
	data = ((data >> 26) & DMA_RCR7_DFF_MASK);\
} while (0)


#define DMA_RCR7_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR7_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR7_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR7_RD(v);\
	v = (v & (DMA_RCR7_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR7_MASK_15))<<15);\
	v = (v & (DMA_RCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR7_MASK_22))<<22);\
	v = (v & (DMA_RCR7_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR7_MASK_28))<<28);\
	v = ((v & DMA_RCR7_MAMS_WR_MASK)\
	|((data & DMA_RCR7_MAMS_MASK)<<27));\
	DMA_RCR7_WR(v);\
} while (0)

#define DMA_RCR7_MAMS_RD(data) do {\
	DMA_RCR7_RD(data);\
	data = ((data >> 27) & DMA_RCR7_MAMS_MASK);\
} while (0)

#define DMA_RCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1408))

#define DMA_RCR6_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR6_OFFSET);\
} while (0)

#define DMA_RCR6_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR6_OFFSET);\
} while (0)


#define  DMA_RCR6_MASK_15 (ULONG)(0x1)


#define DMA_RCR6_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR6_MASK_22 (ULONG)(0x7)


#define DMA_RCR6_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR6_MASK_28 (ULONG)(0xf)


#define DMA_RCR6_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR6_ST_MASK (ULONG)(0x1)


#define DMA_RCR6_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR6_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR6_RD(v);\
	v = (v & (DMA_RCR6_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR6_MASK_15))<<15);\
	v = (v & (DMA_RCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR6_MASK_22))<<22);\
	v = (v & (DMA_RCR6_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR6_MASK_28))<<28);\
	v = ((v & DMA_RCR6_ST_WR_MASK)\
	|((data & DMA_RCR6_ST_MASK)<<0));\
	DMA_RCR6_WR(v);\
} while (0)

#define DMA_RCR6_ST_RD(data) do {\
	DMA_RCR6_RD(data);\
	data = ((data >> 0) & DMA_RCR6_ST_MASK);\
} while (0)


#define DMA_RCR6_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR6_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR6_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR6_RD(v);\
	v = (v & (DMA_RCR6_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR6_MASK_15))<<15);\
	v = (v & (DMA_RCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR6_MASK_22))<<22);\
	v = (v & (DMA_RCR6_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR6_MASK_28))<<28);\
	v = ((v & DMA_RCR6_RBSZ_WR_MASK)\
	|((data & DMA_RCR6_RBSZ_MASK)<<1));\
	DMA_RCR6_WR(v);\
} while (0)

#define DMA_RCR6_RBSZ_RD(data) do {\
	DMA_RCR6_RD(data);\
	data = ((data >> 1) & DMA_RCR6_RBSZ_MASK);\
} while (0)


#define DMA_RCR6_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR6_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR6_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR6_RD(v);\
	v = (v & (DMA_RCR6_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR6_MASK_15))<<15);\
	v = (v & (DMA_RCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR6_MASK_22))<<22);\
	v = (v & (DMA_RCR6_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR6_MASK_28))<<28);\
	v = ((v & DMA_RCR6_PBL_WR_MASK)\
	|((data & DMA_RCR6_PBL_MASK)<<16));\
	DMA_RCR6_WR(v);\
} while (0)

#define DMA_RCR6_PBL_RD(data) do {\
	DMA_RCR6_RD(data);\
	data = ((data >> 16) & DMA_RCR6_PBL_MASK);\
} while (0)


#define DMA_RCR6_RES_MASK (ULONG)(0x1)


#define DMA_RCR6_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR6_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR6_RD(v);\
	v = (v & (DMA_RCR6_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR6_MASK_15))<<15);\
	v = (v & (DMA_RCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR6_MASK_22))<<22);\
	v = (v & (DMA_RCR6_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR6_MASK_28))<<28);\
	v = ((v & DMA_RCR6_RES_WR_MASK)\
	|((data & DMA_RCR6_RES_MASK)<<25));\
	DMA_RCR6_WR(v);\
} while (0)

#define DMA_RCR6_RES_RD(data) do {\
	DMA_RCR6_RD(data);\
	data = ((data >> 25) & DMA_RCR6_RES_MASK);\
} while (0)


#define DMA_RCR6_DFF_MASK (ULONG)(0x1)


#define DMA_RCR6_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR6_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR6_RD(v);\
	v = (v & (DMA_RCR6_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR6_MASK_15))<<15);\
	v = (v & (DMA_RCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR6_MASK_22))<<22);\
	v = (v & (DMA_RCR6_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR6_MASK_28))<<28);\
	v = ((v & DMA_RCR6_DFF_WR_MASK)\
	|((data & DMA_RCR6_DFF_MASK)<<26));\
	DMA_RCR6_WR(v);\
} while (0)

#define DMA_RCR6_DFF_RD(data) do {\
	DMA_RCR6_RD(data);\
	data = ((data >> 26) & DMA_RCR6_DFF_MASK);\
} while (0)


#define DMA_RCR6_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR6_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR6_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR6_RD(v);\
	v = (v & (DMA_RCR6_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR6_MASK_15))<<15);\
	v = (v & (DMA_RCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR6_MASK_22))<<22);\
	v = (v & (DMA_RCR6_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR6_MASK_28))<<28);\
	v = ((v & DMA_RCR6_MAMS_WR_MASK)\
	|((data & DMA_RCR6_MAMS_MASK)<<27));\
	DMA_RCR6_WR(v);\
} while (0)

#define DMA_RCR6_MAMS_RD(data) do {\
	DMA_RCR6_RD(data);\
	data = ((data >> 27) & DMA_RCR6_MAMS_MASK);\
} while (0)

#define DMA_RCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1388))

#define DMA_RCR5_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR5_OFFSET);\
} while (0)

#define DMA_RCR5_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR5_OFFSET);\
} while (0)


#define  DMA_RCR5_MASK_15 (ULONG)(0x1)


#define DMA_RCR5_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR5_MASK_22 (ULONG)(0x7)


#define DMA_RCR5_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR5_MASK_28 (ULONG)(0xf)


#define DMA_RCR5_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR5_ST_MASK (ULONG)(0x1)


#define DMA_RCR5_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR5_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR5_RD(v);\
	v = (v & (DMA_RCR5_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR5_MASK_15))<<15);\
	v = (v & (DMA_RCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR5_MASK_22))<<22);\
	v = (v & (DMA_RCR5_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR5_MASK_28))<<28);\
	v = ((v & DMA_RCR5_ST_WR_MASK)\
	|((data & DMA_RCR5_ST_MASK)<<0));\
	DMA_RCR5_WR(v);\
} while (0)

#define DMA_RCR5_ST_RD(data) do {\
	DMA_RCR5_RD(data);\
	data = ((data >> 0) & DMA_RCR5_ST_MASK);\
} while (0)


#define DMA_RCR5_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR5_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR5_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR5_RD(v);\
	v = (v & (DMA_RCR5_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR5_MASK_15))<<15);\
	v = (v & (DMA_RCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR5_MASK_22))<<22);\
	v = (v & (DMA_RCR5_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR5_MASK_28))<<28);\
	v = ((v & DMA_RCR5_RBSZ_WR_MASK)\
	|((data & DMA_RCR5_RBSZ_MASK)<<1));\
	DMA_RCR5_WR(v);\
} while (0)

#define DMA_RCR5_RBSZ_RD(data) do {\
	DMA_RCR5_RD(data);\
	data = ((data >> 1) & DMA_RCR5_RBSZ_MASK);\
} while (0)


#define DMA_RCR5_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR5_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR5_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR5_RD(v);\
	v = (v & (DMA_RCR5_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR5_MASK_15))<<15);\
	v = (v & (DMA_RCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR5_MASK_22))<<22);\
	v = (v & (DMA_RCR5_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR5_MASK_28))<<28);\
	v = ((v & DMA_RCR5_PBL_WR_MASK)\
	|((data & DMA_RCR5_PBL_MASK)<<16));\
	DMA_RCR5_WR(v);\
} while (0)

#define DMA_RCR5_PBL_RD(data) do {\
	DMA_RCR5_RD(data);\
	data = ((data >> 16) & DMA_RCR5_PBL_MASK);\
} while (0)


#define DMA_RCR5_RES_MASK (ULONG)(0x1)


#define DMA_RCR5_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR5_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR5_RD(v);\
	v = (v & (DMA_RCR5_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR5_MASK_15))<<15);\
	v = (v & (DMA_RCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR5_MASK_22))<<22);\
	v = (v & (DMA_RCR5_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR5_MASK_28))<<28);\
	v = ((v & DMA_RCR5_RES_WR_MASK)\
	|((data & DMA_RCR5_RES_MASK)<<25));\
	DMA_RCR5_WR(v);\
} while (0)

#define DMA_RCR5_RES_RD(data) do {\
	DMA_RCR5_RD(data);\
	data = ((data >> 25) & DMA_RCR5_RES_MASK);\
} while (0)


#define DMA_RCR5_DFF_MASK (ULONG)(0x1)


#define DMA_RCR5_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR5_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR5_RD(v);\
	v = (v & (DMA_RCR5_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR5_MASK_15))<<15);\
	v = (v & (DMA_RCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR5_MASK_22))<<22);\
	v = (v & (DMA_RCR5_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR5_MASK_28))<<28);\
	v = ((v & DMA_RCR5_DFF_WR_MASK)\
	|((data & DMA_RCR5_DFF_MASK)<<26));\
	DMA_RCR5_WR(v);\
} while (0)

#define DMA_RCR5_DFF_RD(data) do {\
	DMA_RCR5_RD(data);\
	data = ((data >> 26) & DMA_RCR5_DFF_MASK);\
} while (0)


#define DMA_RCR5_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR5_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR5_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR5_RD(v);\
	v = (v & (DMA_RCR5_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR5_MASK_15))<<15);\
	v = (v & (DMA_RCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR5_MASK_22))<<22);\
	v = (v & (DMA_RCR5_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR5_MASK_28))<<28);\
	v = ((v & DMA_RCR5_MAMS_WR_MASK)\
	|((data & DMA_RCR5_MAMS_MASK)<<27));\
	DMA_RCR5_WR(v);\
} while (0)

#define DMA_RCR5_MAMS_RD(data) do {\
	DMA_RCR5_RD(data);\
	data = ((data >> 27) & DMA_RCR5_MAMS_MASK);\
} while (0)

#define DMA_RCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1308))

#define DMA_RCR4_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR4_OFFSET);\
} while (0)

#define DMA_RCR4_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR4_OFFSET);\
} while (0)


#define  DMA_RCR4_MASK_15 (ULONG)(0x1)


#define DMA_RCR4_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR4_MASK_22 (ULONG)(0x7)


#define DMA_RCR4_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR4_MASK_28 (ULONG)(0xf)


#define DMA_RCR4_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR4_ST_MASK (ULONG)(0x1)


#define DMA_RCR4_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR4_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR4_RD(v);\
	v = (v & (DMA_RCR4_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR4_MASK_15))<<15);\
	v = (v & (DMA_RCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR4_MASK_22))<<22);\
	v = (v & (DMA_RCR4_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR4_MASK_28))<<28);\
	v = ((v & DMA_RCR4_ST_WR_MASK)\
	|((data & DMA_RCR4_ST_MASK)<<0));\
	DMA_RCR4_WR(v);\
} while (0)

#define DMA_RCR4_ST_RD(data) do {\
	DMA_RCR4_RD(data);\
	data = ((data >> 0) & DMA_RCR4_ST_MASK);\
} while (0)


#define DMA_RCR4_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR4_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR4_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR4_RD(v);\
	v = (v & (DMA_RCR4_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR4_MASK_15))<<15);\
	v = (v & (DMA_RCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR4_MASK_22))<<22);\
	v = (v & (DMA_RCR4_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR4_MASK_28))<<28);\
	v = ((v & DMA_RCR4_RBSZ_WR_MASK)\
	|((data & DMA_RCR4_RBSZ_MASK)<<1));\
	DMA_RCR4_WR(v);\
} while (0)

#define DMA_RCR4_RBSZ_RD(data) do {\
	DMA_RCR4_RD(data);\
	data = ((data >> 1) & DMA_RCR4_RBSZ_MASK);\
} while (0)


#define DMA_RCR4_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR4_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR4_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR4_RD(v);\
	v = (v & (DMA_RCR4_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR4_MASK_15))<<15);\
	v = (v & (DMA_RCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR4_MASK_22))<<22);\
	v = (v & (DMA_RCR4_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR4_MASK_28))<<28);\
	v = ((v & DMA_RCR4_PBL_WR_MASK)\
	|((data & DMA_RCR4_PBL_MASK)<<16));\
	DMA_RCR4_WR(v);\
} while (0)

#define DMA_RCR4_PBL_RD(data) do {\
	DMA_RCR4_RD(data);\
	data = ((data >> 16) & DMA_RCR4_PBL_MASK);\
} while (0)


#define DMA_RCR4_RES_MASK (ULONG)(0x1)


#define DMA_RCR4_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR4_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR4_RD(v);\
	v = (v & (DMA_RCR4_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR4_MASK_15))<<15);\
	v = (v & (DMA_RCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR4_MASK_22))<<22);\
	v = (v & (DMA_RCR4_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR4_MASK_28))<<28);\
	v = ((v & DMA_RCR4_RES_WR_MASK)\
	|((data & DMA_RCR4_RES_MASK)<<25));\
	DMA_RCR4_WR(v);\
} while (0)

#define DMA_RCR4_RES_RD(data) do {\
	DMA_RCR4_RD(data);\
	data = ((data >> 25) & DMA_RCR4_RES_MASK);\
} while (0)


#define DMA_RCR4_DFF_MASK (ULONG)(0x1)


#define DMA_RCR4_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR4_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR4_RD(v);\
	v = (v & (DMA_RCR4_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR4_MASK_15))<<15);\
	v = (v & (DMA_RCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR4_MASK_22))<<22);\
	v = (v & (DMA_RCR4_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR4_MASK_28))<<28);\
	v = ((v & DMA_RCR4_DFF_WR_MASK)\
	|((data & DMA_RCR4_DFF_MASK)<<26));\
	DMA_RCR4_WR(v);\
} while (0)

#define DMA_RCR4_DFF_RD(data) do {\
	DMA_RCR4_RD(data);\
	data = ((data >> 26) & DMA_RCR4_DFF_MASK);\
} while (0)


#define DMA_RCR4_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR4_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR4_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR4_RD(v);\
	v = (v & (DMA_RCR4_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR4_MASK_15))<<15);\
	v = (v & (DMA_RCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR4_MASK_22))<<22);\
	v = (v & (DMA_RCR4_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR4_MASK_28))<<28);\
	v = ((v & DMA_RCR4_MAMS_WR_MASK)\
	|((data & DMA_RCR4_MAMS_MASK)<<27));\
	DMA_RCR4_WR(v);\
} while (0)

#define DMA_RCR4_MAMS_RD(data) do {\
	DMA_RCR4_RD(data);\
	data = ((data >> 27) & DMA_RCR4_MAMS_MASK);\
} while (0)

#define DMA_RCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1288))

#define DMA_RCR3_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR3_OFFSET);\
} while (0)

#define DMA_RCR3_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR3_OFFSET);\
} while (0)


#define  DMA_RCR3_MASK_15 (ULONG)(0x1)


#define DMA_RCR3_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR3_MASK_22 (ULONG)(0x7)


#define DMA_RCR3_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR3_MASK_28 (ULONG)(0xf)


#define DMA_RCR3_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR3_ST_MASK (ULONG)(0x1)


#define DMA_RCR3_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR3_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR3_RD(v);\
	v = (v & (DMA_RCR3_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR3_MASK_15))<<15);\
	v = (v & (DMA_RCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR3_MASK_22))<<22);\
	v = (v & (DMA_RCR3_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR3_MASK_28))<<28);\
	v = ((v & DMA_RCR3_ST_WR_MASK)\
	|((data & DMA_RCR3_ST_MASK)<<0));\
	DMA_RCR3_WR(v);\
} while (0)

#define DMA_RCR3_ST_RD(data) do {\
	DMA_RCR3_RD(data);\
	data = ((data >> 0) & DMA_RCR3_ST_MASK);\
} while (0)


#define DMA_RCR3_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR3_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR3_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR3_RD(v);\
	v = (v & (DMA_RCR3_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR3_MASK_15))<<15);\
	v = (v & (DMA_RCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR3_MASK_22))<<22);\
	v = (v & (DMA_RCR3_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR3_MASK_28))<<28);\
	v = ((v & DMA_RCR3_RBSZ_WR_MASK)\
	|((data & DMA_RCR3_RBSZ_MASK)<<1));\
	DMA_RCR3_WR(v);\
} while (0)

#define DMA_RCR3_RBSZ_RD(data) do {\
	DMA_RCR3_RD(data);\
	data = ((data >> 1) & DMA_RCR3_RBSZ_MASK);\
} while (0)


#define DMA_RCR3_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR3_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR3_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR3_RD(v);\
	v = (v & (DMA_RCR3_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR3_MASK_15))<<15);\
	v = (v & (DMA_RCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR3_MASK_22))<<22);\
	v = (v & (DMA_RCR3_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR3_MASK_28))<<28);\
	v = ((v & DMA_RCR3_PBL_WR_MASK)\
	|((data & DMA_RCR3_PBL_MASK)<<16));\
	DMA_RCR3_WR(v);\
} while (0)

#define DMA_RCR3_PBL_RD(data) do {\
	DMA_RCR3_RD(data);\
	data = ((data >> 16) & DMA_RCR3_PBL_MASK);\
} while (0)


#define DMA_RCR3_RES_MASK (ULONG)(0x1)


#define DMA_RCR3_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR3_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR3_RD(v);\
	v = (v & (DMA_RCR3_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR3_MASK_15))<<15);\
	v = (v & (DMA_RCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR3_MASK_22))<<22);\
	v = (v & (DMA_RCR3_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR3_MASK_28))<<28);\
	v = ((v & DMA_RCR3_RES_WR_MASK)\
	|((data & DMA_RCR3_RES_MASK)<<25));\
	DMA_RCR3_WR(v);\
} while (0)

#define DMA_RCR3_RES_RD(data) do {\
	DMA_RCR3_RD(data);\
	data = ((data >> 25) & DMA_RCR3_RES_MASK);\
} while (0)


#define DMA_RCR3_DFF_MASK (ULONG)(0x1)


#define DMA_RCR3_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR3_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR3_RD(v);\
	v = (v & (DMA_RCR3_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR3_MASK_15))<<15);\
	v = (v & (DMA_RCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR3_MASK_22))<<22);\
	v = (v & (DMA_RCR3_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR3_MASK_28))<<28);\
	v = ((v & DMA_RCR3_DFF_WR_MASK)\
	|((data & DMA_RCR3_DFF_MASK)<<26));\
	DMA_RCR3_WR(v);\
} while (0)

#define DMA_RCR3_DFF_RD(data) do {\
	DMA_RCR3_RD(data);\
	data = ((data >> 26) & DMA_RCR3_DFF_MASK);\
} while (0)


#define DMA_RCR3_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR3_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR3_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR3_RD(v);\
	v = (v & (DMA_RCR3_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR3_MASK_15))<<15);\
	v = (v & (DMA_RCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR3_MASK_22))<<22);\
	v = (v & (DMA_RCR3_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR3_MASK_28))<<28);\
	v = ((v & DMA_RCR3_MAMS_WR_MASK)\
	|((data & DMA_RCR3_MAMS_MASK)<<27));\
	DMA_RCR3_WR(v);\
} while (0)

#define DMA_RCR3_MAMS_RD(data) do {\
	DMA_RCR3_RD(data);\
	data = ((data >> 27) & DMA_RCR3_MAMS_MASK);\
} while (0)

#define DMA_RCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1208))

#define DMA_RCR2_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR2_OFFSET);\
} while (0)

#define DMA_RCR2_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR2_OFFSET);\
} while (0)


#define  DMA_RCR2_MASK_15 (ULONG)(0x1)


#define DMA_RCR2_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR2_MASK_22 (ULONG)(0x7)


#define DMA_RCR2_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR2_MASK_28 (ULONG)(0xf)


#define DMA_RCR2_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR2_ST_MASK (ULONG)(0x1)


#define DMA_RCR2_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR2_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR2_RD(v);\
	v = (v & (DMA_RCR2_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR2_MASK_15))<<15);\
	v = (v & (DMA_RCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR2_MASK_22))<<22);\
	v = (v & (DMA_RCR2_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR2_MASK_28))<<28);\
	v = ((v & DMA_RCR2_ST_WR_MASK)\
	|((data & DMA_RCR2_ST_MASK)<<0));\
	DMA_RCR2_WR(v);\
} while (0)

#define DMA_RCR2_ST_RD(data) do {\
	DMA_RCR2_RD(data);\
	data = ((data >> 0) & DMA_RCR2_ST_MASK);\
} while (0)


#define DMA_RCR2_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR2_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR2_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR2_RD(v);\
	v = (v & (DMA_RCR2_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR2_MASK_15))<<15);\
	v = (v & (DMA_RCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR2_MASK_22))<<22);\
	v = (v & (DMA_RCR2_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR2_MASK_28))<<28);\
	v = ((v & DMA_RCR2_RBSZ_WR_MASK)\
	|((data & DMA_RCR2_RBSZ_MASK)<<1));\
	DMA_RCR2_WR(v);\
} while (0)

#define DMA_RCR2_RBSZ_RD(data) do {\
	DMA_RCR2_RD(data);\
	data = ((data >> 1) & DMA_RCR2_RBSZ_MASK);\
} while (0)


#define DMA_RCR2_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR2_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR2_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR2_RD(v);\
	v = (v & (DMA_RCR2_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR2_MASK_15))<<15);\
	v = (v & (DMA_RCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR2_MASK_22))<<22);\
	v = (v & (DMA_RCR2_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR2_MASK_28))<<28);\
	v = ((v & DMA_RCR2_PBL_WR_MASK)\
	|((data & DMA_RCR2_PBL_MASK)<<16));\
	DMA_RCR2_WR(v);\
} while (0)

#define DMA_RCR2_PBL_RD(data) do {\
	DMA_RCR2_RD(data);\
	data = ((data >> 16) & DMA_RCR2_PBL_MASK);\
} while (0)


#define DMA_RCR2_RES_MASK (ULONG)(0x1)


#define DMA_RCR2_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR2_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR2_RD(v);\
	v = (v & (DMA_RCR2_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR2_MASK_15))<<15);\
	v = (v & (DMA_RCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR2_MASK_22))<<22);\
	v = (v & (DMA_RCR2_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR2_MASK_28))<<28);\
	v = ((v & DMA_RCR2_RES_WR_MASK)\
	|((data & DMA_RCR2_RES_MASK)<<25));\
	DMA_RCR2_WR(v);\
} while (0)

#define DMA_RCR2_RES_RD(data) do {\
	DMA_RCR2_RD(data);\
	data = ((data >> 25) & DMA_RCR2_RES_MASK);\
} while (0)


#define DMA_RCR2_DFF_MASK (ULONG)(0x1)


#define DMA_RCR2_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR2_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR2_RD(v);\
	v = (v & (DMA_RCR2_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR2_MASK_15))<<15);\
	v = (v & (DMA_RCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR2_MASK_22))<<22);\
	v = (v & (DMA_RCR2_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR2_MASK_28))<<28);\
	v = ((v & DMA_RCR2_DFF_WR_MASK)\
	|((data & DMA_RCR2_DFF_MASK)<<26));\
	DMA_RCR2_WR(v);\
} while (0)

#define DMA_RCR2_DFF_RD(data) do {\
	DMA_RCR2_RD(data);\
	data = ((data >> 26) & DMA_RCR2_DFF_MASK);\
} while (0)


#define DMA_RCR2_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR2_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR2_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR2_RD(v);\
	v = (v & (DMA_RCR2_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR2_MASK_15))<<15);\
	v = (v & (DMA_RCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR2_MASK_22))<<22);\
	v = (v & (DMA_RCR2_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR2_MASK_28))<<28);\
	v = ((v & DMA_RCR2_MAMS_WR_MASK)\
	|((data & DMA_RCR2_MAMS_MASK)<<27));\
	DMA_RCR2_WR(v);\
} while (0)

#define DMA_RCR2_MAMS_RD(data) do {\
	DMA_RCR2_RD(data);\
	data = ((data >> 27) & DMA_RCR2_MAMS_MASK);\
} while (0)

#define DMA_RCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1188))

#define DMA_RCR1_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR1_OFFSET);\
} while (0)

#define DMA_RCR1_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR1_OFFSET);\
} while (0)


#define  DMA_RCR1_MASK_15 (ULONG)(0x1)


#define DMA_RCR1_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR1_MASK_22 (ULONG)(0x7)


#define DMA_RCR1_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR1_MASK_28 (ULONG)(0xf)


#define DMA_RCR1_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR1_ST_MASK (ULONG)(0x1)


#define DMA_RCR1_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR1_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR1_RD(v);\
	v = (v & (DMA_RCR1_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR1_MASK_15))<<15);\
	v = (v & (DMA_RCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR1_MASK_22))<<22);\
	v = (v & (DMA_RCR1_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR1_MASK_28))<<28);\
	v = ((v & DMA_RCR1_ST_WR_MASK)\
	|((data & DMA_RCR1_ST_MASK)<<0));\
	DMA_RCR1_WR(v);\
} while (0)

#define DMA_RCR1_ST_RD(data) do {\
	DMA_RCR1_RD(data);\
	data = ((data >> 0) & DMA_RCR1_ST_MASK);\
} while (0)


#define DMA_RCR1_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR1_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR1_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR1_RD(v);\
	v = (v & (DMA_RCR1_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR1_MASK_15))<<15);\
	v = (v & (DMA_RCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR1_MASK_22))<<22);\
	v = (v & (DMA_RCR1_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR1_MASK_28))<<28);\
	v = ((v & DMA_RCR1_RBSZ_WR_MASK)\
	|((data & DMA_RCR1_RBSZ_MASK)<<1));\
	DMA_RCR1_WR(v);\
} while (0)

#define DMA_RCR1_RBSZ_RD(data) do {\
	DMA_RCR1_RD(data);\
	data = ((data >> 1) & DMA_RCR1_RBSZ_MASK);\
} while (0)


#define DMA_RCR1_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR1_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR1_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR1_RD(v);\
	v = (v & (DMA_RCR1_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR1_MASK_15))<<15);\
	v = (v & (DMA_RCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR1_MASK_22))<<22);\
	v = (v & (DMA_RCR1_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR1_MASK_28))<<28);\
	v = ((v & DMA_RCR1_PBL_WR_MASK)\
	|((data & DMA_RCR1_PBL_MASK)<<16));\
	DMA_RCR1_WR(v);\
} while (0)

#define DMA_RCR1_PBL_RD(data) do {\
	DMA_RCR1_RD(data);\
	data = ((data >> 16) & DMA_RCR1_PBL_MASK);\
} while (0)


#define DMA_RCR1_RES_MASK (ULONG)(0x1)


#define DMA_RCR1_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR1_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR1_RD(v);\
	v = (v & (DMA_RCR1_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR1_MASK_15))<<15);\
	v = (v & (DMA_RCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR1_MASK_22))<<22);\
	v = (v & (DMA_RCR1_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR1_MASK_28))<<28);\
	v = ((v & DMA_RCR1_RES_WR_MASK)\
	|((data & DMA_RCR1_RES_MASK)<<25));\
	DMA_RCR1_WR(v);\
} while (0)

#define DMA_RCR1_RES_RD(data) do {\
	DMA_RCR1_RD(data);\
	data = ((data >> 25) & DMA_RCR1_RES_MASK);\
} while (0)


#define DMA_RCR1_DFF_MASK (ULONG)(0x1)


#define DMA_RCR1_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR1_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR1_RD(v);\
	v = (v & (DMA_RCR1_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR1_MASK_15))<<15);\
	v = (v & (DMA_RCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR1_MASK_22))<<22);\
	v = (v & (DMA_RCR1_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR1_MASK_28))<<28);\
	v = ((v & DMA_RCR1_DFF_WR_MASK)\
	|((data & DMA_RCR1_DFF_MASK)<<26));\
	DMA_RCR1_WR(v);\
} while (0)

#define DMA_RCR1_DFF_RD(data) do {\
	DMA_RCR1_RD(data);\
	data = ((data >> 26) & DMA_RCR1_DFF_MASK);\
} while (0)


#define DMA_RCR1_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR1_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR1_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR1_RD(v);\
	v = (v & (DMA_RCR1_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR1_MASK_15))<<15);\
	v = (v & (DMA_RCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR1_MASK_22))<<22);\
	v = (v & (DMA_RCR1_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR1_MASK_28))<<28);\
	v = ((v & DMA_RCR1_MAMS_WR_MASK)\
	|((data & DMA_RCR1_MAMS_MASK)<<27));\
	DMA_RCR1_WR(v);\
} while (0)

#define DMA_RCR1_MAMS_RD(data) do {\
	DMA_RCR1_RD(data);\
	data = ((data >> 27) & DMA_RCR1_MAMS_MASK);\
} while (0)

#define DMA_RCR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1108))

#define DMA_RCR0_WR(data) do {\
	iowrite32(data, (void *)DMA_RCR0_OFFSET);\
} while (0)

#define DMA_RCR0_RD(data) do {\
	(data) = ioread32((void *)DMA_RCR0_OFFSET);\
} while (0)


#define  DMA_RCR0_MASK_15 (ULONG)(0x1)


#define DMA_RCR0_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define  DMA_RCR0_MASK_22 (ULONG)(0x7)


#define DMA_RCR0_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR0_MASK_28 (ULONG)(0xf)


#define DMA_RCR0_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define DMA_RCR0_ST_MASK (ULONG)(0x1)


#define DMA_RCR0_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR0_ST_WR(data) do {\
	ULONG v;\
	DMA_RCR0_RD(v);\
	v = (v & (DMA_RCR0_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR0_MASK_15))<<15);\
	v = (v & (DMA_RCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR0_MASK_22))<<22);\
	v = (v & (DMA_RCR0_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR0_MASK_28))<<28);\
	v = ((v & DMA_RCR0_ST_WR_MASK)\
	|((data & DMA_RCR0_ST_MASK)<<0));\
	DMA_RCR0_WR(v);\
} while (0)

#define DMA_RCR0_ST_RD(data) do {\
	DMA_RCR0_RD(data);\
	data = ((data >> 0) & DMA_RCR0_ST_MASK);\
} while (0)


#define DMA_RCR0_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR0_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR0_RBSZ_WR(data) do {\
	ULONG v;\
	DMA_RCR0_RD(v);\
	v = (v & (DMA_RCR0_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR0_MASK_15))<<15);\
	v = (v & (DMA_RCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR0_MASK_22))<<22);\
	v = (v & (DMA_RCR0_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR0_MASK_28))<<28);\
	v = ((v & DMA_RCR0_RBSZ_WR_MASK)\
	|((data & DMA_RCR0_RBSZ_MASK)<<1));\
	DMA_RCR0_WR(v);\
} while (0)

#define DMA_RCR0_RBSZ_RD(data) do {\
	DMA_RCR0_RD(data);\
	data = ((data >> 1) & DMA_RCR0_RBSZ_MASK);\
} while (0)


#define DMA_RCR0_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR0_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR0_PBL_WR(data) do {\
	ULONG v;\
	DMA_RCR0_RD(v);\
	v = (v & (DMA_RCR0_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR0_MASK_15))<<15);\
	v = (v & (DMA_RCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR0_MASK_22))<<22);\
	v = (v & (DMA_RCR0_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR0_MASK_28))<<28);\
	v = ((v & DMA_RCR0_PBL_WR_MASK)\
	|((data & DMA_RCR0_PBL_MASK)<<16));\
	DMA_RCR0_WR(v);\
} while (0)

#define DMA_RCR0_PBL_RD(data) do {\
	DMA_RCR0_RD(data);\
	data = ((data >> 16) & DMA_RCR0_PBL_MASK);\
} while (0)


#define DMA_RCR0_RES_MASK (ULONG)(0x1)


#define DMA_RCR0_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR0_RES_WR(data) do {\
	ULONG v;\
	DMA_RCR0_RD(v);\
	v = (v & (DMA_RCR0_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR0_MASK_15))<<15);\
	v = (v & (DMA_RCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR0_MASK_22))<<22);\
	v = (v & (DMA_RCR0_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR0_MASK_28))<<28);\
	v = ((v & DMA_RCR0_RES_WR_MASK)\
	|((data & DMA_RCR0_RES_MASK)<<25));\
	DMA_RCR0_WR(v);\
} while (0)

#define DMA_RCR0_RES_RD(data) do {\
	DMA_RCR0_RD(data);\
	data = ((data >> 25) & DMA_RCR0_RES_MASK);\
} while (0)


#define DMA_RCR0_DFF_MASK (ULONG)(0x1)


#define DMA_RCR0_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR0_DFF_WR(data) do {\
	ULONG v;\
	DMA_RCR0_RD(v);\
	v = (v & (DMA_RCR0_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR0_MASK_15))<<15);\
	v = (v & (DMA_RCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR0_MASK_22))<<22);\
	v = (v & (DMA_RCR0_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR0_MASK_28))<<28);\
	v = ((v & DMA_RCR0_DFF_WR_MASK)\
	|((data & DMA_RCR0_DFF_MASK)<<26));\
	DMA_RCR0_WR(v);\
} while (0)

#define DMA_RCR0_DFF_RD(data) do {\
	DMA_RCR0_RD(data);\
	data = ((data >> 26) & DMA_RCR0_DFF_MASK);\
} while (0)


#define DMA_RCR0_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR0_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR0_MAMS_WR(data) do {\
	ULONG v;\
	DMA_RCR0_RD(v);\
	v = (v & (DMA_RCR0_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR0_MASK_15))<<15);\
	v = (v & (DMA_RCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR0_MASK_22))<<22);\
	v = (v & (DMA_RCR0_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR0_MASK_28))<<28);\
	v = ((v & DMA_RCR0_MAMS_WR_MASK)\
	|((data & DMA_RCR0_MAMS_MASK)<<27));\
	DMA_RCR0_WR(v);\
} while (0)

#define DMA_RCR0_MAMS_RD(data) do {\
	DMA_RCR0_RD(data);\
	data = ((data >> 27) & DMA_RCR0_MAMS_MASK);\
} while (0)

#define DMA_TCR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1484))

#define DMA_TCR7_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR7_OFFSET);\
} while (0)

#define DMA_TCR7_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR7_OFFSET);\
} while (0)


#define  DMA_TCR7_MASK_5 (ULONG)(0x7f)


#define DMA_TCR7_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR7_MASK_13 (ULONG)(0x7)


#define DMA_TCR7_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR7_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR7_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR7_ST_MASK (ULONG)(0x1)


#define DMA_TCR7_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR7_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR7_RD(v);\
	v = (v & (DMA_TCR7_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR7_MASK_5))<<5);\
	v = (v & (DMA_TCR7_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR7_MASK_13))<<13);\
	v = (v & (DMA_TCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR7_MASK_22))<<22);\
	v = ((v & DMA_TCR7_ST_WR_MASK)\
	|((data & DMA_TCR7_ST_MASK)<<0));\
	DMA_TCR7_WR(v);\
} while (0)

#define DMA_TCR7_ST_RD(data) do {\
	DMA_TCR7_RD(data);\
	data = ((data >> 0) & DMA_TCR7_ST_MASK);\
} while (0)


#define DMA_TCR7_TCW_MASK (ULONG)(0x7)


#define DMA_TCR7_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR7_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR7_RD(v);\
	v = (v & (DMA_TCR7_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR7_MASK_5))<<5);\
	v = (v & (DMA_TCR7_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR7_MASK_13))<<13);\
	v = (v & (DMA_TCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR7_MASK_22))<<22);\
	v = ((v & DMA_TCR7_TCW_WR_MASK)\
	|((data & DMA_TCR7_TCW_MASK)<<1));\
	DMA_TCR7_WR(v);\
} while (0)

#define DMA_TCR7_TCW_RD(data) do {\
	DMA_TCR7_RD(data);\
	data = ((data >> 1) & DMA_TCR7_TCW_MASK);\
} while (0)


#define DMA_TCR7_OSP_MASK (ULONG)(0x1)


#define DMA_TCR7_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR7_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR7_RD(v);\
	v = (v & (DMA_TCR7_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR7_MASK_5))<<5);\
	v = (v & (DMA_TCR7_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR7_MASK_13))<<13);\
	v = (v & (DMA_TCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR7_MASK_22))<<22);\
	v = ((v & DMA_TCR7_OSP_WR_MASK)\
	|((data & DMA_TCR7_OSP_MASK)<<4));\
	DMA_TCR7_WR(v);\
} while (0)

#define DMA_TCR7_OSP_RD(data) do {\
	DMA_TCR7_RD(data);\
	data = ((data >> 4) & DMA_TCR7_OSP_MASK);\
} while (0)


#define DMA_TCR7_TSE_MASK (ULONG)(0x1)


#define DMA_TCR7_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR7_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR7_RD(v);\
	v = (v & (DMA_TCR7_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR7_MASK_5))<<5);\
	v = (v & (DMA_TCR7_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR7_MASK_13))<<13);\
	v = (v & (DMA_TCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR7_MASK_22))<<22);\
	v = ((v & DMA_TCR7_TSE_WR_MASK)\
	|((data & DMA_TCR7_TSE_MASK)<<12));\
	DMA_TCR7_WR(v);\
} while (0)

#define DMA_TCR7_TSE_RD(data) do {\
	DMA_TCR7_RD(data);\
	data = ((data >> 12) & DMA_TCR7_TSE_MASK);\
} while (0)


#define DMA_TCR7_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR7_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR7_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR7_RD(v);\
	v = (v & (DMA_TCR7_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR7_MASK_5))<<5);\
	v = (v & (DMA_TCR7_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR7_MASK_13))<<13);\
	v = (v & (DMA_TCR7_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR7_MASK_22))<<22);\
	v = ((v & DMA_TCR7_PBL_WR_MASK)\
	|((data & DMA_TCR7_PBL_MASK)<<16));\
	DMA_TCR7_WR(v);\
} while (0)

#define DMA_TCR7_PBL_RD(data) do {\
	DMA_TCR7_RD(data);\
	data = ((data >> 16) & DMA_TCR7_PBL_MASK);\
} while (0)

#define DMA_TCR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1404))

#define DMA_TCR6_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR6_OFFSET);\
} while (0)

#define DMA_TCR6_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR6_OFFSET);\
} while (0)


#define  DMA_TCR6_MASK_5 (ULONG)(0x7f)


#define DMA_TCR6_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR6_MASK_13 (ULONG)(0x7)


#define DMA_TCR6_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR6_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR6_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR6_ST_MASK (ULONG)(0x1)


#define DMA_TCR6_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR6_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR6_RD(v);\
	v = (v & (DMA_TCR6_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR6_MASK_5))<<5);\
	v = (v & (DMA_TCR6_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR6_MASK_13))<<13);\
	v = (v & (DMA_TCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR6_MASK_22))<<22);\
	v = ((v & DMA_TCR6_ST_WR_MASK)\
	|((data & DMA_TCR6_ST_MASK)<<0));\
	DMA_TCR6_WR(v);\
} while (0)

#define DMA_TCR6_ST_RD(data) do {\
	DMA_TCR6_RD(data);\
	data = ((data >> 0) & DMA_TCR6_ST_MASK);\
} while (0)


#define DMA_TCR6_TCW_MASK (ULONG)(0x7)


#define DMA_TCR6_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR6_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR6_RD(v);\
	v = (v & (DMA_TCR6_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR6_MASK_5))<<5);\
	v = (v & (DMA_TCR6_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR6_MASK_13))<<13);\
	v = (v & (DMA_TCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR6_MASK_22))<<22);\
	v = ((v & DMA_TCR6_TCW_WR_MASK)\
	|((data & DMA_TCR6_TCW_MASK)<<1));\
	DMA_TCR6_WR(v);\
} while (0)

#define DMA_TCR6_TCW_RD(data) do {\
	DMA_TCR6_RD(data);\
	data = ((data >> 1) & DMA_TCR6_TCW_MASK);\
} while (0)


#define DMA_TCR6_OSP_MASK (ULONG)(0x1)


#define DMA_TCR6_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR6_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR6_RD(v);\
	v = (v & (DMA_TCR6_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR6_MASK_5))<<5);\
	v = (v & (DMA_TCR6_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR6_MASK_13))<<13);\
	v = (v & (DMA_TCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR6_MASK_22))<<22);\
	v = ((v & DMA_TCR6_OSP_WR_MASK)\
	|((data & DMA_TCR6_OSP_MASK)<<4));\
	DMA_TCR6_WR(v);\
} while (0)

#define DMA_TCR6_OSP_RD(data) do {\
	DMA_TCR6_RD(data);\
	data = ((data >> 4) & DMA_TCR6_OSP_MASK);\
} while (0)


#define DMA_TCR6_TSE_MASK (ULONG)(0x1)


#define DMA_TCR6_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR6_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR6_RD(v);\
	v = (v & (DMA_TCR6_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR6_MASK_5))<<5);\
	v = (v & (DMA_TCR6_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR6_MASK_13))<<13);\
	v = (v & (DMA_TCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR6_MASK_22))<<22);\
	v = ((v & DMA_TCR6_TSE_WR_MASK)\
	|((data & DMA_TCR6_TSE_MASK)<<12));\
	DMA_TCR6_WR(v);\
} while (0)

#define DMA_TCR6_TSE_RD(data) do {\
	DMA_TCR6_RD(data);\
	data = ((data >> 12) & DMA_TCR6_TSE_MASK);\
} while (0)


#define DMA_TCR6_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR6_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR6_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR6_RD(v);\
	v = (v & (DMA_TCR6_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR6_MASK_5))<<5);\
	v = (v & (DMA_TCR6_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR6_MASK_13))<<13);\
	v = (v & (DMA_TCR6_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR6_MASK_22))<<22);\
	v = ((v & DMA_TCR6_PBL_WR_MASK)\
	|((data & DMA_TCR6_PBL_MASK)<<16));\
	DMA_TCR6_WR(v);\
} while (0)

#define DMA_TCR6_PBL_RD(data) do {\
	DMA_TCR6_RD(data);\
	data = ((data >> 16) & DMA_TCR6_PBL_MASK);\
} while (0)

#define DMA_TCR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1384))

#define DMA_TCR5_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR5_OFFSET);\
} while (0)

#define DMA_TCR5_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR5_OFFSET);\
} while (0)


#define  DMA_TCR5_MASK_5 (ULONG)(0x7f)


#define DMA_TCR5_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR5_MASK_13 (ULONG)(0x7)


#define DMA_TCR5_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR5_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR5_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR5_ST_MASK (ULONG)(0x1)


#define DMA_TCR5_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR5_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR5_RD(v);\
	v = (v & (DMA_TCR5_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR5_MASK_5))<<5);\
	v = (v & (DMA_TCR5_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR5_MASK_13))<<13);\
	v = (v & (DMA_TCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR5_MASK_22))<<22);\
	v = ((v & DMA_TCR5_ST_WR_MASK)\
	|((data & DMA_TCR5_ST_MASK)<<0));\
	DMA_TCR5_WR(v);\
} while (0)

#define DMA_TCR5_ST_RD(data) do {\
	DMA_TCR5_RD(data);\
	data = ((data >> 0) & DMA_TCR5_ST_MASK);\
} while (0)


#define DMA_TCR5_TCW_MASK (ULONG)(0x7)


#define DMA_TCR5_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR5_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR5_RD(v);\
	v = (v & (DMA_TCR5_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR5_MASK_5))<<5);\
	v = (v & (DMA_TCR5_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR5_MASK_13))<<13);\
	v = (v & (DMA_TCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR5_MASK_22))<<22);\
	v = ((v & DMA_TCR5_TCW_WR_MASK)\
	|((data & DMA_TCR5_TCW_MASK)<<1));\
	DMA_TCR5_WR(v);\
} while (0)

#define DMA_TCR5_TCW_RD(data) do {\
	DMA_TCR5_RD(data);\
	data = ((data >> 1) & DMA_TCR5_TCW_MASK);\
} while (0)


#define DMA_TCR5_OSP_MASK (ULONG)(0x1)


#define DMA_TCR5_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR5_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR5_RD(v);\
	v = (v & (DMA_TCR5_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR5_MASK_5))<<5);\
	v = (v & (DMA_TCR5_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR5_MASK_13))<<13);\
	v = (v & (DMA_TCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR5_MASK_22))<<22);\
	v = ((v & DMA_TCR5_OSP_WR_MASK)\
	|((data & DMA_TCR5_OSP_MASK)<<4));\
	DMA_TCR5_WR(v);\
} while (0)

#define DMA_TCR5_OSP_RD(data) do {\
	DMA_TCR5_RD(data);\
	data = ((data >> 4) & DMA_TCR5_OSP_MASK);\
} while (0)


#define DMA_TCR5_TSE_MASK (ULONG)(0x1)


#define DMA_TCR5_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR5_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR5_RD(v);\
	v = (v & (DMA_TCR5_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR5_MASK_5))<<5);\
	v = (v & (DMA_TCR5_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR5_MASK_13))<<13);\
	v = (v & (DMA_TCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR5_MASK_22))<<22);\
	v = ((v & DMA_TCR5_TSE_WR_MASK)\
	|((data & DMA_TCR5_TSE_MASK)<<12));\
	DMA_TCR5_WR(v);\
} while (0)

#define DMA_TCR5_TSE_RD(data) do {\
	DMA_TCR5_RD(data);\
	data = ((data >> 12) & DMA_TCR5_TSE_MASK);\
} while (0)


#define DMA_TCR5_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR5_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR5_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR5_RD(v);\
	v = (v & (DMA_TCR5_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR5_MASK_5))<<5);\
	v = (v & (DMA_TCR5_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR5_MASK_13))<<13);\
	v = (v & (DMA_TCR5_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR5_MASK_22))<<22);\
	v = ((v & DMA_TCR5_PBL_WR_MASK)\
	|((data & DMA_TCR5_PBL_MASK)<<16));\
	DMA_TCR5_WR(v);\
} while (0)

#define DMA_TCR5_PBL_RD(data) do {\
	DMA_TCR5_RD(data);\
	data = ((data >> 16) & DMA_TCR5_PBL_MASK);\
} while (0)

#define DMA_TCR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1304))

#define DMA_TCR4_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR4_OFFSET);\
} while (0)

#define DMA_TCR4_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR4_OFFSET);\
} while (0)


#define  DMA_TCR4_MASK_5 (ULONG)(0x7f)


#define DMA_TCR4_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR4_MASK_13 (ULONG)(0x7)


#define DMA_TCR4_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR4_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR4_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR4_ST_MASK (ULONG)(0x1)


#define DMA_TCR4_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR4_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR4_RD(v);\
	v = (v & (DMA_TCR4_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR4_MASK_5))<<5);\
	v = (v & (DMA_TCR4_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR4_MASK_13))<<13);\
	v = (v & (DMA_TCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR4_MASK_22))<<22);\
	v = ((v & DMA_TCR4_ST_WR_MASK)\
	|((data & DMA_TCR4_ST_MASK)<<0));\
	DMA_TCR4_WR(v);\
} while (0)

#define DMA_TCR4_ST_RD(data) do {\
	DMA_TCR4_RD(data);\
	data = ((data >> 0) & DMA_TCR4_ST_MASK);\
} while (0)


#define DMA_TCR4_TCW_MASK (ULONG)(0x7)


#define DMA_TCR4_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR4_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR4_RD(v);\
	v = (v & (DMA_TCR4_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR4_MASK_5))<<5);\
	v = (v & (DMA_TCR4_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR4_MASK_13))<<13);\
	v = (v & (DMA_TCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR4_MASK_22))<<22);\
	v = ((v & DMA_TCR4_TCW_WR_MASK)\
	|((data & DMA_TCR4_TCW_MASK)<<1));\
	DMA_TCR4_WR(v);\
} while (0)

#define DMA_TCR4_TCW_RD(data) do {\
	DMA_TCR4_RD(data);\
	data = ((data >> 1) & DMA_TCR4_TCW_MASK);\
} while (0)


#define DMA_TCR4_OSP_MASK (ULONG)(0x1)


#define DMA_TCR4_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR4_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR4_RD(v);\
	v = (v & (DMA_TCR4_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR4_MASK_5))<<5);\
	v = (v & (DMA_TCR4_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR4_MASK_13))<<13);\
	v = (v & (DMA_TCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR4_MASK_22))<<22);\
	v = ((v & DMA_TCR4_OSP_WR_MASK)\
	|((data & DMA_TCR4_OSP_MASK)<<4));\
	DMA_TCR4_WR(v);\
} while (0)

#define DMA_TCR4_OSP_RD(data) do {\
	DMA_TCR4_RD(data);\
	data = ((data >> 4) & DMA_TCR4_OSP_MASK);\
} while (0)


#define DMA_TCR4_TSE_MASK (ULONG)(0x1)


#define DMA_TCR4_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR4_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR4_RD(v);\
	v = (v & (DMA_TCR4_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR4_MASK_5))<<5);\
	v = (v & (DMA_TCR4_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR4_MASK_13))<<13);\
	v = (v & (DMA_TCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR4_MASK_22))<<22);\
	v = ((v & DMA_TCR4_TSE_WR_MASK)\
	|((data & DMA_TCR4_TSE_MASK)<<12));\
	DMA_TCR4_WR(v);\
} while (0)

#define DMA_TCR4_TSE_RD(data) do {\
	DMA_TCR4_RD(data);\
	data = ((data >> 12) & DMA_TCR4_TSE_MASK);\
} while (0)


#define DMA_TCR4_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR4_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR4_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR4_RD(v);\
	v = (v & (DMA_TCR4_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR4_MASK_5))<<5);\
	v = (v & (DMA_TCR4_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR4_MASK_13))<<13);\
	v = (v & (DMA_TCR4_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR4_MASK_22))<<22);\
	v = ((v & DMA_TCR4_PBL_WR_MASK)\
	|((data & DMA_TCR4_PBL_MASK)<<16));\
	DMA_TCR4_WR(v);\
} while (0)

#define DMA_TCR4_PBL_RD(data) do {\
	DMA_TCR4_RD(data);\
	data = ((data >> 16) & DMA_TCR4_PBL_MASK);\
} while (0)

#define DMA_TCR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1284))

#define DMA_TCR3_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR3_OFFSET);\
} while (0)

#define DMA_TCR3_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR3_OFFSET);\
} while (0)


#define  DMA_TCR3_MASK_5 (ULONG)(0x7f)


#define DMA_TCR3_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR3_MASK_13 (ULONG)(0x7)


#define DMA_TCR3_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR3_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR3_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR3_ST_MASK (ULONG)(0x1)


#define DMA_TCR3_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR3_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR3_RD(v);\
	v = (v & (DMA_TCR3_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR3_MASK_5))<<5);\
	v = (v & (DMA_TCR3_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR3_MASK_13))<<13);\
	v = (v & (DMA_TCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR3_MASK_22))<<22);\
	v = ((v & DMA_TCR3_ST_WR_MASK)\
	|((data & DMA_TCR3_ST_MASK)<<0));\
	DMA_TCR3_WR(v);\
} while (0)

#define DMA_TCR3_ST_RD(data) do {\
	DMA_TCR3_RD(data);\
	data = ((data >> 0) & DMA_TCR3_ST_MASK);\
} while (0)


#define DMA_TCR3_TCW_MASK (ULONG)(0x7)


#define DMA_TCR3_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR3_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR3_RD(v);\
	v = (v & (DMA_TCR3_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR3_MASK_5))<<5);\
	v = (v & (DMA_TCR3_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR3_MASK_13))<<13);\
	v = (v & (DMA_TCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR3_MASK_22))<<22);\
	v = ((v & DMA_TCR3_TCW_WR_MASK)\
	|((data & DMA_TCR3_TCW_MASK)<<1));\
	DMA_TCR3_WR(v);\
} while (0)

#define DMA_TCR3_TCW_RD(data) do {\
	DMA_TCR3_RD(data);\
	data = ((data >> 1) & DMA_TCR3_TCW_MASK);\
} while (0)


#define DMA_TCR3_OSP_MASK (ULONG)(0x1)


#define DMA_TCR3_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR3_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR3_RD(v);\
	v = (v & (DMA_TCR3_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR3_MASK_5))<<5);\
	v = (v & (DMA_TCR3_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR3_MASK_13))<<13);\
	v = (v & (DMA_TCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR3_MASK_22))<<22);\
	v = ((v & DMA_TCR3_OSP_WR_MASK)\
	|((data & DMA_TCR3_OSP_MASK)<<4));\
	DMA_TCR3_WR(v);\
} while (0)

#define DMA_TCR3_OSP_RD(data) do {\
	DMA_TCR3_RD(data);\
	data = ((data >> 4) & DMA_TCR3_OSP_MASK);\
} while (0)


#define DMA_TCR3_TSE_MASK (ULONG)(0x1)


#define DMA_TCR3_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR3_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR3_RD(v);\
	v = (v & (DMA_TCR3_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR3_MASK_5))<<5);\
	v = (v & (DMA_TCR3_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR3_MASK_13))<<13);\
	v = (v & (DMA_TCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR3_MASK_22))<<22);\
	v = ((v & DMA_TCR3_TSE_WR_MASK)\
	|((data & DMA_TCR3_TSE_MASK)<<12));\
	DMA_TCR3_WR(v);\
} while (0)

#define DMA_TCR3_TSE_RD(data) do {\
	DMA_TCR3_RD(data);\
	data = ((data >> 12) & DMA_TCR3_TSE_MASK);\
} while (0)


#define DMA_TCR3_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR3_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR3_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR3_RD(v);\
	v = (v & (DMA_TCR3_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR3_MASK_5))<<5);\
	v = (v & (DMA_TCR3_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR3_MASK_13))<<13);\
	v = (v & (DMA_TCR3_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR3_MASK_22))<<22);\
	v = ((v & DMA_TCR3_PBL_WR_MASK)\
	|((data & DMA_TCR3_PBL_MASK)<<16));\
	DMA_TCR3_WR(v);\
} while (0)

#define DMA_TCR3_PBL_RD(data) do {\
	DMA_TCR3_RD(data);\
	data = ((data >> 16) & DMA_TCR3_PBL_MASK);\
} while (0)

#define DMA_TCR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1204))

#define DMA_TCR2_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR2_OFFSET);\
} while (0)

#define DMA_TCR2_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR2_OFFSET);\
} while (0)


#define  DMA_TCR2_MASK_5 (ULONG)(0x7f)


#define DMA_TCR2_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR2_MASK_13 (ULONG)(0x7)


#define DMA_TCR2_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR2_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR2_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR2_ST_MASK (ULONG)(0x1)


#define DMA_TCR2_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR2_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR2_RD(v);\
	v = (v & (DMA_TCR2_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR2_MASK_5))<<5);\
	v = (v & (DMA_TCR2_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR2_MASK_13))<<13);\
	v = (v & (DMA_TCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR2_MASK_22))<<22);\
	v = ((v & DMA_TCR2_ST_WR_MASK)\
	|((data & DMA_TCR2_ST_MASK)<<0));\
	DMA_TCR2_WR(v);\
} while (0)

#define DMA_TCR2_ST_RD(data) do {\
	DMA_TCR2_RD(data);\
	data = ((data >> 0) & DMA_TCR2_ST_MASK);\
} while (0)


#define DMA_TCR2_TCW_MASK (ULONG)(0x7)


#define DMA_TCR2_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR2_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR2_RD(v);\
	v = (v & (DMA_TCR2_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR2_MASK_5))<<5);\
	v = (v & (DMA_TCR2_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR2_MASK_13))<<13);\
	v = (v & (DMA_TCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR2_MASK_22))<<22);\
	v = ((v & DMA_TCR2_TCW_WR_MASK)\
	|((data & DMA_TCR2_TCW_MASK)<<1));\
	DMA_TCR2_WR(v);\
} while (0)

#define DMA_TCR2_TCW_RD(data) do {\
	DMA_TCR2_RD(data);\
	data = ((data >> 1) & DMA_TCR2_TCW_MASK);\
} while (0)


#define DMA_TCR2_OSP_MASK (ULONG)(0x1)


#define DMA_TCR2_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR2_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR2_RD(v);\
	v = (v & (DMA_TCR2_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR2_MASK_5))<<5);\
	v = (v & (DMA_TCR2_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR2_MASK_13))<<13);\
	v = (v & (DMA_TCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR2_MASK_22))<<22);\
	v = ((v & DMA_TCR2_OSP_WR_MASK)\
	|((data & DMA_TCR2_OSP_MASK)<<4));\
	DMA_TCR2_WR(v);\
} while (0)

#define DMA_TCR2_OSP_RD(data) do {\
	DMA_TCR2_RD(data);\
	data = ((data >> 4) & DMA_TCR2_OSP_MASK);\
} while (0)


#define DMA_TCR2_TSE_MASK (ULONG)(0x1)


#define DMA_TCR2_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR2_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR2_RD(v);\
	v = (v & (DMA_TCR2_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR2_MASK_5))<<5);\
	v = (v & (DMA_TCR2_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR2_MASK_13))<<13);\
	v = (v & (DMA_TCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR2_MASK_22))<<22);\
	v = ((v & DMA_TCR2_TSE_WR_MASK)\
	|((data & DMA_TCR2_TSE_MASK)<<12));\
	DMA_TCR2_WR(v);\
} while (0)

#define DMA_TCR2_TSE_RD(data) do {\
	DMA_TCR2_RD(data);\
	data = ((data >> 12) & DMA_TCR2_TSE_MASK);\
} while (0)


#define DMA_TCR2_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR2_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR2_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR2_RD(v);\
	v = (v & (DMA_TCR2_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR2_MASK_5))<<5);\
	v = (v & (DMA_TCR2_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR2_MASK_13))<<13);\
	v = (v & (DMA_TCR2_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR2_MASK_22))<<22);\
	v = ((v & DMA_TCR2_PBL_WR_MASK)\
	|((data & DMA_TCR2_PBL_MASK)<<16));\
	DMA_TCR2_WR(v);\
} while (0)

#define DMA_TCR2_PBL_RD(data) do {\
	DMA_TCR2_RD(data);\
	data = ((data >> 16) & DMA_TCR2_PBL_MASK);\
} while (0)

#define DMA_TCR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1184))

#define DMA_TCR1_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR1_OFFSET);\
} while (0)

#define DMA_TCR1_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR1_OFFSET);\
} while (0)


#define  DMA_TCR1_MASK_5 (ULONG)(0x7f)


#define DMA_TCR1_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR1_MASK_13 (ULONG)(0x7)


#define DMA_TCR1_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR1_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR1_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR1_ST_MASK (ULONG)(0x1)


#define DMA_TCR1_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR1_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR1_RD(v);\
	v = (v & (DMA_TCR1_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR1_MASK_5))<<5);\
	v = (v & (DMA_TCR1_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR1_MASK_13))<<13);\
	v = (v & (DMA_TCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR1_MASK_22))<<22);\
	v = ((v & DMA_TCR1_ST_WR_MASK)\
	|((data & DMA_TCR1_ST_MASK)<<0));\
	DMA_TCR1_WR(v);\
} while (0)

#define DMA_TCR1_ST_RD(data) do {\
	DMA_TCR1_RD(data);\
	data = ((data >> 0) & DMA_TCR1_ST_MASK);\
} while (0)


#define DMA_TCR1_TCW_MASK (ULONG)(0x7)


#define DMA_TCR1_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR1_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR1_RD(v);\
	v = (v & (DMA_TCR1_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR1_MASK_5))<<5);\
	v = (v & (DMA_TCR1_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR1_MASK_13))<<13);\
	v = (v & (DMA_TCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR1_MASK_22))<<22);\
	v = ((v & DMA_TCR1_TCW_WR_MASK)\
	|((data & DMA_TCR1_TCW_MASK)<<1));\
	DMA_TCR1_WR(v);\
} while (0)

#define DMA_TCR1_TCW_RD(data) do {\
	DMA_TCR1_RD(data);\
	data = ((data >> 1) & DMA_TCR1_TCW_MASK);\
} while (0)


#define DMA_TCR1_OSP_MASK (ULONG)(0x1)


#define DMA_TCR1_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR1_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR1_RD(v);\
	v = (v & (DMA_TCR1_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR1_MASK_5))<<5);\
	v = (v & (DMA_TCR1_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR1_MASK_13))<<13);\
	v = (v & (DMA_TCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR1_MASK_22))<<22);\
	v = ((v & DMA_TCR1_OSP_WR_MASK)\
	|((data & DMA_TCR1_OSP_MASK)<<4));\
	DMA_TCR1_WR(v);\
} while (0)

#define DMA_TCR1_OSP_RD(data) do {\
	DMA_TCR1_RD(data);\
	data = ((data >> 4) & DMA_TCR1_OSP_MASK);\
} while (0)


#define DMA_TCR1_TSE_MASK (ULONG)(0x1)


#define DMA_TCR1_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR1_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR1_RD(v);\
	v = (v & (DMA_TCR1_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR1_MASK_5))<<5);\
	v = (v & (DMA_TCR1_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR1_MASK_13))<<13);\
	v = (v & (DMA_TCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR1_MASK_22))<<22);\
	v = ((v & DMA_TCR1_TSE_WR_MASK)\
	|((data & DMA_TCR1_TSE_MASK)<<12));\
	DMA_TCR1_WR(v);\
} while (0)

#define DMA_TCR1_TSE_RD(data) do {\
	DMA_TCR1_RD(data);\
	data = ((data >> 12) & DMA_TCR1_TSE_MASK);\
} while (0)


#define DMA_TCR1_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR1_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR1_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR1_RD(v);\
	v = (v & (DMA_TCR1_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR1_MASK_5))<<5);\
	v = (v & (DMA_TCR1_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR1_MASK_13))<<13);\
	v = (v & (DMA_TCR1_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR1_MASK_22))<<22);\
	v = ((v & DMA_TCR1_PBL_WR_MASK)\
	|((data & DMA_TCR1_PBL_MASK)<<16));\
	DMA_TCR1_WR(v);\
} while (0)

#define DMA_TCR1_PBL_RD(data) do {\
	DMA_TCR1_RD(data);\
	data = ((data >> 16) & DMA_TCR1_PBL_MASK);\
} while (0)

#define DMA_TCR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1104))

#define DMA_TCR0_WR(data) do {\
	iowrite32(data, (void *)DMA_TCR0_OFFSET);\
} while (0)

#define DMA_TCR0_RD(data) do {\
	(data) = ioread32((void *)DMA_TCR0_OFFSET);\
} while (0)


#define  DMA_TCR0_MASK_5 (ULONG)(0x7f)


#define DMA_TCR0_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define  DMA_TCR0_MASK_13 (ULONG)(0x7)


#define DMA_TCR0_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR0_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR0_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define DMA_TCR0_ST_MASK (ULONG)(0x1)


#define DMA_TCR0_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR0_ST_WR(data) do {\
	ULONG v;\
	DMA_TCR0_RD(v);\
	v = (v & (DMA_TCR0_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR0_MASK_5))<<5);\
	v = (v & (DMA_TCR0_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR0_MASK_13))<<13);\
	v = (v & (DMA_TCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR0_MASK_22))<<22);\
	v = ((v & DMA_TCR0_ST_WR_MASK)\
	|((data & DMA_TCR0_ST_MASK)<<0));\
	DMA_TCR0_WR(v);\
} while (0)

#define DMA_TCR0_ST_RD(data) do {\
	DMA_TCR0_RD(data);\
	data = ((data >> 0) & DMA_TCR0_ST_MASK);\
} while (0)


#define DMA_TCR0_TCW_MASK (ULONG)(0x7)


#define DMA_TCR0_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR0_TCW_WR(data) do {\
	ULONG v;\
	DMA_TCR0_RD(v);\
	v = (v & (DMA_TCR0_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR0_MASK_5))<<5);\
	v = (v & (DMA_TCR0_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR0_MASK_13))<<13);\
	v = (v & (DMA_TCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR0_MASK_22))<<22);\
	v = ((v & DMA_TCR0_TCW_WR_MASK)\
	|((data & DMA_TCR0_TCW_MASK)<<1));\
	DMA_TCR0_WR(v);\
} while (0)

#define DMA_TCR0_TCW_RD(data) do {\
	DMA_TCR0_RD(data);\
	data = ((data >> 1) & DMA_TCR0_TCW_MASK);\
} while (0)


#define DMA_TCR0_OSP_MASK (ULONG)(0x1)


#define DMA_TCR0_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR0_OSP_WR(data) do {\
	ULONG v;\
	DMA_TCR0_RD(v);\
	v = (v & (DMA_TCR0_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR0_MASK_5))<<5);\
	v = (v & (DMA_TCR0_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR0_MASK_13))<<13);\
	v = (v & (DMA_TCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR0_MASK_22))<<22);\
	v = ((v & DMA_TCR0_OSP_WR_MASK)\
	|((data & DMA_TCR0_OSP_MASK)<<4));\
	DMA_TCR0_WR(v);\
} while (0)

#define DMA_TCR0_OSP_RD(data) do {\
	DMA_TCR0_RD(data);\
	data = ((data >> 4) & DMA_TCR0_OSP_MASK);\
} while (0)


#define DMA_TCR0_TSE_MASK (ULONG)(0x1)


#define DMA_TCR0_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR0_TSE_WR(data) do {\
	ULONG v;\
	DMA_TCR0_RD(v);\
	v = (v & (DMA_TCR0_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR0_MASK_5))<<5);\
	v = (v & (DMA_TCR0_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR0_MASK_13))<<13);\
	v = (v & (DMA_TCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR0_MASK_22))<<22);\
	v = ((v & DMA_TCR0_TSE_WR_MASK)\
	|((data & DMA_TCR0_TSE_MASK)<<12));\
	DMA_TCR0_WR(v);\
} while (0)

#define DMA_TCR0_TSE_RD(data) do {\
	DMA_TCR0_RD(data);\
	data = ((data >> 12) & DMA_TCR0_TSE_MASK);\
} while (0)


#define DMA_TCR0_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR0_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR0_PBL_WR(data) do {\
	ULONG v;\
	DMA_TCR0_RD(v);\
	v = (v & (DMA_TCR0_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR0_MASK_5))<<5);\
	v = (v & (DMA_TCR0_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR0_MASK_13))<<13);\
	v = (v & (DMA_TCR0_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR0_MASK_22))<<22);\
	v = ((v & DMA_TCR0_PBL_WR_MASK)\
	|((data & DMA_TCR0_PBL_MASK)<<16));\
	DMA_TCR0_WR(v);\
} while (0)

#define DMA_TCR0_PBL_RD(data) do {\
	DMA_TCR0_RD(data);\
	data = ((data >> 16) & DMA_TCR0_PBL_MASK);\
} while (0)

#define DMA_CR7_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1480))

#define DMA_CR7_WR(data) do {\
	iowrite32(data, (void *)DMA_CR7_OFFSET);\
} while (0)

#define DMA_CR7_RD(data) do {\
	(data) = ioread32((void *)DMA_CR7_OFFSET);\
} while (0)


#define  DMA_CR7_MASK_21 (ULONG)(0x3)


#define DMA_CR7_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR7_MASK_25 (ULONG)(0x7f)


#define DMA_CR7_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR7_MSS_MASK (ULONG)(0xffff)


#define DMA_CR7_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR7_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR7_RD(v);\
	v = (v & (DMA_CR7_RES_WR_MASK_21))\
	|(((0) & (DMA_CR7_MASK_21))<<21);\
	v = (v & (DMA_CR7_RES_WR_MASK_25))\
	|(((0) & (DMA_CR7_MASK_25))<<25);\
	v = ((v & DMA_CR7_MSS_WR_MASK)\
	|((data & DMA_CR7_MSS_MASK)<<0));\
	DMA_CR7_WR(v);\
} while (0)

#define DMA_CR7_MSS_RD(data) do {\
	DMA_CR7_RD(data);\
	data = ((data >> 0) & DMA_CR7_MSS_MASK);\
} while (0)


#define DMA_CR7_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR7_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR7_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR7_RD(v);\
	v = (v & (DMA_CR7_RES_WR_MASK_21))\
	|(((0) & (DMA_CR7_MASK_21))<<21);\
	v = (v & (DMA_CR7_RES_WR_MASK_25))\
	|(((0) & (DMA_CR7_MASK_25))<<25);\
	v = ((v & DMA_CR7_PBLX8_WR_MASK)\
	|((data & DMA_CR7_PBLX8_MASK)<<16));\
	DMA_CR7_WR(v);\
} while (0)

#define DMA_CR7_PBLX8_RD(data) do {\
	DMA_CR7_RD(data);\
	data = ((data >> 16) & DMA_CR7_PBLX8_MASK);\
} while (0)


#define DMA_CR7_DPE_MASK (ULONG)(0x1)


#define DMA_CR7_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR7_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR7_RD(v);\
	v = (v & (DMA_CR7_RES_WR_MASK_21))\
	|(((0) & (DMA_CR7_MASK_21))<<21);\
	v = (v & (DMA_CR7_RES_WR_MASK_25))\
	|(((0) & (DMA_CR7_MASK_25))<<25);\
	v = ((v & DMA_CR7_DPE_WR_MASK)\
	|((data & DMA_CR7_DPE_MASK)<<17));\
	DMA_CR7_WR(v);\
} while (0)

#define DMA_CR7_DPE_RD(data) do {\
	DMA_CR7_RD(data);\
	data = ((data >> 17) & DMA_CR7_DPE_MASK);\
} while (0)


#define DMA_CR7_DSL_MASK (ULONG)(0x7)


#define DMA_CR7_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR7_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR7_RD(v);\
	v = (v & (DMA_CR7_RES_WR_MASK_21))\
	|(((0) & (DMA_CR7_MASK_21))<<21);\
	v = (v & (DMA_CR7_RES_WR_MASK_25))\
	|(((0) & (DMA_CR7_MASK_25))<<25);\
	v = ((v & DMA_CR7_DSL_WR_MASK)\
	|((data & DMA_CR7_DSL_MASK)<<18));\
	DMA_CR7_WR(v);\
} while (0)

#define DMA_CR7_DSL_RD(data) do {\
	DMA_CR7_RD(data);\
	data = ((data >> 18) & DMA_CR7_DSL_MASK);\
} while (0)


#define DMA_CR7_CH_MASK (ULONG)(0x1)


#define DMA_CR7_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR7_CH_WR(data) do {\
	ULONG v;\
	DMA_CR7_RD(v);\
	v = (v & (DMA_CR7_RES_WR_MASK_21))\
	|(((0) & (DMA_CR7_MASK_21))<<21);\
	v = (v & (DMA_CR7_RES_WR_MASK_25))\
	|(((0) & (DMA_CR7_MASK_25))<<25);\
	v = ((v & DMA_CR7_CH_WR_MASK)\
	|((data & DMA_CR7_CH_MASK)<<23));\
	DMA_CR7_WR(v);\
} while (0)

#define DMA_CR7_CH_RD(data) do {\
	DMA_CR7_RD(data);\
	data = ((data >> 23) & DMA_CR7_CH_MASK);\
} while (0)


#define DMA_CR7_SPH_MASK (ULONG)(0x1)


#define DMA_CR7_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR7_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR7_RD(v);\
	v = (v & (DMA_CR7_RES_WR_MASK_21))\
	|(((0) & (DMA_CR7_MASK_21))<<21);\
	v = (v & (DMA_CR7_RES_WR_MASK_25))\
	|(((0) & (DMA_CR7_MASK_25))<<25);\
	v = ((v & DMA_CR7_SPH_WR_MASK)\
	|((data & DMA_CR7_SPH_MASK)<<24));\
	DMA_CR7_WR(v);\
} while (0)

#define DMA_CR7_SPH_RD(data) do {\
	DMA_CR7_RD(data);\
	data = ((data >> 24) & DMA_CR7_SPH_MASK);\
} while (0)

#define DMA_CR6_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1400))

#define DMA_CR6_WR(data) do {\
	iowrite32(data, (void *)DMA_CR6_OFFSET);\
} while (0)

#define DMA_CR6_RD(data) do {\
	(data) = ioread32((void *)DMA_CR6_OFFSET);\
} while (0)


#define  DMA_CR6_MASK_21 (ULONG)(0x3)


#define DMA_CR6_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR6_MASK_25 (ULONG)(0x7f)


#define DMA_CR6_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR6_MSS_MASK (ULONG)(0xffff)


#define DMA_CR6_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR6_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR6_RD(v);\
	v = (v & (DMA_CR6_RES_WR_MASK_21))\
	|(((0) & (DMA_CR6_MASK_21))<<21);\
	v = (v & (DMA_CR6_RES_WR_MASK_25))\
	|(((0) & (DMA_CR6_MASK_25))<<25);\
	v = ((v & DMA_CR6_MSS_WR_MASK)\
	|((data & DMA_CR6_MSS_MASK)<<0));\
	DMA_CR6_WR(v);\
} while (0)

#define DMA_CR6_MSS_RD(data) do {\
	DMA_CR6_RD(data);\
	data = ((data >> 0) & DMA_CR6_MSS_MASK);\
} while (0)


#define DMA_CR6_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR6_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR6_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR6_RD(v);\
	v = (v & (DMA_CR6_RES_WR_MASK_21))\
	|(((0) & (DMA_CR6_MASK_21))<<21);\
	v = (v & (DMA_CR6_RES_WR_MASK_25))\
	|(((0) & (DMA_CR6_MASK_25))<<25);\
	v = ((v & DMA_CR6_PBLX8_WR_MASK)\
	|((data & DMA_CR6_PBLX8_MASK)<<16));\
	DMA_CR6_WR(v);\
} while (0)

#define DMA_CR6_PBLX8_RD(data) do {\
	DMA_CR6_RD(data);\
	data = ((data >> 16) & DMA_CR6_PBLX8_MASK);\
} while (0)


#define DMA_CR6_DPE_MASK (ULONG)(0x1)


#define DMA_CR6_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR6_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR6_RD(v);\
	v = (v & (DMA_CR6_RES_WR_MASK_21))\
	|(((0) & (DMA_CR6_MASK_21))<<21);\
	v = (v & (DMA_CR6_RES_WR_MASK_25))\
	|(((0) & (DMA_CR6_MASK_25))<<25);\
	v = ((v & DMA_CR6_DPE_WR_MASK)\
	|((data & DMA_CR6_DPE_MASK)<<17));\
	DMA_CR6_WR(v);\
} while (0)

#define DMA_CR6_DPE_RD(data) do {\
	DMA_CR6_RD(data);\
	data = ((data >> 17) & DMA_CR6_DPE_MASK);\
} while (0)


#define DMA_CR6_DSL_MASK (ULONG)(0x7)


#define DMA_CR6_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR6_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR6_RD(v);\
	v = (v & (DMA_CR6_RES_WR_MASK_21))\
	|(((0) & (DMA_CR6_MASK_21))<<21);\
	v = (v & (DMA_CR6_RES_WR_MASK_25))\
	|(((0) & (DMA_CR6_MASK_25))<<25);\
	v = ((v & DMA_CR6_DSL_WR_MASK)\
	|((data & DMA_CR6_DSL_MASK)<<18));\
	DMA_CR6_WR(v);\
} while (0)

#define DMA_CR6_DSL_RD(data) do {\
	DMA_CR6_RD(data);\
	data = ((data >> 18) & DMA_CR6_DSL_MASK);\
} while (0)


#define DMA_CR6_CH_MASK (ULONG)(0x1)


#define DMA_CR6_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR6_CH_WR(data) do {\
	ULONG v;\
	DMA_CR6_RD(v);\
	v = (v & (DMA_CR6_RES_WR_MASK_21))\
	|(((0) & (DMA_CR6_MASK_21))<<21);\
	v = (v & (DMA_CR6_RES_WR_MASK_25))\
	|(((0) & (DMA_CR6_MASK_25))<<25);\
	v = ((v & DMA_CR6_CH_WR_MASK)\
	|((data & DMA_CR6_CH_MASK)<<23));\
	DMA_CR6_WR(v);\
} while (0)

#define DMA_CR6_CH_RD(data) do {\
	DMA_CR6_RD(data);\
	data = ((data >> 23) & DMA_CR6_CH_MASK);\
} while (0)


#define DMA_CR6_SPH_MASK (ULONG)(0x1)


#define DMA_CR6_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR6_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR6_RD(v);\
	v = (v & (DMA_CR6_RES_WR_MASK_21))\
	|(((0) & (DMA_CR6_MASK_21))<<21);\
	v = (v & (DMA_CR6_RES_WR_MASK_25))\
	|(((0) & (DMA_CR6_MASK_25))<<25);\
	v = ((v & DMA_CR6_SPH_WR_MASK)\
	|((data & DMA_CR6_SPH_MASK)<<24));\
	DMA_CR6_WR(v);\
} while (0)

#define DMA_CR6_SPH_RD(data) do {\
	DMA_CR6_RD(data);\
	data = ((data >> 24) & DMA_CR6_SPH_MASK);\
} while (0)

#define DMA_CR5_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1380))

#define DMA_CR5_WR(data) do {\
	iowrite32(data, (void *)DMA_CR5_OFFSET);\
} while (0)

#define DMA_CR5_RD(data) do {\
	(data) = ioread32((void *)DMA_CR5_OFFSET);\
} while (0)


#define  DMA_CR5_MASK_21 (ULONG)(0x3)


#define DMA_CR5_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR5_MASK_25 (ULONG)(0x7f)


#define DMA_CR5_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR5_MSS_MASK (ULONG)(0xffff)


#define DMA_CR5_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR5_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR5_RD(v);\
	v = (v & (DMA_CR5_RES_WR_MASK_21))\
	|(((0) & (DMA_CR5_MASK_21))<<21);\
	v = (v & (DMA_CR5_RES_WR_MASK_25))\
	|(((0) & (DMA_CR5_MASK_25))<<25);\
	v = ((v & DMA_CR5_MSS_WR_MASK)\
	|((data & DMA_CR5_MSS_MASK)<<0));\
	DMA_CR5_WR(v);\
} while (0)

#define DMA_CR5_MSS_RD(data) do {\
	DMA_CR5_RD(data);\
	data = ((data >> 0) & DMA_CR5_MSS_MASK);\
} while (0)


#define DMA_CR5_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR5_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR5_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR5_RD(v);\
	v = (v & (DMA_CR5_RES_WR_MASK_21))\
	|(((0) & (DMA_CR5_MASK_21))<<21);\
	v = (v & (DMA_CR5_RES_WR_MASK_25))\
	|(((0) & (DMA_CR5_MASK_25))<<25);\
	v = ((v & DMA_CR5_PBLX8_WR_MASK)\
	|((data & DMA_CR5_PBLX8_MASK)<<16));\
	DMA_CR5_WR(v);\
} while (0)

#define DMA_CR5_PBLX8_RD(data) do {\
	DMA_CR5_RD(data);\
	data = ((data >> 16) & DMA_CR5_PBLX8_MASK);\
} while (0)


#define DMA_CR5_DPE_MASK (ULONG)(0x1)


#define DMA_CR5_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR5_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR5_RD(v);\
	v = (v & (DMA_CR5_RES_WR_MASK_21))\
	|(((0) & (DMA_CR5_MASK_21))<<21);\
	v = (v & (DMA_CR5_RES_WR_MASK_25))\
	|(((0) & (DMA_CR5_MASK_25))<<25);\
	v = ((v & DMA_CR5_DPE_WR_MASK)\
	|((data & DMA_CR5_DPE_MASK)<<17));\
	DMA_CR5_WR(v);\
} while (0)

#define DMA_CR5_DPE_RD(data) do {\
	DMA_CR5_RD(data);\
	data = ((data >> 17) & DMA_CR5_DPE_MASK);\
} while (0)


#define DMA_CR5_DSL_MASK (ULONG)(0x7)


#define DMA_CR5_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR5_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR5_RD(v);\
	v = (v & (DMA_CR5_RES_WR_MASK_21))\
	|(((0) & (DMA_CR5_MASK_21))<<21);\
	v = (v & (DMA_CR5_RES_WR_MASK_25))\
	|(((0) & (DMA_CR5_MASK_25))<<25);\
	v = ((v & DMA_CR5_DSL_WR_MASK)\
	|((data & DMA_CR5_DSL_MASK)<<18));\
	DMA_CR5_WR(v);\
} while (0)

#define DMA_CR5_DSL_RD(data) do {\
	DMA_CR5_RD(data);\
	data = ((data >> 18) & DMA_CR5_DSL_MASK);\
} while (0)


#define DMA_CR5_CH_MASK (ULONG)(0x1)


#define DMA_CR5_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR5_CH_WR(data) do {\
	ULONG v;\
	DMA_CR5_RD(v);\
	v = (v & (DMA_CR5_RES_WR_MASK_21))\
	|(((0) & (DMA_CR5_MASK_21))<<21);\
	v = (v & (DMA_CR5_RES_WR_MASK_25))\
	|(((0) & (DMA_CR5_MASK_25))<<25);\
	v = ((v & DMA_CR5_CH_WR_MASK)\
	|((data & DMA_CR5_CH_MASK)<<23));\
	DMA_CR5_WR(v);\
} while (0)

#define DMA_CR5_CH_RD(data) do {\
	DMA_CR5_RD(data);\
	data = ((data >> 23) & DMA_CR5_CH_MASK);\
} while (0)


#define DMA_CR5_SPH_MASK (ULONG)(0x1)


#define DMA_CR5_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR5_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR5_RD(v);\
	v = (v & (DMA_CR5_RES_WR_MASK_21))\
	|(((0) & (DMA_CR5_MASK_21))<<21);\
	v = (v & (DMA_CR5_RES_WR_MASK_25))\
	|(((0) & (DMA_CR5_MASK_25))<<25);\
	v = ((v & DMA_CR5_SPH_WR_MASK)\
	|((data & DMA_CR5_SPH_MASK)<<24));\
	DMA_CR5_WR(v);\
} while (0)

#define DMA_CR5_SPH_RD(data) do {\
	DMA_CR5_RD(data);\
	data = ((data >> 24) & DMA_CR5_SPH_MASK);\
} while (0)

#define DMA_CR4_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1300))

#define DMA_CR4_WR(data) do {\
	iowrite32(data, (void *)DMA_CR4_OFFSET);\
} while (0)

#define DMA_CR4_RD(data) do {\
	(data) = ioread32((void *)DMA_CR4_OFFSET);\
} while (0)


#define  DMA_CR4_MASK_21 (ULONG)(0x3)


#define DMA_CR4_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR4_MASK_25 (ULONG)(0x7f)


#define DMA_CR4_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR4_MSS_MASK (ULONG)(0xffff)


#define DMA_CR4_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR4_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR4_RD(v);\
	v = (v & (DMA_CR4_RES_WR_MASK_21))\
	|(((0) & (DMA_CR4_MASK_21))<<21);\
	v = (v & (DMA_CR4_RES_WR_MASK_25))\
	|(((0) & (DMA_CR4_MASK_25))<<25);\
	v = ((v & DMA_CR4_MSS_WR_MASK)\
	|((data & DMA_CR4_MSS_MASK)<<0));\
	DMA_CR4_WR(v);\
} while (0)

#define DMA_CR4_MSS_RD(data) do {\
	DMA_CR4_RD(data);\
	data = ((data >> 0) & DMA_CR4_MSS_MASK);\
} while (0)


#define DMA_CR4_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR4_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR4_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR4_RD(v);\
	v = (v & (DMA_CR4_RES_WR_MASK_21))\
	|(((0) & (DMA_CR4_MASK_21))<<21);\
	v = (v & (DMA_CR4_RES_WR_MASK_25))\
	|(((0) & (DMA_CR4_MASK_25))<<25);\
	v = ((v & DMA_CR4_PBLX8_WR_MASK)\
	|((data & DMA_CR4_PBLX8_MASK)<<16));\
	DMA_CR4_WR(v);\
} while (0)

#define DMA_CR4_PBLX8_RD(data) do {\
	DMA_CR4_RD(data);\
	data = ((data >> 16) & DMA_CR4_PBLX8_MASK);\
} while (0)


#define DMA_CR4_DPE_MASK (ULONG)(0x1)


#define DMA_CR4_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR4_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR4_RD(v);\
	v = (v & (DMA_CR4_RES_WR_MASK_21))\
	|(((0) & (DMA_CR4_MASK_21))<<21);\
	v = (v & (DMA_CR4_RES_WR_MASK_25))\
	|(((0) & (DMA_CR4_MASK_25))<<25);\
	v = ((v & DMA_CR4_DPE_WR_MASK)\
	|((data & DMA_CR4_DPE_MASK)<<17));\
	DMA_CR4_WR(v);\
} while (0)

#define DMA_CR4_DPE_RD(data) do {\
	DMA_CR4_RD(data);\
	data = ((data >> 17) & DMA_CR4_DPE_MASK);\
} while (0)


#define DMA_CR4_DSL_MASK (ULONG)(0x7)


#define DMA_CR4_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR4_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR4_RD(v);\
	v = (v & (DMA_CR4_RES_WR_MASK_21))\
	|(((0) & (DMA_CR4_MASK_21))<<21);\
	v = (v & (DMA_CR4_RES_WR_MASK_25))\
	|(((0) & (DMA_CR4_MASK_25))<<25);\
	v = ((v & DMA_CR4_DSL_WR_MASK)\
	|((data & DMA_CR4_DSL_MASK)<<18));\
	DMA_CR4_WR(v);\
} while (0)

#define DMA_CR4_DSL_RD(data) do {\
	DMA_CR4_RD(data);\
	data = ((data >> 18) & DMA_CR4_DSL_MASK);\
} while (0)


#define DMA_CR4_CH_MASK (ULONG)(0x1)


#define DMA_CR4_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR4_CH_WR(data) do {\
	ULONG v;\
	DMA_CR4_RD(v);\
	v = (v & (DMA_CR4_RES_WR_MASK_21))\
	|(((0) & (DMA_CR4_MASK_21))<<21);\
	v = (v & (DMA_CR4_RES_WR_MASK_25))\
	|(((0) & (DMA_CR4_MASK_25))<<25);\
	v = ((v & DMA_CR4_CH_WR_MASK)\
	|((data & DMA_CR4_CH_MASK)<<23));\
	DMA_CR4_WR(v);\
} while (0)

#define DMA_CR4_CH_RD(data) do {\
	DMA_CR4_RD(data);\
	data = ((data >> 23) & DMA_CR4_CH_MASK);\
} while (0)


#define DMA_CR4_SPH_MASK (ULONG)(0x1)


#define DMA_CR4_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR4_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR4_RD(v);\
	v = (v & (DMA_CR4_RES_WR_MASK_21))\
	|(((0) & (DMA_CR4_MASK_21))<<21);\
	v = (v & (DMA_CR4_RES_WR_MASK_25))\
	|(((0) & (DMA_CR4_MASK_25))<<25);\
	v = ((v & DMA_CR4_SPH_WR_MASK)\
	|((data & DMA_CR4_SPH_MASK)<<24));\
	DMA_CR4_WR(v);\
} while (0)

#define DMA_CR4_SPH_RD(data) do {\
	DMA_CR4_RD(data);\
	data = ((data >> 24) & DMA_CR4_SPH_MASK);\
} while (0)

#define DMA_CR3_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1280))

#define DMA_CR3_WR(data) do {\
	iowrite32(data, (void *)DMA_CR3_OFFSET);\
} while (0)

#define DMA_CR3_RD(data) do {\
	(data) = ioread32((void *)DMA_CR3_OFFSET);\
} while (0)


#define  DMA_CR3_MASK_21 (ULONG)(0x3)


#define DMA_CR3_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR3_MASK_25 (ULONG)(0x7f)


#define DMA_CR3_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR3_MSS_MASK (ULONG)(0xffff)


#define DMA_CR3_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR3_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR3_RD(v);\
	v = (v & (DMA_CR3_RES_WR_MASK_21))\
	|(((0) & (DMA_CR3_MASK_21))<<21);\
	v = (v & (DMA_CR3_RES_WR_MASK_25))\
	|(((0) & (DMA_CR3_MASK_25))<<25);\
	v = ((v & DMA_CR3_MSS_WR_MASK)\
	|((data & DMA_CR3_MSS_MASK)<<0));\
	DMA_CR3_WR(v);\
} while (0)

#define DMA_CR3_MSS_RD(data) do {\
	DMA_CR3_RD(data);\
	data = ((data >> 0) & DMA_CR3_MSS_MASK);\
} while (0)


#define DMA_CR3_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR3_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR3_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR3_RD(v);\
	v = (v & (DMA_CR3_RES_WR_MASK_21))\
	|(((0) & (DMA_CR3_MASK_21))<<21);\
	v = (v & (DMA_CR3_RES_WR_MASK_25))\
	|(((0) & (DMA_CR3_MASK_25))<<25);\
	v = ((v & DMA_CR3_PBLX8_WR_MASK)\
	|((data & DMA_CR3_PBLX8_MASK)<<16));\
	DMA_CR3_WR(v);\
} while (0)

#define DMA_CR3_PBLX8_RD(data) do {\
	DMA_CR3_RD(data);\
	data = ((data >> 16) & DMA_CR3_PBLX8_MASK);\
} while (0)


#define DMA_CR3_DPE_MASK (ULONG)(0x1)


#define DMA_CR3_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR3_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR3_RD(v);\
	v = (v & (DMA_CR3_RES_WR_MASK_21))\
	|(((0) & (DMA_CR3_MASK_21))<<21);\
	v = (v & (DMA_CR3_RES_WR_MASK_25))\
	|(((0) & (DMA_CR3_MASK_25))<<25);\
	v = ((v & DMA_CR3_DPE_WR_MASK)\
	|((data & DMA_CR3_DPE_MASK)<<17));\
	DMA_CR3_WR(v);\
} while (0)

#define DMA_CR3_DPE_RD(data) do {\
	DMA_CR3_RD(data);\
	data = ((data >> 17) & DMA_CR3_DPE_MASK);\
} while (0)


#define DMA_CR3_DSL_MASK (ULONG)(0x7)


#define DMA_CR3_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR3_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR3_RD(v);\
	v = (v & (DMA_CR3_RES_WR_MASK_21))\
	|(((0) & (DMA_CR3_MASK_21))<<21);\
	v = (v & (DMA_CR3_RES_WR_MASK_25))\
	|(((0) & (DMA_CR3_MASK_25))<<25);\
	v = ((v & DMA_CR3_DSL_WR_MASK)\
	|((data & DMA_CR3_DSL_MASK)<<18));\
	DMA_CR3_WR(v);\
} while (0)

#define DMA_CR3_DSL_RD(data) do {\
	DMA_CR3_RD(data);\
	data = ((data >> 18) & DMA_CR3_DSL_MASK);\
} while (0)


#define DMA_CR3_CH_MASK (ULONG)(0x1)


#define DMA_CR3_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR3_CH_WR(data) do {\
	ULONG v;\
	DMA_CR3_RD(v);\
	v = (v & (DMA_CR3_RES_WR_MASK_21))\
	|(((0) & (DMA_CR3_MASK_21))<<21);\
	v = (v & (DMA_CR3_RES_WR_MASK_25))\
	|(((0) & (DMA_CR3_MASK_25))<<25);\
	v = ((v & DMA_CR3_CH_WR_MASK)\
	|((data & DMA_CR3_CH_MASK)<<23));\
	DMA_CR3_WR(v);\
} while (0)

#define DMA_CR3_CH_RD(data) do {\
	DMA_CR3_RD(data);\
	data = ((data >> 23) & DMA_CR3_CH_MASK);\
} while (0)


#define DMA_CR3_SPH_MASK (ULONG)(0x1)


#define DMA_CR3_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR3_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR3_RD(v);\
	v = (v & (DMA_CR3_RES_WR_MASK_21))\
	|(((0) & (DMA_CR3_MASK_21))<<21);\
	v = (v & (DMA_CR3_RES_WR_MASK_25))\
	|(((0) & (DMA_CR3_MASK_25))<<25);\
	v = ((v & DMA_CR3_SPH_WR_MASK)\
	|((data & DMA_CR3_SPH_MASK)<<24));\
	DMA_CR3_WR(v);\
} while (0)

#define DMA_CR3_SPH_RD(data) do {\
	DMA_CR3_RD(data);\
	data = ((data >> 24) & DMA_CR3_SPH_MASK);\
} while (0)

#define DMA_CR2_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1200))

#define DMA_CR2_WR(data) do {\
	iowrite32(data, (void *)DMA_CR2_OFFSET);\
} while (0)

#define DMA_CR2_RD(data) do {\
	(data) = ioread32((void *)DMA_CR2_OFFSET);\
} while (0)


#define  DMA_CR2_MASK_21 (ULONG)(0x3)


#define DMA_CR2_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR2_MASK_25 (ULONG)(0x7f)


#define DMA_CR2_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR2_MSS_MASK (ULONG)(0xffff)


#define DMA_CR2_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR2_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR2_RD(v);\
	v = (v & (DMA_CR2_RES_WR_MASK_21))\
	|(((0) & (DMA_CR2_MASK_21))<<21);\
	v = (v & (DMA_CR2_RES_WR_MASK_25))\
	|(((0) & (DMA_CR2_MASK_25))<<25);\
	v = ((v & DMA_CR2_MSS_WR_MASK)\
	|((data & DMA_CR2_MSS_MASK)<<0));\
	DMA_CR2_WR(v);\
} while (0)

#define DMA_CR2_MSS_RD(data) do {\
	DMA_CR2_RD(data);\
	data = ((data >> 0) & DMA_CR2_MSS_MASK);\
} while (0)


#define DMA_CR2_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR2_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR2_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR2_RD(v);\
	v = (v & (DMA_CR2_RES_WR_MASK_21))\
	|(((0) & (DMA_CR2_MASK_21))<<21);\
	v = (v & (DMA_CR2_RES_WR_MASK_25))\
	|(((0) & (DMA_CR2_MASK_25))<<25);\
	v = ((v & DMA_CR2_PBLX8_WR_MASK)\
	|((data & DMA_CR2_PBLX8_MASK)<<16));\
	DMA_CR2_WR(v);\
} while (0)

#define DMA_CR2_PBLX8_RD(data) do {\
	DMA_CR2_RD(data);\
	data = ((data >> 16) & DMA_CR2_PBLX8_MASK);\
} while (0)


#define DMA_CR2_DPE_MASK (ULONG)(0x1)


#define DMA_CR2_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR2_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR2_RD(v);\
	v = (v & (DMA_CR2_RES_WR_MASK_21))\
	|(((0) & (DMA_CR2_MASK_21))<<21);\
	v = (v & (DMA_CR2_RES_WR_MASK_25))\
	|(((0) & (DMA_CR2_MASK_25))<<25);\
	v = ((v & DMA_CR2_DPE_WR_MASK)\
	|((data & DMA_CR2_DPE_MASK)<<17));\
	DMA_CR2_WR(v);\
} while (0)

#define DMA_CR2_DPE_RD(data) do {\
	DMA_CR2_RD(data);\
	data = ((data >> 17) & DMA_CR2_DPE_MASK);\
} while (0)


#define DMA_CR2_DSL_MASK (ULONG)(0x7)


#define DMA_CR2_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR2_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR2_RD(v);\
	v = (v & (DMA_CR2_RES_WR_MASK_21))\
	|(((0) & (DMA_CR2_MASK_21))<<21);\
	v = (v & (DMA_CR2_RES_WR_MASK_25))\
	|(((0) & (DMA_CR2_MASK_25))<<25);\
	v = ((v & DMA_CR2_DSL_WR_MASK)\
	|((data & DMA_CR2_DSL_MASK)<<18));\
	DMA_CR2_WR(v);\
} while (0)

#define DMA_CR2_DSL_RD(data) do {\
	DMA_CR2_RD(data);\
	data = ((data >> 18) & DMA_CR2_DSL_MASK);\
} while (0)


#define DMA_CR2_CH_MASK (ULONG)(0x1)


#define DMA_CR2_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR2_CH_WR(data) do {\
	ULONG v;\
	DMA_CR2_RD(v);\
	v = (v & (DMA_CR2_RES_WR_MASK_21))\
	|(((0) & (DMA_CR2_MASK_21))<<21);\
	v = (v & (DMA_CR2_RES_WR_MASK_25))\
	|(((0) & (DMA_CR2_MASK_25))<<25);\
	v = ((v & DMA_CR2_CH_WR_MASK)\
	|((data & DMA_CR2_CH_MASK)<<23));\
	DMA_CR2_WR(v);\
} while (0)

#define DMA_CR2_CH_RD(data) do {\
	DMA_CR2_RD(data);\
	data = ((data >> 23) & DMA_CR2_CH_MASK);\
} while (0)


#define DMA_CR2_SPH_MASK (ULONG)(0x1)


#define DMA_CR2_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR2_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR2_RD(v);\
	v = (v & (DMA_CR2_RES_WR_MASK_21))\
	|(((0) & (DMA_CR2_MASK_21))<<21);\
	v = (v & (DMA_CR2_RES_WR_MASK_25))\
	|(((0) & (DMA_CR2_MASK_25))<<25);\
	v = ((v & DMA_CR2_SPH_WR_MASK)\
	|((data & DMA_CR2_SPH_MASK)<<24));\
	DMA_CR2_WR(v);\
} while (0)

#define DMA_CR2_SPH_RD(data) do {\
	DMA_CR2_RD(data);\
	data = ((data >> 24) & DMA_CR2_SPH_MASK);\
} while (0)

#define DMA_CR1_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1180))

#define DMA_CR1_WR(data) do {\
	iowrite32(data, (void *)DMA_CR1_OFFSET);\
} while (0)

#define DMA_CR1_RD(data) do {\
	(data) = ioread32((void *)DMA_CR1_OFFSET);\
} while (0)


#define  DMA_CR1_MASK_21 (ULONG)(0x3)


#define DMA_CR1_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR1_MASK_25 (ULONG)(0x7f)


#define DMA_CR1_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR1_MSS_MASK (ULONG)(0xffff)


#define DMA_CR1_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR1_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR1_RD(v);\
	v = (v & (DMA_CR1_RES_WR_MASK_21))\
	|(((0) & (DMA_CR1_MASK_21))<<21);\
	v = (v & (DMA_CR1_RES_WR_MASK_25))\
	|(((0) & (DMA_CR1_MASK_25))<<25);\
	v = ((v & DMA_CR1_MSS_WR_MASK)\
	|((data & DMA_CR1_MSS_MASK)<<0));\
	DMA_CR1_WR(v);\
} while (0)

#define DMA_CR1_MSS_RD(data) do {\
	DMA_CR1_RD(data);\
	data = ((data >> 0) & DMA_CR1_MSS_MASK);\
} while (0)


#define DMA_CR1_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR1_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR1_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR1_RD(v);\
	v = (v & (DMA_CR1_RES_WR_MASK_21))\
	|(((0) & (DMA_CR1_MASK_21))<<21);\
	v = (v & (DMA_CR1_RES_WR_MASK_25))\
	|(((0) & (DMA_CR1_MASK_25))<<25);\
	v = ((v & DMA_CR1_PBLX8_WR_MASK)\
	|((data & DMA_CR1_PBLX8_MASK)<<16));\
	DMA_CR1_WR(v);\
} while (0)

#define DMA_CR1_PBLX8_RD(data) do {\
	DMA_CR1_RD(data);\
	data = ((data >> 16) & DMA_CR1_PBLX8_MASK);\
} while (0)


#define DMA_CR1_DPE_MASK (ULONG)(0x1)


#define DMA_CR1_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR1_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR1_RD(v);\
	v = (v & (DMA_CR1_RES_WR_MASK_21))\
	|(((0) & (DMA_CR1_MASK_21))<<21);\
	v = (v & (DMA_CR1_RES_WR_MASK_25))\
	|(((0) & (DMA_CR1_MASK_25))<<25);\
	v = ((v & DMA_CR1_DPE_WR_MASK)\
	|((data & DMA_CR1_DPE_MASK)<<17));\
	DMA_CR1_WR(v);\
} while (0)

#define DMA_CR1_DPE_RD(data) do {\
	DMA_CR1_RD(data);\
	data = ((data >> 17) & DMA_CR1_DPE_MASK);\
} while (0)


#define DMA_CR1_DSL_MASK (ULONG)(0x7)


#define DMA_CR1_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR1_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR1_RD(v);\
	v = (v & (DMA_CR1_RES_WR_MASK_21))\
	|(((0) & (DMA_CR1_MASK_21))<<21);\
	v = (v & (DMA_CR1_RES_WR_MASK_25))\
	|(((0) & (DMA_CR1_MASK_25))<<25);\
	v = ((v & DMA_CR1_DSL_WR_MASK)\
	|((data & DMA_CR1_DSL_MASK)<<18));\
	DMA_CR1_WR(v);\
} while (0)

#define DMA_CR1_DSL_RD(data) do {\
	DMA_CR1_RD(data);\
	data = ((data >> 18) & DMA_CR1_DSL_MASK);\
} while (0)


#define DMA_CR1_CH_MASK (ULONG)(0x1)


#define DMA_CR1_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR1_CH_WR(data) do {\
	ULONG v;\
	DMA_CR1_RD(v);\
	v = (v & (DMA_CR1_RES_WR_MASK_21))\
	|(((0) & (DMA_CR1_MASK_21))<<21);\
	v = (v & (DMA_CR1_RES_WR_MASK_25))\
	|(((0) & (DMA_CR1_MASK_25))<<25);\
	v = ((v & DMA_CR1_CH_WR_MASK)\
	|((data & DMA_CR1_CH_MASK)<<23));\
	DMA_CR1_WR(v);\
} while (0)

#define DMA_CR1_CH_RD(data) do {\
	DMA_CR1_RD(data);\
	data = ((data >> 23) & DMA_CR1_CH_MASK);\
} while (0)


#define DMA_CR1_SPH_MASK (ULONG)(0x1)


#define DMA_CR1_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR1_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR1_RD(v);\
	v = (v & (DMA_CR1_RES_WR_MASK_21))\
	|(((0) & (DMA_CR1_MASK_21))<<21);\
	v = (v & (DMA_CR1_RES_WR_MASK_25))\
	|(((0) & (DMA_CR1_MASK_25))<<25);\
	v = ((v & DMA_CR1_SPH_WR_MASK)\
	|((data & DMA_CR1_SPH_MASK)<<24));\
	DMA_CR1_WR(v);\
} while (0)

#define DMA_CR1_SPH_RD(data) do {\
	DMA_CR1_RD(data);\
	data = ((data >> 24) & DMA_CR1_SPH_MASK);\
} while (0)

#define DMA_CR0_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x1100))

#define DMA_CR0_WR(data) do {\
	iowrite32(data, (void *)DMA_CR0_OFFSET);\
} while (0)

#define DMA_CR0_RD(data) do {\
	(data) = ioread32((void *)DMA_CR0_OFFSET);\
} while (0)


#define  DMA_CR0_MASK_21 (ULONG)(0x3)


#define DMA_CR0_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define  DMA_CR0_MASK_25 (ULONG)(0x7f)


#define DMA_CR0_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define DMA_CR0_MSS_MASK (ULONG)(0xffff)


#define DMA_CR0_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR0_MSS_WR(data) do {\
	ULONG v;\
	DMA_CR0_RD(v);\
	v = (v & (DMA_CR0_RES_WR_MASK_21))\
	|(((0) & (DMA_CR0_MASK_21))<<21);\
	v = (v & (DMA_CR0_RES_WR_MASK_25))\
	|(((0) & (DMA_CR0_MASK_25))<<25);\
	v = ((v & DMA_CR0_MSS_WR_MASK)\
	|((data & DMA_CR0_MSS_MASK)<<0));\
	DMA_CR0_WR(v);\
} while (0)

#define DMA_CR0_MSS_RD(data) do {\
	DMA_CR0_RD(data);\
	data = ((data >> 0) & DMA_CR0_MSS_MASK);\
} while (0)


#define DMA_CR0_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR0_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR0_PBLX8_WR(data) do {\
	ULONG v;\
	DMA_CR0_RD(v);\
	v = (v & (DMA_CR0_RES_WR_MASK_21))\
	|(((0) & (DMA_CR0_MASK_21))<<21);\
	v = (v & (DMA_CR0_RES_WR_MASK_25))\
	|(((0) & (DMA_CR0_MASK_25))<<25);\
	v = ((v & DMA_CR0_PBLX8_WR_MASK)\
	|((data & DMA_CR0_PBLX8_MASK)<<16));\
	DMA_CR0_WR(v);\
} while (0)

#define DMA_CR0_PBLX8_RD(data) do {\
	DMA_CR0_RD(data);\
	data = ((data >> 16) & DMA_CR0_PBLX8_MASK);\
} while (0)


#define DMA_CR0_DPE_MASK (ULONG)(0x1)


#define DMA_CR0_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR0_DPE_WR(data) do {\
	ULONG v;\
	DMA_CR0_RD(v);\
	v = (v & (DMA_CR0_RES_WR_MASK_21))\
	|(((0) & (DMA_CR0_MASK_21))<<21);\
	v = (v & (DMA_CR0_RES_WR_MASK_25))\
	|(((0) & (DMA_CR0_MASK_25))<<25);\
	v = ((v & DMA_CR0_DPE_WR_MASK)\
	|((data & DMA_CR0_DPE_MASK)<<17));\
	DMA_CR0_WR(v);\
} while (0)

#define DMA_CR0_DPE_RD(data) do {\
	DMA_CR0_RD(data);\
	data = ((data >> 17) & DMA_CR0_DPE_MASK);\
} while (0)


#define DMA_CR0_DSL_MASK (ULONG)(0x7)


#define DMA_CR0_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR0_DSL_WR(data) do {\
	ULONG v;\
	DMA_CR0_RD(v);\
	v = (v & (DMA_CR0_RES_WR_MASK_21))\
	|(((0) & (DMA_CR0_MASK_21))<<21);\
	v = (v & (DMA_CR0_RES_WR_MASK_25))\
	|(((0) & (DMA_CR0_MASK_25))<<25);\
	v = ((v & DMA_CR0_DSL_WR_MASK)\
	|((data & DMA_CR0_DSL_MASK)<<18));\
	DMA_CR0_WR(v);\
} while (0)

#define DMA_CR0_DSL_RD(data) do {\
	DMA_CR0_RD(data);\
	data = ((data >> 18) & DMA_CR0_DSL_MASK);\
} while (0)


#define DMA_CR0_CH_MASK (ULONG)(0x1)


#define DMA_CR0_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR0_CH_WR(data) do {\
	ULONG v;\
	DMA_CR0_RD(v);\
	v = (v & (DMA_CR0_RES_WR_MASK_21))\
	|(((0) & (DMA_CR0_MASK_21))<<21);\
	v = (v & (DMA_CR0_RES_WR_MASK_25))\
	|(((0) & (DMA_CR0_MASK_25))<<25);\
	v = ((v & DMA_CR0_CH_WR_MASK)\
	|((data & DMA_CR0_CH_MASK)<<23));\
	DMA_CR0_WR(v);\
} while (0)

#define DMA_CR0_CH_RD(data) do {\
	DMA_CR0_RD(data);\
	data = ((data >> 23) & DMA_CR0_CH_MASK);\
} while (0)


#define DMA_CR0_SPH_MASK (ULONG)(0x1)


#define DMA_CR0_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR0_SPH_WR(data) do {\
	ULONG v;\
	DMA_CR0_RD(v);\
	v = (v & (DMA_CR0_RES_WR_MASK_21))\
	|(((0) & (DMA_CR0_MASK_21))<<21);\
	v = (v & (DMA_CR0_RES_WR_MASK_25))\
	|(((0) & (DMA_CR0_MASK_25))<<25);\
	v = ((v & DMA_CR0_SPH_WR_MASK)\
	|((data & DMA_CR0_SPH_MASK)<<24));\
	DMA_CR0_WR(v);\
} while (0)

#define DMA_CR0_SPH_RD(data) do {\
	DMA_CR0_RD(data);\
	data = ((data >> 24) & DMA_CR0_SPH_MASK);\
} while (0)

#define MAC_WTR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0xc))

#define MAC_WTR_WR(data) do {\
	iowrite32(data, (void *)MAC_WTR_OFFSET);\
} while (0)

#define MAC_WTR_RD(data) do {\
	(data) = ioread32((void *)MAC_WTR_OFFSET);\
} while (0)


#define  MAC_WTR_MASK_17 (ULONG)(0x7fff)


#define MAC_WTR_RES_WR_MASK_17 (ULONG)(0x1ffff)


#define  MAC_WTR_MASK_14 (ULONG)(0x3)


#define MAC_WTR_RES_WR_MASK_14 (ULONG)(0xffff3fff)


#define MAC_WTR_PWE_MASK (ULONG)(0x1)


#define MAC_WTR_PWE_WR_MASK (ULONG)(0xfffeffff)

#define MAC_WTR_PWE_WR(data) do {\
	ULONG v;\
	MAC_WTR_RD(v);\
	v = (v & (MAC_WTR_RES_WR_MASK_17))\
	|(((0) & (MAC_WTR_MASK_17))<<17);\
	v = (v & (MAC_WTR_RES_WR_MASK_14))\
	|(((0) & (MAC_WTR_MASK_14))<<14);\
	v = ((v & MAC_WTR_PWE_WR_MASK)\
	|((data & MAC_WTR_PWE_MASK)<<16));\
	MAC_WTR_WR(v);\
} while (0)

#define MAC_WTR_PWE_RD(data) do {\
	MAC_WTR_RD(data);\
	data = ((data >> 16) & MAC_WTR_PWE_MASK);\
} while (0)


#define MAC_WTR_WTO_MASK (ULONG)(0x3fff)


#define MAC_WTR_WTO_WR_MASK (ULONG)(0xffffc000)

#define MAC_WTR_WTO_WR(data) do {\
	ULONG v;\
	MAC_WTR_RD(v);\
	v = (v & (MAC_WTR_RES_WR_MASK_17))\
	|(((0) & (MAC_WTR_MASK_17))<<17);\
	v = (v & (MAC_WTR_RES_WR_MASK_14))\
	|(((0) & (MAC_WTR_MASK_14))<<14);\
	v = ((v & MAC_WTR_WTO_WR_MASK)\
	|((data & MAC_WTR_WTO_MASK)<<0));\
	MAC_WTR_WR(v);\
} while (0)

#define MAC_WTR_WTO_RD(data) do {\
	MAC_WTR_RD(data);\
	data = ((data >> 0) & MAC_WTR_WTO_MASK);\
} while (0)

#define MAC_MPFR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x8))

#define MAC_MPFR_WR(data) do {\
	iowrite32(data, (void *)MAC_MPFR_OFFSET);\
} while (0)

#define MAC_MPFR_RD(data) do {\
	(data) = ioread32((void *)MAC_MPFR_OFFSET);\
} while (0)


#define  MAC_MPFR_MASK_22 (ULONG)(0x1ff)


#define MAC_MPFR_RES_WR_MASK_22 (ULONG)(0x803fffff)


#define  MAC_MPFR_MASK_17 (ULONG)(0x7)


#define MAC_MPFR_RES_WR_MASK_17 (ULONG)(0xfff1ffff)


#define  MAC_MPFR_MASK_11 (ULONG)(0x1f)


#define MAC_MPFR_RES_WR_MASK_11 (ULONG)(0xffff07ff)


#define MAC_MPFR_RA_MASK (ULONG)(0x1)


#define MAC_MPFR_RA_WR_MASK (ULONG)(0x7fffffff)

#define MAC_MPFR_RA_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_RA_WR_MASK)\
	|((data & MAC_MPFR_RA_MASK)<<31));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_RA_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 31) & MAC_MPFR_RA_MASK);\
} while (0)


#define MAC_MPFR_DNTU_MASK (ULONG)(0x1)


#define MAC_MPFR_DNTU_WR_MASK (ULONG)(0xffdfffff)

#define MAC_MPFR_DNTU_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_DNTU_WR_MASK)\
	|((data & MAC_MPFR_DNTU_MASK)<<21));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_DNTU_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 21) & MAC_MPFR_DNTU_MASK);\
} while (0)


#define MAC_MPFR_IPFE_MASK (ULONG)(0x1)


#define MAC_MPFR_IPFE_WR_MASK (ULONG)(0xffefffff)

#define MAC_MPFR_IPFE_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_IPFE_WR_MASK)\
	|((data & MAC_MPFR_IPFE_MASK)<<20));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_IPFE_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 20) & MAC_MPFR_IPFE_MASK);\
} while (0)


#define MAC_MPFR_VTFE_MASK (ULONG)(0x1)


#define MAC_MPFR_VTFE_WR_MASK (ULONG)(0xfffeffff)

#define MAC_MPFR_VTFE_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_VTFE_WR_MASK)\
	|((data & MAC_MPFR_VTFE_MASK)<<16));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_VTFE_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 16) & MAC_MPFR_VTFE_MASK);\
} while (0)


#define MAC_MPFR_HPF_MASK (ULONG)(0x1)


#define MAC_MPFR_HPF_WR_MASK (ULONG)(0xfffffbff)

#define MAC_MPFR_HPF_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_HPF_WR_MASK)\
	|((data & MAC_MPFR_HPF_MASK)<<10));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_HPF_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 10) & MAC_MPFR_HPF_MASK);\
} while (0)


#define MAC_MPFR_SAF_MASK (ULONG)(0x1)


#define MAC_MPFR_SAF_WR_MASK (ULONG)(0xfffffdff)

#define MAC_MPFR_SAF_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_SAF_WR_MASK)\
	|((data & MAC_MPFR_SAF_MASK)<<9));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_SAF_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 9) & MAC_MPFR_SAF_MASK);\
} while (0)


#define MAC_MPFR_SAIF_MASK (ULONG)(0x1)


#define MAC_MPFR_SAIF_WR_MASK (ULONG)(0xfffffeff)

#define MAC_MPFR_SAIF_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_SAIF_WR_MASK)\
	|((data & MAC_MPFR_SAIF_MASK)<<8));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_SAIF_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 8) & MAC_MPFR_SAIF_MASK);\
} while (0)


#define MAC_MPFR_PCF_MASK (ULONG)(0x3)


#define MAC_MPFR_PCF_WR_MASK (ULONG)(0xffffff3f)

#define MAC_MPFR_PCF_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_PCF_WR_MASK)\
	|((data & MAC_MPFR_PCF_MASK)<<6));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_PCF_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 6) & MAC_MPFR_PCF_MASK);\
} while (0)


#define MAC_MPFR_DBF_MASK (ULONG)(0x1)


#define MAC_MPFR_DBF_WR_MASK (ULONG)(0xffffffdf)

#define MAC_MPFR_DBF_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_DBF_WR_MASK)\
	|((data & MAC_MPFR_DBF_MASK)<<5));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_DBF_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 5) & MAC_MPFR_DBF_MASK);\
} while (0)


#define MAC_MPFR_PM_MASK (ULONG)(0x1)


#define MAC_MPFR_PM_WR_MASK (ULONG)(0xffffffef)

#define MAC_MPFR_PM_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_PM_WR_MASK)\
	|((data & MAC_MPFR_PM_MASK)<<4));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_PM_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 4) & MAC_MPFR_PM_MASK);\
} while (0)


#define MAC_MPFR_DAIF_MASK (ULONG)(0x1)


#define MAC_MPFR_DAIF_WR_MASK (ULONG)(0xfffffff7)

#define MAC_MPFR_DAIF_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_DAIF_WR_MASK)\
	|((data & MAC_MPFR_DAIF_MASK)<<3));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_DAIF_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 3) & MAC_MPFR_DAIF_MASK);\
} while (0)


#define MAC_MPFR_HMC_MASK (ULONG)(0x1)


#define MAC_MPFR_HMC_WR_MASK (ULONG)(0xfffffffb)

#define MAC_MPFR_HMC_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_HMC_WR_MASK)\
	|((data & MAC_MPFR_HMC_MASK)<<2));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_HMC_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 2) & MAC_MPFR_HMC_MASK);\
} while (0)


#define MAC_MPFR_HUC_MASK (ULONG)(0x1)


#define MAC_MPFR_HUC_WR_MASK (ULONG)(0xfffffffd)

#define MAC_MPFR_HUC_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_HUC_WR_MASK)\
	|((data & MAC_MPFR_HUC_MASK)<<1));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_HUC_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 1) & MAC_MPFR_HUC_MASK);\
} while (0)


#define MAC_MPFR_PR_MASK (ULONG)(0x1)


#define MAC_MPFR_PR_WR_MASK (ULONG)(0xfffffffe)

#define MAC_MPFR_PR_WR(data) do {\
	ULONG v;\
	MAC_MPFR_RD(v);\
	v = (v & (MAC_MPFR_RES_WR_MASK_22))\
	|(((0) & (MAC_MPFR_MASK_22))<<22);\
	v = (v & (MAC_MPFR_RES_WR_MASK_17))\
	|(((0) & (MAC_MPFR_MASK_17))<<17);\
	v = (v & (MAC_MPFR_RES_WR_MASK_11))\
	|(((0) & (MAC_MPFR_MASK_11))<<11);\
	v = ((v & MAC_MPFR_PR_WR_MASK)\
	|((data & MAC_MPFR_PR_MASK)<<0));\
	MAC_MPFR_WR(v);\
} while (0)

#define MAC_MPFR_PR_RD(data) do {\
	MAC_MPFR_RD(data);\
	data = ((data >> 0) & MAC_MPFR_PR_MASK);\
} while (0)

#define MAC_MECR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0x4))

#define MAC_MECR_WR(data) do {\
	iowrite32(data, (void *)MAC_MECR_OFFSET);\
} while (0)

#define MAC_MECR_RD(data) do {\
	(data) = ioread32((void *)MAC_MECR_OFFSET);\
} while (0)


#define  MAC_MECR_MASK_23 (ULONG)(0x1ff)


#define MAC_MECR_RES_WR_MASK_23 (ULONG)(0x7fffff)


#define  MAC_MECR_MASK_19 (ULONG)(0x1)


#define MAC_MECR_RES_WR_MASK_19 (ULONG)(0xfff7ffff)


#define  MAC_MECR_MASK_15 (ULONG)(0x1)


#define MAC_MECR_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define MAC_MECR_HDSMS_MASK (ULONG)(0x7)


#define MAC_MECR_HDSMS_WR_MASK (ULONG)(0xff8fffff)

#define MAC_MECR_HDSMS_WR(data) do {\
	ULONG v;\
	MAC_MECR_RD(v);\
	v = (v & (MAC_MECR_RES_WR_MASK_23))\
	|(((0) & (MAC_MECR_MASK_23))<<23);\
	v = (v & (MAC_MECR_RES_WR_MASK_19))\
	|(((0) & (MAC_MECR_MASK_19))<<19);\
	v = (v & (MAC_MECR_RES_WR_MASK_15))\
	|(((0) & (MAC_MECR_MASK_15))<<15);\
	v = ((v & MAC_MECR_HDSMS_WR_MASK)\
	|((data & MAC_MECR_HDSMS_MASK)<<20));\
	MAC_MECR_WR(v);\
} while (0)

#define MAC_MECR_HDSMS_RD(data) do {\
	MAC_MECR_RD(data);\
	data = ((data >> 20) & MAC_MECR_HDSMS_MASK);\
} while (0)


#define MAC_MECR_USP_MASK (ULONG)(0x1)


#define MAC_MECR_USP_WR_MASK (ULONG)(0xfffbffff)

#define MAC_MECR_USP_WR(data) do {\
	ULONG v;\
	MAC_MECR_RD(v);\
	v = (v & (MAC_MECR_RES_WR_MASK_23))\
	|(((0) & (MAC_MECR_MASK_23))<<23);\
	v = (v & (MAC_MECR_RES_WR_MASK_19))\
	|(((0) & (MAC_MECR_MASK_19))<<19);\
	v = (v & (MAC_MECR_RES_WR_MASK_15))\
	|(((0) & (MAC_MECR_MASK_15))<<15);\
	v = ((v & MAC_MECR_USP_WR_MASK)\
	|((data & MAC_MECR_USP_MASK)<<18));\
	MAC_MECR_WR(v);\
} while (0)

#define MAC_MECR_USP_RD(data) do {\
	MAC_MECR_RD(data);\
	data = ((data >> 18) & MAC_MECR_USP_MASK);\
} while (0)


#define MAC_MECR_SPEN_MASK (ULONG)(0x1)


#define MAC_MECR_SPEN_WR_MASK (ULONG)(0xfffdffff)

#define MAC_MECR_SPEN_WR(data) do {\
	ULONG v;\
	MAC_MECR_RD(v);\
	v = (v & (MAC_MECR_RES_WR_MASK_23))\
	|(((0) & (MAC_MECR_MASK_23))<<23);\
	v = (v & (MAC_MECR_RES_WR_MASK_19))\
	|(((0) & (MAC_MECR_MASK_19))<<19);\
	v = (v & (MAC_MECR_RES_WR_MASK_15))\
	|(((0) & (MAC_MECR_MASK_15))<<15);\
	v = ((v & MAC_MECR_SPEN_WR_MASK)\
	|((data & MAC_MECR_SPEN_MASK)<<17));\
	MAC_MECR_WR(v);\
} while (0)

#define MAC_MECR_SPEN_RD(data) do {\
	MAC_MECR_RD(data);\
	data = ((data >> 17) & MAC_MECR_SPEN_MASK);\
} while (0)


#define MAC_MECR_DCRCC_MASK (ULONG)(0x1)


#define MAC_MECR_DCRCC_WR_MASK (ULONG)(0xfffeffff)

#define MAC_MECR_DCRCC_WR(data) do {\
	ULONG v;\
	MAC_MECR_RD(v);\
	v = (v & (MAC_MECR_RES_WR_MASK_23))\
	|(((0) & (MAC_MECR_MASK_23))<<23);\
	v = (v & (MAC_MECR_RES_WR_MASK_19))\
	|(((0) & (MAC_MECR_MASK_19))<<19);\
	v = (v & (MAC_MECR_RES_WR_MASK_15))\
	|(((0) & (MAC_MECR_MASK_15))<<15);\
	v = ((v & MAC_MECR_DCRCC_WR_MASK)\
	|((data & MAC_MECR_DCRCC_MASK)<<16));\
	MAC_MECR_WR(v);\
} while (0)

#define MAC_MECR_DCRCC_RD(data) do {\
	MAC_MECR_RD(data);\
	data = ((data >> 16) & MAC_MECR_DCRCC_MASK);\
} while (0)


#define MAC_MECR_GPSL_MASK (ULONG)(0x7fff)


#define MAC_MECR_GPSL_WR_MASK (ULONG)(0xffff8000)

#define MAC_MECR_GPSL_WR(data) do {\
	ULONG v;\
	MAC_MECR_RD(v);\
	v = (v & (MAC_MECR_RES_WR_MASK_23))\
	|(((0) & (MAC_MECR_MASK_23))<<23);\
	v = (v & (MAC_MECR_RES_WR_MASK_19))\
	|(((0) & (MAC_MECR_MASK_19))<<19);\
	v = (v & (MAC_MECR_RES_WR_MASK_15))\
	|(((0) & (MAC_MECR_MASK_15))<<15);\
	v = ((v & MAC_MECR_GPSL_WR_MASK)\
	|((data & MAC_MECR_GPSL_MASK)<<0));\
	MAC_MECR_WR(v);\
} while (0)

#define MAC_MECR_GPSL_RD(data) do {\
	MAC_MECR_RD(data);\
	data = ((data >> 0) & MAC_MECR_GPSL_MASK);\
} while (0)

#define MAC_MCR_OFFSET ((volatile ULONG *)(BASE_ADDRESS + 0))

#define MAC_MCR_WR(data) do {\
	iowrite32(data, (void *)MAC_MCR_OFFSET);\
} while (0)

#define MAC_MCR_RD(data) do {\
	(data) = ioread32((void *)MAC_MCR_OFFSET);\
} while (0)


#define  MAC_MCR_MASK_7 (ULONG)(0x1)


#define MAC_MCR_RES_WR_MASK_7 (ULONG)(0xffffff7f)


#define MAC_MCR_ARPEN_MASK (ULONG)(0x1)


#define MAC_MCR_ARPEN_WR_MASK (ULONG)(0x7fffffff)

#define MAC_MCR_ARPEN_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_ARPEN_WR_MASK)\
	|((data & MAC_MCR_ARPEN_MASK)<<31));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_ARPEN_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 31) & MAC_MCR_ARPEN_MASK);\
} while (0)


#define MAC_MCR_SARC_MASK (ULONG)(0x7)


#define MAC_MCR_SARC_WR_MASK (ULONG)(0x8fffffff)

#define MAC_MCR_SARC_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_SARC_WR_MASK)\
	|((data & MAC_MCR_SARC_MASK)<<28));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_SARC_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 28) & MAC_MCR_SARC_MASK);\
} while (0)


#define MAC_MCR_IPC_MASK (ULONG)(0x1)


#define MAC_MCR_IPC_WR_MASK (ULONG)(0xf7ffffff)

#define MAC_MCR_IPC_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_IPC_WR_MASK)\
	|((data & MAC_MCR_IPC_MASK)<<27));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_IPC_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 27) & MAC_MCR_IPC_MASK);\
} while (0)


#define MAC_MCR_IFG_MASK (ULONG)(0x7)


#define MAC_MCR_IFG_WR_MASK (ULONG)(0xf8ffffff)

#define MAC_MCR_IFG_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_IFG_WR_MASK)\
	|((data & MAC_MCR_IFG_MASK)<<24));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_IFG_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 24) & MAC_MCR_IFG_MASK);\
} while (0)


#define MAC_MCR_GPSLCE_MASK (ULONG)(0x1)


#define MAC_MCR_GPSLCE_WR_MASK (ULONG)(0xff7fffff)

#define MAC_MCR_GPSLCE_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_GPSLCE_WR_MASK)\
	|((data & MAC_MCR_GPSLCE_MASK)<<23));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_GPSLCE_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 23) & MAC_MCR_GPSLCE_MASK);\
} while (0)


#define MAC_MCR_S2KP_MASK (ULONG)(0x1)


#define MAC_MCR_S2KP_WR_MASK (ULONG)(0xffbfffff)

#define MAC_MCR_S2KP_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_S2KP_WR_MASK)\
	|((data & MAC_MCR_S2KP_MASK)<<22));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_S2KP_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 22) & MAC_MCR_S2KP_MASK);\
} while (0)


#define MAC_MCR_CST_MASK (ULONG)(0x1)


#define MAC_MCR_CST_WR_MASK (ULONG)(0xffdfffff)

#define MAC_MCR_CST_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_CST_WR_MASK)\
	|((data & MAC_MCR_CST_MASK)<<21));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_CST_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 21) & MAC_MCR_CST_MASK);\
} while (0)


#define MAC_MCR_ACS_MASK (ULONG)(0x1)


#define MAC_MCR_ACS_WR_MASK (ULONG)(0xffefffff)

#define MAC_MCR_ACS_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_ACS_WR_MASK)\
	|((data & MAC_MCR_ACS_MASK)<<20));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_ACS_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 20) & MAC_MCR_ACS_MASK);\
} while (0)


#define MAC_MCR_WD_MASK (ULONG)(0x1)


#define MAC_MCR_WD_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_MCR_WD_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_WD_WR_MASK)\
	|((data & MAC_MCR_WD_MASK)<<19));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_WD_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 19) & MAC_MCR_WD_MASK);\
} while (0)


#define MAC_MCR_BE_MASK (ULONG)(0x1)


#define MAC_MCR_BE_WR_MASK (ULONG)(0xfffbffff)

#define MAC_MCR_BE_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_BE_WR_MASK)\
	|((data & MAC_MCR_BE_MASK)<<18));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_BE_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 18) & MAC_MCR_BE_MASK);\
} while (0)


#define MAC_MCR_JD_MASK (ULONG)(0x1)


#define MAC_MCR_JD_WR_MASK (ULONG)(0xfffdffff)

#define MAC_MCR_JD_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_JD_WR_MASK)\
	|((data & MAC_MCR_JD_MASK)<<17));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_JD_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 17) & MAC_MCR_JD_MASK);\
} while (0)


#define MAC_MCR_JE_MASK (ULONG)(0x1)


#define MAC_MCR_JE_WR_MASK (ULONG)(0xfffeffff)

#define MAC_MCR_JE_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_JE_WR_MASK)\
	|((data & MAC_MCR_JE_MASK)<<16));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_JE_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 16) & MAC_MCR_JE_MASK);\
} while (0)


#define MAC_MCR_PS_MASK (ULONG)(0x1)


#define MAC_MCR_PS_WR_MASK (ULONG)(0xffff7fff)

#define MAC_MCR_PS_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_PS_WR_MASK)\
	|((data & MAC_MCR_PS_MASK)<<15));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_PS_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 15) & MAC_MCR_PS_MASK);\
} while (0)


#define MAC_MCR_FES_MASK (ULONG)(0x1)


#define MAC_MCR_FES_WR_MASK (ULONG)(0xffffbfff)

#define MAC_MCR_FES_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_FES_WR_MASK)\
	|((data & MAC_MCR_FES_MASK)<<14));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_FES_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 14) & MAC_MCR_FES_MASK);\
} while (0)


#define MAC_MCR_DM_MASK (ULONG)(0x1)


#define MAC_MCR_DM_WR_MASK (ULONG)(0xffffdfff)

#define MAC_MCR_DM_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_DM_WR_MASK)\
	|((data & MAC_MCR_DM_MASK)<<13));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_DM_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 13) & MAC_MCR_DM_MASK);\
} while (0)


#define MAC_MCR_LM_MASK (ULONG)(0x1)


#define MAC_MCR_LM_WR_MASK (ULONG)(0xffffefff)

#define MAC_MCR_LM_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_LM_WR_MASK)\
	|((data & MAC_MCR_LM_MASK)<<12));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_LM_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 12) & MAC_MCR_LM_MASK);\
} while (0)


#define MAC_MCR_ECRSFD_MASK (ULONG)(0x1)


#define MAC_MCR_ECRSFD_WR_MASK (ULONG)(0xfffff7ff)

#define MAC_MCR_ECRSFD_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_ECRSFD_WR_MASK)\
	|((data & MAC_MCR_ECRSFD_MASK)<<11));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_ECRSFD_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 11) & MAC_MCR_ECRSFD_MASK);\
} while (0)


#define MAC_MCR_DRO_MASK (ULONG)(0x1)


#define MAC_MCR_DRO_WR_MASK (ULONG)(0xfffffbff)

#define MAC_MCR_DRO_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_DRO_WR_MASK)\
	|((data & MAC_MCR_DRO_MASK)<<10));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_DRO_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 10) & MAC_MCR_DRO_MASK);\
} while (0)


#define MAC_MCR_DCRS_MASK (ULONG)(0x1)


#define MAC_MCR_DCRS_WR_MASK (ULONG)(0xfffffdff)

#define MAC_MCR_DCRS_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_DCRS_WR_MASK)\
	|((data & MAC_MCR_DCRS_MASK)<<9));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_DCRS_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 9) & MAC_MCR_DCRS_MASK);\
} while (0)


#define MAC_MCR_DR_MASK (ULONG)(0x1)


#define MAC_MCR_DR_WR_MASK (ULONG)(0xfffffeff)

#define MAC_MCR_DR_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_DR_WR_MASK)\
	|((data & MAC_MCR_DR_MASK)<<8));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_DR_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 8) & MAC_MCR_DR_MASK);\
} while (0)


#define MAC_MCR_BL_MASK (ULONG)(0x3)


#define MAC_MCR_BL_WR_MASK (ULONG)(0xffffff9f)

#define MAC_MCR_BL_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_BL_WR_MASK)\
	|((data & MAC_MCR_BL_MASK)<<5));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_BL_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 5) & MAC_MCR_BL_MASK);\
} while (0)


#define MAC_MCR_DEFC_MASK (ULONG)(0x1)


#define MAC_MCR_DEFC_WR_MASK (ULONG)(0xffffffef)

#define MAC_MCR_DEFC_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_DEFC_WR_MASK)\
	|((data & MAC_MCR_DEFC_MASK)<<4));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_DEFC_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 4) & MAC_MCR_DEFC_MASK);\
} while (0)


#define MAC_MCR_PRELEN_MASK (ULONG)(0x3)


#define MAC_MCR_PRELEN_WR_MASK (ULONG)(0xfffffff3)

#define MAC_MCR_PRELEN_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_PRELEN_WR_MASK)\
	|((data & MAC_MCR_PRELEN_MASK)<<2));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_PRELEN_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 2) & MAC_MCR_PRELEN_MASK);\
} while (0)


#define MAC_MCR_TE_MASK (ULONG)(0x1)


#define MAC_MCR_TE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_MCR_TE_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_TE_WR_MASK)\
	|((data & MAC_MCR_TE_MASK)<<1));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_TE_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 1) & MAC_MCR_TE_MASK);\
} while (0)


#define MAC_MCR_RE_MASK (ULONG)(0x1)


#define MAC_MCR_RE_WR_MASK (ULONG)(0xfffffffe)

#define MAC_MCR_RE_WR(data) do {\
	ULONG v;\
	MAC_MCR_RD(v);\
	v = (v & (MAC_MCR_RES_WR_MASK_7))\
	|(((0) & (MAC_MCR_MASK_7))<<7);\
	v = ((v & MAC_MCR_RE_WR_MASK)\
	|((data & MAC_MCR_RE_MASK)<<0));\
	MAC_MCR_WR(v);\
} while (0)

#define MAC_MCR_RE_RD(data) do {\
	MAC_MCR_RD(data);\
	data = ((data >> 0) & MAC_MCR_RE_MASK);\
} while (0)

#define MAC_MA32_127LR_OFFSET (BASE_ADDRESS + 0x404)

#define MAC_MA32_127LR_OFFSET_Q(i) ((volatile ULONG *)(MAC_MA32_127LR_OFFSET + ((i-32)*8)))

#define MAC_MA32_127LR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_MA32_127LR_OFFSET_Q(i));\
} while (0)

#define MAC_MA32_127LR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_MA32_127LR_OFFSET_Q(i));\
} while (0)

#define MAC_MA32_127LR_ADDRLO_WR(i, data) do {\
	MAC_MA32_127LR_WR(i, data);\
} while (0)

#define MAC_MA32_127LR_ADDRLO_RD(i, data) do {\
	MAC_MA32_127LR_RD(i, data);\
} while (0)

#define MAC_MA32_127HR_OFFSET (BASE_ADDRESS + 0x400)

#define MAC_MA32_127HR_OFFSET_Q(i) ((volatile ULONG *)(MAC_MA32_127HR_OFFSET + ((i-32)*8)))

#define MAC_MA32_127HR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_MA32_127HR_OFFSET_Q(i));\
} while (0)

#define MAC_MA32_127HR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_MA32_127HR_OFFSET_Q(i));\
} while (0)


#define  MAC_MA32_127HR_MASK_19 (ULONG)(0xfff)


#define MAC_MA32_127HR_RES_WR_MASK_19 (ULONG)(0x8007ffff)


#define MAC_MA32_127HR_AE_MASK (ULONG)(0x1)


#define MAC_MA32_127HR_AE_WR_MASK (ULONG)(0x7fffffff)

#define MAC_MA32_127HR_AE_RD(i, data) do {\
	MAC_MA32_127HR_RD(i, data);\
	data = ((data >> 31) & MAC_MA32_127HR_AE_MASK);\
} while (0)


#define MAC_MA32_127HR_DCS_MASK (ULONG)(0x7)


#define MAC_MA32_127HR_DCS_WR_MASK (ULONG)(0xfff8ffff)

#define MAC_MA32_127HR_DCS_WR(i, data) do {\
	ULONG v;\
	MAC_MA32_127HR_RD(i, v);\
	v = (v & (MAC_MA32_127HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA32_127HR_MASK_19))<<19);\
	v = ((v & MAC_MA32_127HR_DCS_WR_MASK)\
	|((data & MAC_MA32_127HR_DCS_MASK)<<16));\
	MAC_MA32_127HR_WR(i, v);\
} while (0)

#define MAC_MA32_127HR_DCS_RD(i, data) do {\
	MAC_MA32_127HR_RD(i, data);\
	data = ((data >> 16) & MAC_MA32_127HR_DCS_MASK);\
} while (0)


#define MAC_MA32_127HR_ADDRHI_MASK (ULONG)(0xffff)


#define MAC_MA32_127HR_ADDRHI_WR_MASK (ULONG)(0xffff0000)

#define MAC_MA32_127HR_ADDRHI_AE_WR(i, data, ae) do {\
	ULONG v;\
	MAC_MA32_127HR_RD(i, v);\
	v = (v & (MAC_MA32_127HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA32_127HR_MASK_19))<<19);\
	v = ((v & MAC_MA32_127HR_ADDRHI_WR_MASK)\
	|((data & MAC_MA32_127HR_ADDRHI_MASK)<<0));\
	v = ((v & MAC_MA32_127HR_AE_WR_MASK)\
	|((ae & MAC_MA32_127HR_AE_MASK)<<31));\
	MAC_MA32_127HR_WR(i, v);\
} while (0)

#define MAC_MA32_127HR_ADDRHI_RD(i, data) do {\
	MAC_MA32_127HR_RD(i, data);\
	data = ((data >> 0) & MAC_MA32_127HR_ADDRHI_MASK);\
} while (0)

#define MAC_MA1_31LR_OFFSET (BASE_ADDRESS + 0x30c)

#define MAC_MA1_31LR_OFFSET_Q(i) ((volatile ULONG *)(MAC_MA1_31LR_OFFSET + ((i-1)*8)))

#define MAC_MA1_31LR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_MA1_31LR_OFFSET_Q(i));\
} while (0)

#define MAC_MA1_31LR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_MA1_31LR_OFFSET_Q(i));\
} while (0)

#define MAC_MA1_31LR_ADDRLO_WR(i, data) do {\
	MAC_MA1_31LR_WR(i, data);\
} while (0)

#define MAC_MA1_31LR_ADDRLO_RD(i, data) do {\
	MAC_MA1_31LR_RD(i, data);\
} while (0)

#define MAC_MA1_31HR_OFFSET (BASE_ADDRESS + 0x308)

#define MAC_MA1_31HR_OFFSET_Q(i) ((volatile ULONG *)(MAC_MA1_31HR_OFFSET + ((i-1)*8)))

#define MAC_MA1_31HR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_MA1_31HR_OFFSET_Q(i));\
} while (0)

#define MAC_MA1_31HR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_MA1_31HR_OFFSET_Q(i));\
} while (0)


#define  MAC_MA1_31HR_MASK_19 (ULONG)(0x1f)


#define MAC_MA1_31HR_RES_WR_MASK_19 (ULONG)(0xff07ffff)


#define MAC_MA1_31HR_AE_MASK (ULONG)(0x1)


#define MAC_MA1_31HR_AE_WR_MASK (ULONG)(0x7fffffff)

#define MAC_MA1_31HR_AE_RD(i, data) do {\
	MAC_MA1_31HR_RD(i, data);\
	data = ((data >> 31) & MAC_MA1_31HR_AE_MASK);\
} while (0)


#define MAC_MA1_31HR_SA_MASK (ULONG)(0x1)


#define MAC_MA1_31HR_SA_WR_MASK (ULONG)(0xbfffffff)

#define MAC_MA1_31HR_SA_WR(i, data) do {\
	ULONG v;\
	MAC_MA1_31HR_RD(i, v);\
	v = (v & (MAC_MA1_31HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1_31HR_MASK_19))<<19);\
	v = ((v & MAC_MA1_31HR_SA_WR_MASK)\
	|((data & MAC_MA1_31HR_SA_MASK)<<30));\
	MAC_MA1_31HR_WR(i, v);\
} while (0)

#define MAC_MA1_31HR_SA_RD(i, data) do {\
	MAC_MA1_31HR_RD(i, data);\
	data = ((data >> 30) & MAC_MA1_31HR_SA_MASK);\
} while (0)


#define MAC_MA1_31HR_MBC_MASK (ULONG)(0x3f)


#define MAC_MA1_31HR_MBC_WR_MASK (ULONG)(0xc0ffffff)

#define MAC_MA1_31HR_MBC_WR(i, data) do {\
	ULONG v;\
	MAC_MA1_31HR_RD(i, v);\
	v = (v & (MAC_MA1_31HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1_31HR_MASK_19))<<19);\
	v = ((v & MAC_MA1_31HR_MBC_WR_MASK)\
	|((data & MAC_MA1_31HR_MBC_MASK)<<24));\
	MAC_MA1_31HR_WR(i, v);\
} while (0)

#define MAC_MA1_31HR_MBC_RD(i, data) do {\
	MAC_MA1_31HR_RD(i, data);\
	data = ((data >> 24) & MAC_MA1_31HR_MBC_MASK);\
} while (0)


#define MAC_MA1_31HR_DCS_MASK (ULONG)(0x7)


#define MAC_MA1_31HR_DCS_WR_MASK (ULONG)(0xfff8ffff)

#define MAC_MA1_31HR_DCS_WR(i, data) do {\
	ULONG v;\
	MAC_MA1_31HR_RD(i, v);\
	v = (v & (MAC_MA1_31HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1_31HR_MASK_19))<<19);\
	v = ((v & MAC_MA1_31HR_DCS_WR_MASK)\
	|((data & MAC_MA1_31HR_DCS_MASK)<<16));\
	MAC_MA1_31HR_WR(i, v);\
} while (0)

#define MAC_MA1_31HR_DCS_RD(i, data) do {\
	MAC_MA1_31HR_RD(i, data);\
	data = ((data >> 16) & MAC_MA1_31HR_DCS_MASK);\
} while (0)


#define MAC_MA1_31HR_ADDRHI_MASK (ULONG)(0xffff)


#define MAC_MA1_31HR_ADDRHI_WR_MASK (ULONG)(0xffff0000)

#define MAC_MA1_31HR_ADDRHI_AE_WR(i, data, ae) do {\
	ULONG v;\
	MAC_MA1_31HR_RD(i, v);\
	v = (v & (MAC_MA1_31HR_RES_WR_MASK_19))\
	|(((0) & (MAC_MA1_31HR_MASK_19))<<19);\
	v = ((v & MAC_MA1_31HR_ADDRHI_WR_MASK)\
	|((data & MAC_MA1_31HR_ADDRHI_MASK)<<0));\
	v = ((v & MAC_MA1_31HR_AE_WR_MASK)\
	|((ae & MAC_MA1_31HR_AE_MASK)<<31));\
	MAC_MA1_31HR_WR(i, v);\
} while (0)

#define MAC_MA1_31HR_ADDRHI_RD(i, data) do {\
	MAC_MA1_31HR_RD(i, data);\
	data = ((data >> 0) & MAC_MA1_31HR_ADDRHI_MASK);\
} while (0)

#define MAC_L3A3R_OFFSET (BASE_ADDRESS + 0x91c)

#define MAC_L3A3R_OFFSET_Q(i) ((volatile ULONG *)(MAC_L3A3R_OFFSET + ((i-0)*48)))

#define MAC_L3A3R_WR(i, data) do {\
	iowrite32(data, (void *)MAC_L3A3R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A3R_RD(i, data) do {\
	(data) = ioread32((void *)MAC_L3A3R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A3R_L3A30_WR(i, data) do {\
	MAC_L3A3R_WR(i, data);\
} while (0)

#define MAC_L3A3R_L3A30_RD(i, data) do {\
	MAC_L3A3R_RD(i, data);\
} while (0)

#define MAC_L3A2R_OFFSET (BASE_ADDRESS + 0x918)

#define MAC_L3A2R_OFFSET_Q(i) ((volatile ULONG *)(MAC_L3A2R_OFFSET + ((i-0)*48)))

#define MAC_L3A2R_WR(i, data) do {\
	iowrite32(data, (void *)MAC_L3A2R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A2R_RD(i, data) do {\
	(data) = ioread32((void *)MAC_L3A2R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A2R_L3A20_WR(i, data) do {\
	MAC_L3A2R_WR(i, data);\
} while (0)

#define MAC_L3A2R_L3A20_RD(i, data) do {\
	MAC_L3A2R_RD(i, data);\
} while (0)

#define MAC_L3A1R_OFFSET (BASE_ADDRESS + 0x914)

#define MAC_L3A1R_OFFSET_Q(i) ((volatile ULONG *)(MAC_L3A1R_OFFSET + ((i-0)*48)))

#define MAC_L3A1R_WR(i, data) do {\
	iowrite32(data, (void *)MAC_L3A1R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A1R_RD(i, data) do {\
	(data) = ioread32((void *)MAC_L3A1R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A1R_L3A10_WR(i, data) do {\
	MAC_L3A1R_WR(i, data);\
} while (0)

#define MAC_L3A1R_L3A10_RD(i, data) do {\
	MAC_L3A1R_RD(i, data);\
} while (0)

#define MAC_L3A0R_OFFSET (BASE_ADDRESS + 0x910)

#define MAC_L3A0R_OFFSET_Q(i) ((volatile ULONG *)(MAC_L3A0R_OFFSET + ((i-0)*48)))

#define MAC_L3A0R_WR(i, data) do {\
	iowrite32(data, (void *)MAC_L3A0R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A0R_RD(i, data) do {\
	(data) = ioread32((void *)MAC_L3A0R_OFFSET_Q(i));\
} while (0)

#define MAC_L3A0R_L3A00_WR(i, data) do {\
	MAC_L3A0R_WR(i, data);\
} while (0)

#define MAC_L3A0R_L3A00_RD(i, data) do {\
	MAC_L3A0R_RD(i, data);\
} while (0)

#define MAC_L4AR_OFFSET (BASE_ADDRESS + 0x904)

#define MAC_L4AR_OFFSET_Q(i) ((volatile ULONG *)(MAC_L4AR_OFFSET + ((i-0)*48)))

#define MAC_L4AR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_L4AR_OFFSET_Q(i));\
} while (0)

#define MAC_L4AR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_L4AR_OFFSET_Q(i));\
} while (0)


#define MAC_L4AR_L4DP0_MASK (ULONG)(0xffff)


#define MAC_L4AR_L4DP0_WR_MASK (ULONG)(0xffff)

#define MAC_L4AR_L4DP0_WR(i, data) do {\
	ULONG v;\
	MAC_L4AR_RD(i, v);\
	v = ((v & MAC_L4AR_L4DP0_WR_MASK)\
	|((data & MAC_L4AR_L4DP0_MASK)<<16));\
	MAC_L4AR_WR(i, v);\
} while (0)

#define MAC_L4AR_L4DP0_RD(i, data) do {\
	MAC_L4AR_RD(i, data);\
	data = ((data >> 16) & MAC_L4AR_L4DP0_MASK);\
} while (0)


#define MAC_L4AR_L4SP0_MASK (ULONG)(0xffff)


#define MAC_L4AR_L4SP0_WR_MASK (ULONG)(0xffff0000)

#define MAC_L4AR_L4SP0_WR(i, data) do {\
	ULONG v;\
	MAC_L4AR_RD(i, v);\
	v = ((v & MAC_L4AR_L4SP0_WR_MASK)\
	|((data & MAC_L4AR_L4SP0_MASK)<<0));\
	MAC_L4AR_WR(i, v);\
} while (0)

#define MAC_L4AR_L4SP0_RD(i, data) do {\
	MAC_L4AR_RD(i, data);\
	data = ((data >> 0) & MAC_L4AR_L4SP0_MASK);\
} while (0)

#define MAC_L3L4CR_OFFSET (BASE_ADDRESS + 0x900)

#define MAC_L3L4CR_OFFSET_Q(i) ((volatile ULONG *)(MAC_L3L4CR_OFFSET + ((i-0)*48)))

#define MAC_L3L4CR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_L3L4CR_OFFSET_Q(i));\
} while (0)

#define MAC_L3L4CR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_L3L4CR_OFFSET_Q(i));\
} while (0)


#define  MAC_L3L4CR_MASK_22 (ULONG)(0x3ff)


#define MAC_L3L4CR_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define  MAC_L3L4CR_MASK_17 (ULONG)(0x1)


#define MAC_L3L4CR_RES_WR_MASK_17 (ULONG)(0xfffdffff)


#define  MAC_L3L4CR_MASK_1 (ULONG)(0x1)


#define MAC_L3L4CR_RES_WR_MASK_1 (ULONG)(0xfffffffd)


#define MAC_L3L4CR_L4DPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L4DPIM0_WR_MASK (ULONG)(0xffdfffff)

#define MAC_L3L4CR_L4DPIM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L4DPIM0_WR_MASK)\
	|((data & MAC_L3L4CR_L4DPIM0_MASK)<<21));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L4DPIM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 21) & MAC_L3L4CR_L4DPIM0_MASK);\
} while (0)


#define MAC_L3L4CR_L4DPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L4DPM0_WR_MASK (ULONG)(0xffefffff)

#define MAC_L3L4CR_L4DPM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L4DPM0_WR_MASK)\
	|((data & MAC_L3L4CR_L4DPM0_MASK)<<20));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L4DPM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 20) & MAC_L3L4CR_L4DPM0_MASK);\
} while (0)


#define MAC_L3L4CR_L4SPIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L4SPIM0_WR_MASK (ULONG)(0xfff7ffff)

#define MAC_L3L4CR_L4SPIM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L4SPIM0_WR_MASK)\
	|((data & MAC_L3L4CR_L4SPIM0_MASK)<<19));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L4SPIM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 19) & MAC_L3L4CR_L4SPIM0_MASK);\
} while (0)


#define MAC_L3L4CR_L4SPM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L4SPM0_WR_MASK (ULONG)(0xfffbffff)

#define MAC_L3L4CR_L4SPM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L4SPM0_WR_MASK)\
	|((data & MAC_L3L4CR_L4SPM0_MASK)<<18));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L4SPM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 18) & MAC_L3L4CR_L4SPM0_MASK);\
} while (0)


#define MAC_L3L4CR_L4PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L4PEN0_WR_MASK (ULONG)(0xfffeffff)

#define MAC_L3L4CR_L4PEN0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L4PEN0_WR_MASK)\
	|((data & MAC_L3L4CR_L4PEN0_MASK)<<16));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L4PEN0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 16) & MAC_L3L4CR_L4PEN0_MASK);\
} while (0)


#define MAC_L3L4CR_L3HDBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR_L3HDBM0_WR_MASK (ULONG)(0xffff07ff)

#define MAC_L3L4CR_L3HDBM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3HDBM0_WR_MASK)\
	|((data & MAC_L3L4CR_L3HDBM0_MASK)<<11));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3HDBM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 11) & MAC_L3L4CR_L3HDBM0_MASK);\
} while (0)


#define MAC_L3L4CR_L3HSBM0_MASK (ULONG)(0x1f)


#define MAC_L3L4CR_L3HSBM0_WR_MASK (ULONG)(0xfffff83f)

#define MAC_L3L4CR_L3HSBM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3HSBM0_WR_MASK)\
	|((data & MAC_L3L4CR_L3HSBM0_MASK)<<6));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3HSBM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 6) & MAC_L3L4CR_L3HSBM0_MASK);\
} while (0)


#define MAC_L3L4CR_L3DAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L3DAIM0_WR_MASK (ULONG)(0xffffffdf)

#define MAC_L3L4CR_L3DAIM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3DAIM0_WR_MASK)\
	|((data & MAC_L3L4CR_L3DAIM0_MASK)<<5));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3DAIM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 5) & MAC_L3L4CR_L3DAIM0_MASK);\
} while (0)


#define MAC_L3L4CR_L3DAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L3DAM0_WR_MASK (ULONG)(0xffffffef)

#define MAC_L3L4CR_L3DAM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3DAM0_WR_MASK)\
	|((data & MAC_L3L4CR_L3DAM0_MASK)<<4));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3DAM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 4) & MAC_L3L4CR_L3DAM0_MASK);\
} while (0)


#define MAC_L3L4CR_L3SAIM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L3SAIM0_WR_MASK (ULONG)(0xfffffff7)

#define MAC_L3L4CR_L3SAIM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3SAIM0_WR_MASK)\
	|((data & MAC_L3L4CR_L3SAIM0_MASK)<<3));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3SAIM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 3) & MAC_L3L4CR_L3SAIM0_MASK);\
} while (0)


#define MAC_L3L4CR_L3SAM0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L3SAM0_WR_MASK (ULONG)(0xfffffffb)

#define MAC_L3L4CR_L3SAM0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3SAM0_WR_MASK)\
	|((data & MAC_L3L4CR_L3SAM0_MASK)<<2));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3SAM0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 2) & MAC_L3L4CR_L3SAM0_MASK);\
} while (0)


#define MAC_L3L4CR_L3PEN0_MASK (ULONG)(0x1)


#define MAC_L3L4CR_L3PEN0_WR_MASK (ULONG)(0xfffffffe)

#define MAC_L3L4CR_L3PEN0_WR(i, data) do {\
	ULONG v;\
	MAC_L3L4CR_RD(i, v);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_22))\
	|(((0) & (MAC_L3L4CR_MASK_22))<<22);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_17))\
	|(((0) & (MAC_L3L4CR_MASK_17))<<17);\
	v = (v & (MAC_L3L4CR_RES_WR_MASK_1))\
	|(((0) & (MAC_L3L4CR_MASK_1))<<1);\
	v = ((v & MAC_L3L4CR_L3PEN0_WR_MASK)\
	|((data & MAC_L3L4CR_L3PEN0_MASK)<<0));\
	MAC_L3L4CR_WR(i, v);\
} while (0)

#define MAC_L3L4CR_L3PEN0_RD(i, data) do {\
	MAC_L3L4CR_RD(i, data);\
	data = ((data >> 0) & MAC_L3L4CR_L3PEN0_MASK);\
} while (0)

#define MAC_PPS_WIDTH_OFFSET (BASE_ADDRESS + 0xb8c)

#define MAC_PPS_WIDTH_OFFSET_Q(i) ((volatile ULONG *)(MAC_PPS_WIDTH_OFFSET + ((i-0)*16)))

#define MAC_PPS_WIDTH_WR(i, data) do {\
	iowrite32(data, (void *)MAC_PPS_WIDTH_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_WIDTH_RD(i, data) do {\
	(data) = ioread32((void *)MAC_PPS_WIDTH_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_WIDTH_PPSWIDTH0_WR(i, data) do {\
	MAC_PPS_WIDTH_WR(i, data);\
} while (0)

#define MAC_PPS_WIDTH_PPSWIDTH0_RD(i, data) do {\
	MAC_PPS_WIDTH_RD(i, data);\
} while (0)

#define MAC_PPS_INTVAL_OFFSET (BASE_ADDRESS + 0xb88)

#define MAC_PPS_INTVAL_OFFSET_Q(i) ((volatile ULONG *)(MAC_PPS_INTVAL_OFFSET + ((i-0)*16)))

#define MAC_PPS_INTVAL_WR(i, data) do {\
	iowrite32(data, (void *)MAC_PPS_INTVAL_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_INTVAL_RD(i, data) do {\
	(data) = ioread32((void *)MAC_PPS_INTVAL_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_INTVAL_PPSINT0_WR(i, data) do {\
	MAC_PPS_INTVAL_WR(i, data);\
} while (0)

#define MAC_PPS_INTVAL_PPSINT0_RD(i, data) do {\
	MAC_PPS_INTVAL_RD(i, data);\
} while (0)

#define MAC_PPS_TTNS_OFFSET (BASE_ADDRESS + 0xb84)

#define MAC_PPS_TTNS_OFFSET_Q(i) ((volatile ULONG *)(MAC_PPS_TTNS_OFFSET + ((i-0)*16)))

#define MAC_PPS_TTNS_WR(i, data) do {\
	iowrite32(data, (void *)MAC_PPS_TTNS_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_TTNS_RD(i, data) do {\
	(data) = ioread32((void *)MAC_PPS_TTNS_OFFSET_Q(i));\
} while (0)


#define MAC_PPS_TTNS_TRGTBUSY0_MASK (ULONG)(0x1)


#define MAC_PPS_TTNS_TRGTBUSY0_WR_MASK (ULONG)(0x7fffffff)

#define MAC_PPS_TTNS_TRGTBUSY0_WR(i, data) do {\
	ULONG v;\
	MAC_PPS_TTNS_RD(i, v);\
	v = ((v & MAC_PPS_TTNS_TRGTBUSY0_WR_MASK)\
	|((data & MAC_PPS_TTNS_TRGTBUSY0_MASK)<<31));\
	MAC_PPS_TTNS_WR(i, v);\
} while (0)

#define MAC_PPS_TTNS_TRGTBUSY0_RD(i, data) do {\
	MAC_PPS_TTNS_RD(i, data);\
	data = ((data >> 31) & MAC_PPS_TTNS_TRGTBUSY0_MASK);\
} while (0)


#define MAC_PPS_TTNS_TTSL0_MASK (ULONG)(0x7fffffff)


#define MAC_PPS_TTNS_TTSL0_WR_MASK (ULONG)(0x80000000)

#define MAC_PPS_TTNS_TTSL0_WR(i, data) do {\
	ULONG v;\
	MAC_PPS_TTNS_RD(i, v);\
	v = ((v & MAC_PPS_TTNS_TTSL0_WR_MASK)\
	|((data & MAC_PPS_TTNS_TTSL0_MASK)<<0));\
	MAC_PPS_TTNS_WR(i, v);\
} while (0)

#define MAC_PPS_TTNS_TTSL0_RD(i, data) do {\
	MAC_PPS_TTNS_RD(i, data);\
	data = ((data >> 0) & MAC_PPS_TTNS_TTSL0_MASK);\
} while (0)

#define MAC_PPS_TTS_OFFSET (BASE_ADDRESS + 0xb80)

#define MAC_PPS_TTS_OFFSET_Q(i) ((volatile ULONG *)(MAC_PPS_TTS_OFFSET + ((i-0)*16)))

#define MAC_PPS_TTS_WR(i, data) do {\
	iowrite32(data, (void *)MAC_PPS_TTS_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_TTS_RD(i, data) do {\
	(data) = ioread32((void *)MAC_PPS_TTS_OFFSET_Q(i));\
} while (0)

#define MAC_PPS_TTS_TSTRH0_WR(i, data) do {\
	MAC_PPS_TTS_WR(i, data);\
} while (0)

#define MAC_PPS_TTS_TSTRH0_RD(i, data) do {\
	MAC_PPS_TTS_RD(i, data);\
} while (0)

#define MTL_QRCR_OFFSET (BASE_ADDRESS + 0xd3c)

#define MTL_QRCR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QRCR_OFFSET + ((i-0)*64)))

#define MTL_QRCR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QRCR_OFFSET_Q(i));\
} while (0)

#define MTL_QRCR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QRCR_OFFSET_Q(i));\
} while (0)


#define  MTL_QRCR_MASK_4 (ULONG)(0xfffffff)


#define MTL_QRCR_RES_WR_MASK_4 (ULONG)(0xf)


#define MTL_QRCR_RXQ_PKT_ARBIT_MASK (ULONG)(0x1)


#define MTL_QRCR_RXQ_PKT_ARBIT_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QRCR_RXQ_PKT_ARBIT_WR(i, data) do {\
	ULONG v;\
	MTL_QRCR_RD(i, v);\
	v = (v & (MTL_QRCR_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR_MASK_4))<<4);\
	v = ((v & MTL_QRCR_RXQ_PKT_ARBIT_WR_MASK)\
	|((data & MTL_QRCR_RXQ_PKT_ARBIT_MASK)<<3));\
	MTL_QRCR_WR(i, v);\
} while (0)

#define MTL_QRCR_RXQ_PKT_ARBIT_RD(i, data) do {\
	MTL_QRCR_RD(i, data);\
	data = ((data >> 3) & MTL_QRCR_RXQ_PKT_ARBIT_MASK);\
} while (0)


#define MTL_QRCR_RXQ_WEGT_MASK (ULONG)(0x7)


#define MTL_QRCR_RXQ_WEGT_WR_MASK (ULONG)(0xfffffff8)

#define MTL_QRCR_RXQ_WEGT_WR(i, data) do {\
	ULONG v;\
	MTL_QRCR_RD(i, v);\
	v = (v & (MTL_QRCR_RES_WR_MASK_4))\
	|(((0) & (MTL_QRCR_MASK_4))<<4);\
	v = ((v & MTL_QRCR_RXQ_WEGT_WR_MASK)\
	|((data & MTL_QRCR_RXQ_WEGT_MASK)<<0));\
	MTL_QRCR_WR(i, v);\
} while (0)

#define MTL_QRCR_RXQ_WEGT_RD(i, data) do {\
	MTL_QRCR_RD(i, data);\
	data = ((data >> 0) & MTL_QRCR_RXQ_WEGT_MASK);\
} while (0)

#define MTL_QRDR_OFFSET (BASE_ADDRESS + 0xd38)

#define MTL_QRDR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QRDR_OFFSET + ((i-3)*64)))

#define MTL_QRDR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QRDR_OFFSET_Q(i));\
} while (0)


#define MTL_QRDR_PRXQ_MASK (ULONG)(0x3fff)

#define MTL_QRDR_PRXQ_RD(i, data) do {\
	MTL_QRDR_RD(i, data);\
	data = ((data >> 16) & MTL_QRDR_PRXQ_MASK);\
} while (0)


#define MTL_QRDR_RXQSTS_MASK (ULONG)(0x3)

#define MTL_QRDR_RXQSTS_RD(i, data) do {\
	MTL_QRDR_RD(i, data);\
	data = ((data >> 4) & MTL_QRDR_RXQSTS_MASK);\
} while (0)


#define MTL_QRDR_RRCSTS_MASK (ULONG)(0x3)

#define MTL_QRDR_RRCSTS_RD(i, data) do {\
	MTL_QRDR_RD(i, data);\
	data = ((data >> 1) & MTL_QRDR_RRCSTS_MASK);\
} while (0)


#define MTL_QRDR_RWCSTS_MASK (ULONG)(0x1)

#define MTL_QRDR_RWCSTS_RD(i, data) do {\
	MTL_QRDR_RD(i, data);\
	data = ((data >> 0) & MTL_QRDR_RWCSTS_MASK);\
} while (0)

#define MTL_QOCR_OFFSET (BASE_ADDRESS + 0xd34)

#define MTL_QOCR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QOCR_OFFSET + ((i-0)*64)))

#define MTL_QOCR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QOCR_OFFSET_Q(i));\
} while (0)

#define MTL_QOCR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QOCR_OFFSET_Q(i));\
} while (0)


#define  MTL_QOCR_MASK_28 (ULONG)(0xf)


#define MTL_QOCR_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define  MTL_QOCR_MASK_12 (ULONG)(0xf)


#define MTL_QOCR_RES_WR_MASK_12 (ULONG)(0xffff0fff)


#define MTL_QOCR_MISCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR_MISCNTOVF_WR_MASK (ULONG)(0xf7ffffff)

#define MTL_QOCR_MISCNTOVF_WR(i, data) do {\
	ULONG v;\
	MTL_QOCR_RD(i, v);\
	v = (v & (MTL_QOCR_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR_MASK_28))<<28);\
	v = (v & (MTL_QOCR_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR_MASK_12))<<12);\
	v = ((v & MTL_QOCR_MISCNTOVF_WR_MASK)\
	|((data & MTL_QOCR_MISCNTOVF_MASK)<<27));\
	MTL_QOCR_WR(i, v);\
} while (0)

#define MTL_QOCR_MISCNTOVF_RD(i, data) do {\
	MTL_QOCR_RD(i, data);\
	data = ((data >> 27) & MTL_QOCR_MISCNTOVF_MASK);\
} while (0)


#define MTL_QOCR_MISPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR_MISPKTCNT_WR_MASK (ULONG)(0xf800ffff)

#define MTL_QOCR_MISPKTCNT_WR(i, data) do {\
	ULONG v;\
	MTL_QOCR_RD(i, v);\
	v = (v & (MTL_QOCR_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR_MASK_28))<<28);\
	v = (v & (MTL_QOCR_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR_MASK_12))<<12);\
	v = ((v & MTL_QOCR_MISPKTCNT_WR_MASK)\
	|((data & MTL_QOCR_MISPKTCNT_MASK)<<16));\
	MTL_QOCR_WR(i, v);\
} while (0)

#define MTL_QOCR_MISPKTCNT_RD(i, data) do {\
	MTL_QOCR_RD(i, data);\
	data = ((data >> 16) & MTL_QOCR_MISPKTCNT_MASK);\
} while (0)


#define MTL_QOCR_OVFCNTOVF_MASK (ULONG)(0x1)


#define MTL_QOCR_OVFCNTOVF_WR_MASK (ULONG)(0xfffff7ff)

#define MTL_QOCR_OVFCNTOVF_WR(i, data) do {\
	ULONG v;\
	MTL_QOCR_RD(i, v);\
	v = (v & (MTL_QOCR_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR_MASK_28))<<28);\
	v = (v & (MTL_QOCR_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR_MASK_12))<<12);\
	v = ((v & MTL_QOCR_OVFCNTOVF_WR_MASK)\
	|((data & MTL_QOCR_OVFCNTOVF_MASK)<<11));\
	MTL_QOCR_WR(i, v);\
} while (0)

#define MTL_QOCR_OVFCNTOVF_RD(i, data) do {\
	MTL_QOCR_RD(i, data);\
	data = ((data >> 11) & MTL_QOCR_OVFCNTOVF_MASK);\
} while (0)


#define MTL_QOCR_OVFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QOCR_OVFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QOCR_OVFPKTCNT_WR(i, data) do {\
	ULONG v;\
	MTL_QOCR_RD(i, v);\
	v = (v & (MTL_QOCR_RES_WR_MASK_28))\
	|(((0) & (MTL_QOCR_MASK_28))<<28);\
	v = (v & (MTL_QOCR_RES_WR_MASK_12))\
	|(((0) & (MTL_QOCR_MASK_12))<<12);\
	v = ((v & MTL_QOCR_OVFPKTCNT_WR_MASK)\
	|((data & MTL_QOCR_OVFPKTCNT_MASK)<<0));\
	MTL_QOCR_WR(i, v);\
} while (0)

#define MTL_QOCR_OVFPKTCNT_RD(i, data) do {\
	MTL_QOCR_RD(i, data);\
	data = ((data >> 0) & MTL_QOCR_OVFPKTCNT_MASK);\
} while (0)

#define MTL_QROMR_OFFSET (BASE_ADDRESS + 0xd30)

#define MTL_QROMR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QROMR_OFFSET + ((i-0)*64)))

#define MTL_QROMR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QROMR_OFFSET_Q(i));\
} while (0)

#define MTL_QROMR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QROMR_OFFSET_Q(i));\
} while (0)

#ifdef EQOS_VER_4_0


#define  MTL_QROMR_MASK_30 (ULONG)(0x3)


#define MTL_QROMR_RES_WR_MASK_30 (ULONG)(0x3fffffff)


#define  MTL_QROMR_MASK_16 (ULONG)(0xf)


#define MTL_QROMR_RES_WR_MASK_16 (ULONG)(0xfff0ffff)


#define  MTL_QROMR_MASK_11 (ULONG)(0x3)


#define MTL_QROMR_RES_WR_MASK_11 (ULONG)(0xffffe7ff)


#define  MTL_QROMR_MASK_2 (ULONG)(0x1)


#define MTL_QROMR_RES_WR_MASK_2 (ULONG)(0xfffffffb)


#define MTL_QROMR_RQS_MASK (ULONG)(0x3ff)


#define MTL_QROMR_RQS_WR_MASK (ULONG)(0xc00fffff)

#define MTL_QROMR_RQS_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RQS_WR_MASK)\
	|((data & MTL_QROMR_RQS_MASK)<<20));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RQS_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 20) & MTL_QROMR_RQS_MASK);\
} while (0)


#define MTL_QROMR_RFD_MASK (ULONG)(0x7)


#define MTL_QROMR_RFD_WR_MASK (ULONG)(0xffff1fff)

#define MTL_QROMR_RFD_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RFD_WR_MASK)\
	|((data & MTL_QROMR_RFD_MASK)<<13));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RFD_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 13) & MTL_QROMR_RFD_MASK);\
} while (0)


#define MTL_QROMR_RFA_MASK (ULONG)(0x7)


#define MTL_QROMR_RFA_WR_MASK (ULONG)(0xfffff8ff)

#define MTL_QROMR_RFA_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RFA_WR_MASK)\
	|((data & MTL_QROMR_RFA_MASK)<<8));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RFA_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 8) & MTL_QROMR_RFA_MASK);\
} while (0)


#define MTL_QROMR_EHFC_MASK (ULONG)(0x1)


#define MTL_QROMR_EHFC_WR_MASK (ULONG)(0xffffff7f)

#define MTL_QROMR_EHFC_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_EHFC_WR_MASK)\
	|((data & MTL_QROMR_EHFC_MASK)<<7));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_EHFC_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 7) & MTL_QROMR_EHFC_MASK);\
} while (0)


#define MTL_QROMR_DIS_TCP_EF_MASK (ULONG)(0x1)


#define MTL_QROMR_DIS_TCP_EF_WR_MASK (ULONG)(0xffffffbf)

#define MTL_QROMR_DIS_TCP_EF_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_DIS_TCP_EF_WR_MASK)\
	|((data & MTL_QROMR_DIS_TCP_EF_MASK)<<6));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_DIS_TCP_EF_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 6) & MTL_QROMR_DIS_TCP_EF_MASK);\
} while (0)


#define MTL_QROMR_RSF_MASK (ULONG)(0x1)


#define MTL_QROMR_RSF_WR_MASK (ULONG)(0xffffffdf)

#define MTL_QROMR_RSF_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RSF_WR_MASK)\
	|((data & MTL_QROMR_RSF_MASK)<<5));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RSF_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 5) & MTL_QROMR_RSF_MASK);\
} while (0)


#define MTL_QROMR_FEP_MASK (ULONG)(0x1)


#define MTL_QROMR_FEP_WR_MASK (ULONG)(0xffffffef)

#define MTL_QROMR_FEP_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_FEP_WR_MASK)\
	|((data & MTL_QROMR_FEP_MASK)<<4));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_FEP_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 4) & MTL_QROMR_FEP_MASK);\
} while (0)


#define MTL_QROMR_FUP_MASK (ULONG)(0x1)


#define MTL_QROMR_FUP_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QROMR_FUP_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_FUP_WR_MASK)\
	|((data & MTL_QROMR_FUP_MASK)<<3));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_FUP_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 3) & MTL_QROMR_FUP_MASK);\
} while (0)


#define MTL_QROMR_RTC_MASK (ULONG)(0x3)


#define MTL_QROMR_RTC_WR_MASK (ULONG)(0xfffffffc)

#define MTL_QROMR_RTC_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_16))\
	|(((0) & (MTL_QROMR_MASK_16))<<16);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RTC_WR_MASK)\
	|((data & MTL_QROMR_RTC_MASK)<<0));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RTC_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 0) & MTL_QROMR_RTC_MASK);\
} while (0)

#else


#define  MTL_QROMR_MASK_30 (ULONG)(0x3)


#define MTL_QROMR_RES_WR_MASK_30 (ULONG)(0x3fffffff)


#define  MTL_QROMR_MASK_11 (ULONG)(0x3)


#define MTL_QROMR_RES_WR_MASK_11 (ULONG)(0xffffe7ff)


#define  MTL_QROMR_MASK_2 (ULONG)(0x1)


#define MTL_QROMR_RES_WR_MASK_2 (ULONG)(0xfffffffb)


#define MTL_QROMR_RQS_MASK (ULONG)(0x3ff)


#define MTL_QROMR_RQS_WR_MASK (ULONG)(0xc00fffff)

#define MTL_QROMR_RQS_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RQS_WR_MASK)\
	|((data & MTL_QROMR_RQS_MASK)<<20));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RQS_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 20) & MTL_QROMR_RQS_MASK);\
} while (0)

#define MTL_QROMR_RFD_MASK (ULONG)(0x3f)
#define MTL_QROMR_RFD_WR_MASK (ULONG)(0xfff03fff)

#define MTL_QROMR_RFD_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RFD_WR_MASK)\
	|((data & MTL_QROMR_RFD_MASK)<<14));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RFD_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 14) & MTL_QROMR_RFD_MASK);\
} while (0)

#define MTL_QROMR_RFA_MASK (ULONG)(0x3f)
#define MTL_QROMR_RFA_WR_MASK (ULONG)(0xffffc0ff)

#define MTL_QROMR_RFA_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RFA_WR_MASK)\
	|((data & MTL_QROMR_RFA_MASK)<<8));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RFA_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 8) & MTL_QROMR_RFA_MASK);\
} while (0)


#define MTL_QROMR_EHFC_MASK (ULONG)(0x1)


#define MTL_QROMR_EHFC_WR_MASK (ULONG)(0xffffff7f)

#define MTL_QROMR_EHFC_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_EHFC_WR_MASK)\
	|((data & MTL_QROMR_EHFC_MASK)<<7));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_EHFC_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 7) & MTL_QROMR_EHFC_MASK);\
} while (0)


#define MTL_QROMR_DIS_TCP_EF_MASK (ULONG)(0x1)


#define MTL_QROMR_DIS_TCP_EF_WR_MASK (ULONG)(0xffffffbf)

#define MTL_QROMR_DIS_TCP_EF_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_DIS_TCP_EF_WR_MASK)\
	|((data & MTL_QROMR_DIS_TCP_EF_MASK)<<6));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_DIS_TCP_EF_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 6) & MTL_QROMR_DIS_TCP_EF_MASK);\
} while (0)


#define MTL_QROMR_RSF_MASK (ULONG)(0x1)


#define MTL_QROMR_RSF_WR_MASK (ULONG)(0xffffffdf)

#define MTL_QROMR_RSF_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RSF_WR_MASK)\
	|((data & MTL_QROMR_RSF_MASK)<<5));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RSF_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 5) & MTL_QROMR_RSF_MASK);\
} while (0)


#define MTL_QROMR_FEP_MASK (ULONG)(0x1)


#define MTL_QROMR_FEP_WR_MASK (ULONG)(0xffffffef)

#define MTL_QROMR_FEP_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_FEP_WR_MASK)\
	|((data & MTL_QROMR_FEP_MASK)<<4));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_FEP_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 4) & MTL_QROMR_FEP_MASK);\
} while (0)


#define MTL_QROMR_FUP_MASK (ULONG)(0x1)


#define MTL_QROMR_FUP_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QROMR_FUP_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_FUP_WR_MASK)\
	|((data & MTL_QROMR_FUP_MASK)<<3));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_FUP_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 3) & MTL_QROMR_FUP_MASK);\
} while (0)


#define MTL_QROMR_RTC_MASK (ULONG)(0x3)


#define MTL_QROMR_RTC_WR_MASK (ULONG)(0xfffffffc)

#define MTL_QROMR_RTC_WR(i, data) do {\
	ULONG v;\
	MTL_QROMR_RD(i, v);\
	v = (v & (MTL_QROMR_RES_WR_MASK_30))\
	|(((0) & (MTL_QROMR_MASK_30))<<30);\
	v = (v & (MTL_QROMR_RES_WR_MASK_11))\
	|(((0) & (MTL_QROMR_MASK_11))<<11);\
	v = (v & (MTL_QROMR_RES_WR_MASK_2))\
	|(((0) & (MTL_QROMR_MASK_2))<<2);\
	v = ((v & MTL_QROMR_RTC_WR_MASK)\
	|((data & MTL_QROMR_RTC_MASK)<<0));\
	MTL_QROMR_WR(i, v);\
} while (0)

#define MTL_QROMR_RTC_RD(i, data) do {\
	MTL_QROMR_RD(i, data);\
	data = ((data >> 0) & MTL_QROMR_RTC_MASK);\
} while (0)

#endif

#define MTL_QLCR_OFFSET (BASE_ADDRESS + 0xd24)

#define MTL_QLCR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QLCR_OFFSET + ((i-0)*64)))

#define MTL_QLCR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QLCR_OFFSET_Q(i));\
} while (0)

#define MTL_QLCR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QLCR_OFFSET_Q(i));\
} while (0)


#define  MTL_QLCR_MASK_29 (ULONG)(0x7)


#define MTL_QLCR_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QLCR_LC_MASK (ULONG)(0x1fffffff)


#define MTL_QLCR_LC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QLCR_LC_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QLCR_RES_WR_MASK_29))\
	|(((0) & (MTL_QLCR_MASK_29))<<29);\
	(v) = ((v & MTL_QLCR_LC_WR_MASK)\
	|((data & MTL_QLCR_LC_MASK)<<0));\
	MTL_QLCR_WR(i, v);\
} while (0)

#define MTL_QLCR_LC_RD(i, data) do {\
	MTL_QLCR_RD(i, data);\
	data = ((data >> 0) & MTL_QLCR_LC_MASK);\
} while (0)

#define MTL_QHCR_OFFSET (BASE_ADDRESS + 0xd20)

#define MTL_QHCR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QHCR_OFFSET + ((i-0)*64)))

#define MTL_QHCR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QHCR_OFFSET_Q(i));\
} while (0)

#define MTL_QHCR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QHCR_OFFSET_Q(i));\
} while (0)


#define  MTL_QHCR_MASK_29 (ULONG)(0x7)


#define MTL_QHCR_RES_WR_MASK_29 (ULONG)(0x1fffffff)


#define MTL_QHCR_HC_MASK (ULONG)(0x1fffffff)


#define MTL_QHCR_HC_WR_MASK (ULONG)(0xe0000000)

#define MTL_QHCR_HC_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QHCR_RES_WR_MASK_29))\
	|(((0) & (MTL_QHCR_MASK_29))<<29);\
	(v) = ((v & MTL_QHCR_HC_WR_MASK)\
	|((data & MTL_QHCR_HC_MASK)<<0));\
	MTL_QHCR_WR(i, v);\
} while (0)

#define MTL_QHCR_HC_RD(i, data) do {\
	MTL_QHCR_RD(i, data);\
	data = ((data >> 0) & MTL_QHCR_HC_MASK);\
} while (0)

#define MTL_QSSCR_OFFSET (BASE_ADDRESS + 0xd1c)

#define MTL_QSSCR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QSSCR_OFFSET + ((i-0)*64)))

#define MTL_QSSCR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QSSCR_OFFSET_Q(i));\
} while (0)

#define MTL_QSSCR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QSSCR_OFFSET_Q(i));\
} while (0)


#define  MTL_QSSCR_MASK_14 (ULONG)(0x3ffff)


#define MTL_QSSCR_RES_WR_MASK_14 (ULONG)(0x3fff)


#define MTL_QSSCR_SSC_MASK (ULONG)(0x3fff)


#define MTL_QSSCR_SSC_WR_MASK (ULONG)(0xffffc000)

#define MTL_QSSCR_SSC_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QSSCR_RES_WR_MASK_14))\
	|(((0) & (MTL_QSSCR_MASK_14))<<14);\
	(v) = ((v & MTL_QSSCR_SSC_WR_MASK)\
	|((data & MTL_QSSCR_SSC_MASK)<<0));\
	MTL_QSSCR_WR(i, v);\
} while (0)

#define MTL_QSSCR_SSC_RD(i, data) do {\
	MTL_QSSCR_RD(i, data);\
	data = ((data >> 0) & MTL_QSSCR_SSC_MASK);\
} while (0)

#define MTL_QW_OFFSET (BASE_ADDRESS + 0xd18)

#define MTL_QW_OFFSET_Q(i) ((volatile ULONG *)(MTL_QW_OFFSET + ((i-0)*64)))

#define MTL_QW_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QW_OFFSET_Q(i));\
} while (0)

#define MTL_QW_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QW_OFFSET_Q(i));\
} while (0)


#define  MTL_QW_MASK_21 (ULONG)(0x7ff)


#define MTL_QW_RES_WR_MASK_21 (ULONG)(0x1fffff)


#define MTL_QW_ISCQW_MASK (ULONG)(0x1fffff)


#define MTL_QW_ISCQW_WR_MASK (ULONG)(0xffe00000)

#define MTL_QW_ISCQW_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (MTL_QW_RES_WR_MASK_21))\
	|(((0) & (MTL_QW_MASK_21))<<21);\
	(v) = ((v & MTL_QW_ISCQW_WR_MASK)\
	|((data & MTL_QW_ISCQW_MASK)<<0));\
	MTL_QW_WR(i, v);\
} while (0)

#define MTL_QW_ISCQW_RD(i, data) do {\
	MTL_QW_RD(i, data);\
	data = ((data >> 0) & MTL_QW_ISCQW_MASK);\
} while (0)

#define MTL_QESR_OFFSET (BASE_ADDRESS + 0xd14)

#define MTL_QESR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QESR_OFFSET + ((i-0)*64)))

#define MTL_QESR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QESR_OFFSET_Q(i));\
} while (0)


#define MTL_QESR_ABSU_MASK (ULONG)(0x1)

#define MTL_QESR_ABSU_RD(i, data) do {\
	MTL_QESR_RD(i, data);\
	data = ((data >> 24) & MTL_QESR_ABSU_MASK);\
} while (0)


#define MTL_QESR_ABS_MASK (ULONG)(0xffffff)

#define MTL_QESR_ABS_RD(i, data) do {\
	MTL_QESR_RD(i, data);\
	data = ((data >> 0) & MTL_QESR_ABS_MASK);\
} while (0)

#define MTL_QECR_OFFSET (BASE_ADDRESS + 0xd10)

#define MTL_QECR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QECR_OFFSET + ((i-0)*64)))

#define MTL_QECR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QECR_OFFSET_Q(i));\
} while (0)

#define MTL_QECR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QECR_OFFSET_Q(i));\
} while (0)


#define  MTL_QECR_MASK_25 (ULONG)(0x7f)


#define MTL_QECR_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define  MTL_QECR_MASK_7 (ULONG)(0x1ffff)


#define MTL_QECR_RES_WR_MASK_7 (ULONG)(0xff00007f)


#define  MTL_QECR_MASK_0 (ULONG)(0x3)


#define MTL_QECR_RES_WR_MASK_0 (ULONG)(0xfffffffc)


#define MTL_QECR_ABPSSIE_MASK (ULONG)(0x1)


#define MTL_QECR_ABPSSIE_WR_MASK (ULONG)(0xfeffffff)

#define MTL_QECR_ABPSSIE_WR(i, data) do {\
	ULONG v;\
	MTL_QECR_RD(i, v);\
	v = (v & (MTL_QECR_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR_MASK_25))<<25);\
	v = (v & (MTL_QECR_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR_MASK_7))<<7);\
	v = (v & (MTL_QECR_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR_MASK_0))<<0);\
	v = ((v & MTL_QECR_ABPSSIE_WR_MASK)\
	|((data & MTL_QECR_ABPSSIE_MASK)<<24));\
	MTL_QECR_WR(i, v);\
} while (0)

#define MTL_QECR_ABPSSIE_RD(i, data) do {\
	MTL_QECR_RD(i, data);\
	data = ((data >> 24) & MTL_QECR_ABPSSIE_MASK);\
} while (0)


#define MTL_QECR_SLC_MASK (ULONG)(0x7)


#define MTL_QECR_SLC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QECR_SLC_WR(i, data) do {\
	ULONG v;\
	MTL_QECR_RD(i, v);\
	v = (v & (MTL_QECR_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR_MASK_25))<<25);\
	v = (v & (MTL_QECR_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR_MASK_7))<<7);\
	v = (v & (MTL_QECR_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR_MASK_0))<<0);\
	v = ((v & MTL_QECR_SLC_WR_MASK)\
	|((data & MTL_QECR_SLC_MASK)<<4));\
	MTL_QECR_WR(i, v);\
} while (0)

#define MTL_QECR_SLC_RD(i, data) do {\
	MTL_QECR_RD(i, data);\
	data = ((data >> 4) & MTL_QECR_SLC_MASK);\
} while (0)


#define MTL_QECR_CC_MASK (ULONG)(0x1)


#define MTL_QECR_CC_WR_MASK (ULONG)(0xfffffff7)

#define MTL_QECR_CC_WR(i, data) do {\
	ULONG v;\
	MTL_QECR_RD(i, v);\
	v = (v & (MTL_QECR_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR_MASK_25))<<25);\
	v = (v & (MTL_QECR_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR_MASK_7))<<7);\
	v = (v & (MTL_QECR_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR_MASK_0))<<0);\
	v = ((v & MTL_QECR_CC_WR_MASK)\
	|((data & MTL_QECR_CC_MASK)<<3));\
	MTL_QECR_WR(i, v);\
} while (0)

#define MTL_QECR_CC_RD(i, data) do {\
	MTL_QECR_RD(i, data);\
	data = ((data >> 3) & MTL_QECR_CC_MASK);\
} while (0)


#define MTL_QECR_AVALG_MASK (ULONG)(0x1)


#define MTL_QECR_AVALG_WR_MASK (ULONG)(0xfffffffb)

#define MTL_QECR_AVALG_WR(i, data) do {\
	ULONG v;\
	MTL_QECR_RD(i, v);\
	v = (v & (MTL_QECR_RES_WR_MASK_25))\
	|(((0) & (MTL_QECR_MASK_25))<<25);\
	v = (v & (MTL_QECR_RES_WR_MASK_7))\
	|(((0) & (MTL_QECR_MASK_7))<<7);\
	v = (v & (MTL_QECR_RES_WR_MASK_0))\
	|(((0) & (MTL_QECR_MASK_0))<<0);\
	v = ((v & MTL_QECR_AVALG_WR_MASK)\
	|((data & MTL_QECR_AVALG_MASK)<<2));\
	MTL_QECR_WR(i, v);\
} while (0)

#define MTL_QECR_AVALG_RD(i, data) do {\
	MTL_QECR_RD(i, data);\
	data = ((data >> 2) & MTL_QECR_AVALG_MASK);\
} while (0)

#define MTL_QTDR_OFFSET (BASE_ADDRESS + 0xd08)

#define MTL_QTDR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QTDR_OFFSET + ((i-0)*64)))

#define MTL_QTDR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QTDR_OFFSET_Q(i));\
} while (0)


#define MTL_QTDR_STXSTSF_MASK (ULONG)(0x7)

#define MTL_QTDR_STXSTSF_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 20) & MTL_QTDR_STXSTSF_MASK);\
} while (0)


#define MTL_QTDR_PTXQ_MASK (ULONG)(0x7)

#define MTL_QTDR_PTXQ_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 16) & MTL_QTDR_PTXQ_MASK);\
} while (0)


#define MTL_QTDR_TXSTSFSTS_MASK (ULONG)(0x1)

#define MTL_QTDR_TXSTSFSTS_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 5) & MTL_QTDR_TXSTSFSTS_MASK);\
} while (0)


#define MTL_QTDR_TXQSTS_MASK (ULONG)(0x1)

#define MTL_QTDR_TXQSTS_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 4) & MTL_QTDR_TXQSTS_MASK);\
} while (0)


#define MTL_QTDR_TWCSTS_MASK (ULONG)(0x1)

#define MTL_QTDR_TWCSTS_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 3) & MTL_QTDR_TWCSTS_MASK);\
} while (0)


#define MTL_QTDR_TRCSTS_MASK (ULONG)(0x3)

#define MTL_QTDR_TRCSTS_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 1) & MTL_QTDR_TRCSTS_MASK);\
} while (0)


#define MTL_QTDR_TXQPAUSED_MASK (ULONG)(0x1)

#define MTL_QTDR_TXQPAUSED_RD(i, data) do {\
	MTL_QTDR_RD(i, data);\
	data = ((data >> 0) & MTL_QTDR_TXQPAUSED_MASK);\
} while (0)

#define MTL_QUCR_OFFSET (BASE_ADDRESS + 0xd04)

#define MTL_QUCR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QUCR_OFFSET + ((i-0)*64)))

#define MTL_QUCR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QUCR_OFFSET_Q(i));\
} while (0)

#define MTL_QUCR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QUCR_OFFSET_Q(i));\
} while (0)


#define  MTL_QUCR_MASK_12 (ULONG)(0xfffff)


#define MTL_QUCR_RES_WR_MASK_12 (ULONG)(0xfff)


#define MTL_QUCR_UFCNTOVF_MASK (ULONG)(0x1)

#define MTL_QUCR_UFCNTOVF_RD(i, data) do {\
	MTL_QUCR_RD(i, data);\
	data = ((data >> 11) & MTL_QUCR_UFCNTOVF_MASK);\
} while (0)


#define MTL_QUCR_UFPKTCNT_MASK (ULONG)(0x7ff)


#define MTL_QUCR_UFPKTCNT_WR_MASK (ULONG)(0xfffff800)

#define MTL_QUCR_UFPKTCNT_WR(i, data) do {\
	ULONG v;\
	MTL_QUCR_RD(i, v);\
	v = (v & (MTL_QUCR_RES_WR_MASK_12))\
	|(((0) & (MTL_QUCR_MASK_12))<<12);\
	v = ((v & MTL_QUCR_UFPKTCNT_WR_MASK)\
	|((data & MTL_QUCR_UFPKTCNT_MASK)<<0));\
	MTL_QUCR_WR(i, v);\
} while (0)

#define MTL_QUCR_UFPKTCNT_RD(i, data) do {\
	MTL_QUCR_RD(i, data);\
	data = ((data >> 0) & MTL_QUCR_UFPKTCNT_MASK);\
} while (0)

#define MTL_QTOMR_OFFSET (BASE_ADDRESS + 0xd00)

#define MTL_QTOMR_OFFSET_Q(i) ((volatile ULONG *)(MTL_QTOMR_OFFSET + ((i-0)*64)))

#define MTL_QTOMR_WR(i, data) do {\
	iowrite32(data, (void *)MTL_QTOMR_OFFSET_Q(i));\
} while (0)

#define MTL_QTOMR_RD(i, data) do {\
	(data) = ioread32((void *)MTL_QTOMR_OFFSET_Q(i));\
} while (0)


#define  MTL_QTOMR_MASK_26 (ULONG)(0x3f)


#define MTL_QTOMR_RES_WR_MASK_26 (ULONG)(0x3ffffff)


#define  MTL_QTOMR_MASK_7 (ULONG)(0x1ff)


#define MTL_QTOMR_RES_WR_MASK_7 (ULONG)(0xffff007f)


#define MTL_QTOMR_TQS_MASK (ULONG)(0x3ff)


#define MTL_QTOMR_TQS_WR_MASK (ULONG)(0xfc00ffff)

#define MTL_QTOMR_TQS_WR(i, data) do {\
	ULONG v;\
	MTL_QTOMR_RD(i, v);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR_MASK_26))<<26);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR_MASK_7))<<7);\
	v = ((v & MTL_QTOMR_TQS_WR_MASK)\
	|((data & MTL_QTOMR_TQS_MASK)<<16));\
	MTL_QTOMR_WR(i, v);\
} while (0)

#define MTL_QTOMR_TQS_RD(i, data) do {\
	MTL_QTOMR_RD(i, data);\
	data = ((data >> 16) & MTL_QTOMR_TQS_MASK);\
} while (0)


#define MTL_QTOMR_TTC_MASK (ULONG)(0x7)


#define MTL_QTOMR_TTC_WR_MASK (ULONG)(0xffffff8f)

#define MTL_QTOMR_TTC_WR(i, data) do {\
	ULONG v;\
	MTL_QTOMR_RD(i, v);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR_MASK_26))<<26);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR_MASK_7))<<7);\
	v = ((v & MTL_QTOMR_TTC_WR_MASK)\
	|((data & MTL_QTOMR_TTC_MASK)<<4));\
	MTL_QTOMR_WR(i, v);\
} while (0)

#define MTL_QTOMR_TTC_RD(i, data) do {\
	MTL_QTOMR_RD(i, data);\
	data = ((data >> 4) & MTL_QTOMR_TTC_MASK);\
} while (0)


#define MTL_QTOMR_TXQEN_MASK (ULONG)(0x3)


#define MTL_QTOMR_TXQEN_WR_MASK (ULONG)(0xfffffff3)

#define MTL_QTOMR_TXQEN_WR(i, data) do {\
	ULONG v;\
	MTL_QTOMR_RD(i, v);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR_MASK_26))<<26);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR_MASK_7))<<7);\
	v = ((v & MTL_QTOMR_TXQEN_WR_MASK)\
	|((data & MTL_QTOMR_TXQEN_MASK)<<2));\
	MTL_QTOMR_WR(i, v);\
} while (0)

#define MTL_QTOMR_TXQEN_RD(i, data) do {\
	MTL_QTOMR_RD(i, data);\
	data = ((data >> 2) & MTL_QTOMR_TXQEN_MASK);\
} while (0)


#define MTL_QTOMR_TSF_MASK (ULONG)(0x1)


#define MTL_QTOMR_TSF_WR_MASK (ULONG)(0xfffffffd)

#define MTL_QTOMR_TSF_WR(i, data) do {\
	ULONG v;\
	MTL_QTOMR_RD(i, v);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR_MASK_26))<<26);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR_MASK_7))<<7);\
	v = ((v & MTL_QTOMR_TSF_WR_MASK)\
	|((data & MTL_QTOMR_TSF_MASK)<<1));\
	MTL_QTOMR_WR(i, v);\
} while (0)

#define MTL_QTOMR_TSF_RD(i, data) do {\
	MTL_QTOMR_RD(i, data);\
	data = ((data >> 1) & MTL_QTOMR_TSF_MASK);\
} while (0)


#define MTL_QTOMR_FTQ_MASK (ULONG)(0x1)


#define MTL_QTOMR_FTQ_WR_MASK (ULONG)(0xfffffffe)

#define MTL_QTOMR_FTQ_WR(i, data) do {\
	ULONG v;\
	MTL_QTOMR_RD(i, v);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_26))\
	|(((0) & (MTL_QTOMR_MASK_26))<<26);\
	v = (v & (MTL_QTOMR_RES_WR_MASK_7))\
	|(((0) & (MTL_QTOMR_MASK_7))<<7);\
	v = ((v & MTL_QTOMR_FTQ_WR_MASK)\
	|((data & MTL_QTOMR_FTQ_MASK)<<0));\
	MTL_QTOMR_WR(i, v);\
} while (0)

#define MTL_QTOMR_FTQ_RD(i, data) do {\
	MTL_QTOMR_RD(i, data);\
	data = ((data >> 0) & MTL_QTOMR_FTQ_MASK);\
} while (0)

#define MAC_HTR_OFFSET (BASE_ADDRESS + 0x10)

#define MAC_HTR_OFFSET_Q(i) ((volatile ULONG *)(MAC_HTR_OFFSET + ((i-0)*4)))

#define MAC_HTR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_HTR_OFFSET_Q(i));\
} while (0)

#define MAC_HTR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_HTR_OFFSET_Q(i));\
} while (0)

#define MAC_HTR_HT_WR(i, data) do {\
	MAC_HTR_WR(i, data);\
} while (0)

#define MAC_HTR_HT_RD(i, data) do {\
	MAC_HTR_RD(i, data);\
} while (0)

#define DMA_RIWTR_OFFSET (BASE_ADDRESS + 0x1138)

#define DMA_RIWTR_OFFSET_Q(i) ((volatile ULONG *)(DMA_RIWTR_OFFSET + ((i-0)*128)))

#define DMA_RIWTR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_RIWTR_OFFSET_Q(i));\
} while (0)

#define DMA_RIWTR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_RIWTR_OFFSET_Q(i));\
} while (0)


#define  DMA_RIWTR_MASK_8 (ULONG)(0xffffff)


#define DMA_RIWTR_RES_WR_MASK_8 (ULONG)(0xff)


#define DMA_RIWTR_RWT_MASK (ULONG)(0xff)


#define DMA_RIWTR_RWT_WR_MASK (ULONG)(0xffffff00)

#define DMA_RIWTR_RWT_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RIWTR_RES_WR_MASK_8))\
	|(((0) & (DMA_RIWTR_MASK_8))<<8);\
	(v) = ((v & DMA_RIWTR_RWT_WR_MASK)\
	|((data & DMA_RIWTR_RWT_MASK)<<0));\
	DMA_RIWTR_WR(i, v);\
} while (0)

#define DMA_RIWTR_RWT_RD(i, data) do {\
	DMA_RIWTR_RD(i, data);\
	data = ((data >> 0) & DMA_RIWTR_RWT_MASK);\
} while (0)

#define DMA_RDRLR_OFFSET (BASE_ADDRESS + 0x1130)

#define DMA_RDRLR_OFFSET_Q(i) ((volatile ULONG *)(DMA_RDRLR_OFFSET + ((i-0)*128)))

#define DMA_RDRLR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_RDRLR_OFFSET_Q(i));\
} while (0)

#define DMA_RDRLR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_RDRLR_OFFSET_Q(i));\
} while (0)


#define  DMA_RDRLR_MASK_10 (ULONG)(0x3fffff)


#define DMA_RDRLR_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_RDRLR_RDRL_MASK (ULONG)(0x3ff)


#define DMA_RDRLR_RDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_RDRLR_RDRL_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (DMA_RDRLR_RES_WR_MASK_10))\
	|(((0) & (DMA_RDRLR_MASK_10))<<10);\
	(v) = ((v & DMA_RDRLR_RDRL_WR_MASK)\
	|((data & DMA_RDRLR_RDRL_MASK)<<0));\
	DMA_RDRLR_WR(i, v);\
} while (0)

#define DMA_RDRLR_RDRL_RD(i, data) do {\
	DMA_RDRLR_RD(i, data);\
	data = ((data >> 0) & DMA_RDRLR_RDRL_MASK);\
} while (0)

#define DMA_TDRLR_OFFSET (BASE_ADDRESS + 0x112c)

#define DMA_TDRLR_OFFSET_Q(i) ((volatile ULONG *)(DMA_TDRLR_OFFSET + ((i-0)*128)))

#define DMA_TDRLR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_TDRLR_OFFSET_Q(i));\
} while (0)

#define DMA_TDRLR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_TDRLR_OFFSET_Q(i));\
} while (0)


#define  DMA_TDRLR_MASK_10 (ULONG)(0x3fffff)


#define DMA_TDRLR_RES_WR_MASK_10 (ULONG)(0x3ff)


#define DMA_TDRLR_TDRL_MASK (ULONG)(0x3ff)


#define DMA_TDRLR_TDRL_WR_MASK (ULONG)(0xfffffc00)

#define DMA_TDRLR_TDRL_WR(i, data) do {\
	ULONG v = 0; \
	v = (v & (DMA_TDRLR_RES_WR_MASK_10))\
	|(((0) & (DMA_TDRLR_MASK_10))<<10);\
	(v) = ((v & DMA_TDRLR_TDRL_WR_MASK)\
	|((data & DMA_TDRLR_TDRL_MASK)<<0));\
	DMA_TDRLR_WR(i, v);\
} while (0)

#define DMA_TDRLR_TDRL_RD(i, data) do {\
	DMA_TDRLR_RD(i, data);\
	data = ((data >> 0) & DMA_TDRLR_TDRL_MASK);\
} while (0)

#define DMA_RDTP_RPDR_OFFSET (BASE_ADDRESS + 0x1128)

#define DMA_RDTP_RPDR_OFFSET_Q(i) ((volatile ULONG *)(DMA_RDTP_RPDR_OFFSET + ((i-0)*128)))

#define DMA_RDTP_RPDR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_RDTP_RPDR_OFFSET_Q(i));\
} while (0)

#define DMA_RDTP_RPDR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_RDTP_RPDR_OFFSET_Q(i));\
} while (0)

#define DMA_RDTP_RPDR_RDT_WR(i, data) do {\
	DMA_RDTP_RPDR_WR(i, data);\
} while (0)

#define DMA_RDTP_RPDR_RDT_RD(i, data) do {\
	DMA_RDTP_RPDR_RD(i, data);\
} while (0)

#define DMA_TDTP_TPDR_OFFSET (BASE_ADDRESS + 0x1120)

#define DMA_TDTP_TPDR_OFFSET_Q(i) ((volatile ULONG *)(DMA_TDTP_TPDR_OFFSET + ((i-0)*128)))

#define DMA_TDTP_TPDR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_TDTP_TPDR_OFFSET_Q(i));\
} while (0)

#define DMA_TDTP_TPDR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_TDTP_TPDR_OFFSET_Q(i));\
} while (0)

#define DMA_TDTP_TPDR_TDT_WR(i, data) do {\
	DMA_TDTP_TPDR_WR(i, data);\
} while (0)

#define DMA_TDTP_TPDR_TDT_RD(i, data) do {\
	DMA_TDTP_TPDR_RD(i, data);\
} while (0)

#define DMA_RDLAR_HR_OFFSET (BASE_ADDRESS + 0x1118)

#define DMA_RDLAR_OFFSET (BASE_ADDRESS + 0x111c)

#define DMA_RDLAR_HR_OFFSET_Q(i) ((volatile ULONG *)(DMA_RDLAR_HR_OFFSET + ((i-0)*128)))

#define DMA_RDLAR_OFFSET_Q(i) ((volatile ULONG *)(DMA_RDLAR_OFFSET + ((i-0)*128)))

#define DMA_RDLAR_WR(i, data) do {\
	iowrite32((data>>32) & 0xFFFF, (void *)DMA_RDLAR_HR_OFFSET_Q(i));\
	iowrite32(data & 0xFFFFFFFF, (void *)DMA_RDLAR_OFFSET_Q(i));\
} while (0)

#define DMA_RDLAR_RD(i, data) do {\
	uint64_t hread = ioread32((void *)DMA_RDLAR_HR_OFFSET_Q(i));\
	uint64_t lread = ioread32((void *)DMA_RDLAR_OFFSET_Q(i));\
	(data) |= (hread << 32) | lread;\
} while (0)

#define DMA_RDLAR_RDESLA_WR(i, data) do {\
	DMA_RDLAR_WR(i, data);\
} while (0)

#define DMA_RDLAR_RDESLA_RD(i, data) do {\
	DMA_RDLAR_RD(i, data);\
} while (0)

#define DMA_TDLAR_HR_OFFSET (BASE_ADDRESS + 0x1110)

#define DMA_TDLAR_OFFSET (BASE_ADDRESS + 0x1114)

#define DMA_TDLAR_OFFSET_Q(i) ((volatile ULONG *)(DMA_TDLAR_OFFSET + ((i-0)*128)))

#define DMA_TDLAR_HR_OFFSET_Q(i) ((volatile ULONG *)(DMA_TDLAR_HR_OFFSET + ((i-0)*128)))

#define DMA_TDLAR_WR(i, data) do {\
	iowrite32((((data) >> 32) & 0xFFFF), (void *)DMA_TDLAR_HR_OFFSET_Q(i));\
	iowrite32(data, (void *)DMA_TDLAR_OFFSET_Q(i));\
} while (0)

#define DMA_TDLAR_RD(i, data) do {\
	(data) = (ioread32((void *)DMA_TDLAR_HR_OFFSET_Q(i)) << 32);\
	(data) |= ioread32((void *)DMA_TDLAR_OFFSET_Q(i));\
} while (0)

#define DMA_TDLAR_TDESLA_WR(i, data) do {\
	DMA_TDLAR_WR(i, data);\
} while (0)

#define DMA_TDLAR_TDESLA_RD(i, data) do {\
	DMA_TDLAR_RD(i, data);\
} while (0)

#ifdef EQOS_VER_4_0

#define DMA_IER_OFFSET (BASE_ADDRESS + 0x1134)

#define DMA_IER_OFFSET_Q(i) ((volatile ULONG *)(DMA_IER_OFFSET + ((i-0)*128)))

#define DMA_IER_WR(i, data) do {\
	iowrite32(data, (void *)DMA_IER_OFFSET_Q(i));\
} while (0)

#define DMA_IER_RD(i, data) do {\
	(data) = ioread32((void *)DMA_IER_OFFSET_Q(i));\
} while (0)


#define  DMA_IER_MASK_17 (ULONG)(0x7fff)


#define DMA_IER_RES_WR_MASK_17 (ULONG)(0x1ffff)


#define  DMA_IER_MASK_14 (ULONG)(0x1)


#define DMA_IER_RES_WR_MASK_14 (ULONG)(0xffffbfff)


#define  DMA_IER_MASK_3 (ULONG)(0x7)


#define DMA_IER_RES_WR_MASK_3 (ULONG)(0xffffffc7)


#define DMA_IER_NIE_MASK (ULONG)(0x1)


#define DMA_IER_NIE_WR_MASK (ULONG)(0xfffeffff)

#define DMA_IER_NIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_NIE_WR_MASK)\
	|((data & DMA_IER_NIE_MASK)<<16));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_NIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 16) & DMA_IER_NIE_MASK);\
} while (0)


#define DMA_IER_AIE_MASK (ULONG)(0x1)


#define DMA_IER_AIE_WR_MASK (ULONG)(0xffff7fff)

#define DMA_IER_AIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_AIE_WR_MASK)\
	|((data & DMA_IER_AIE_MASK)<<15));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_AIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 15) & DMA_IER_AIE_MASK);\
} while (0)


#define DMA_IER_CDEE_MASK (ULONG)(0x1)


#define DMA_IER_CDEE_WR_MASK (ULONG)(0xffffdfff)

#define DMA_IER_CDEE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_CDEE_WR_MASK)\
	|((data & DMA_IER_CDEE_MASK)<<13));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_CDEE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 13) & DMA_IER_CDEE_MASK);\
} while (0)


#define DMA_IER_FBEE_MASK (ULONG)(0x1)


#define DMA_IER_FBEE_WR_MASK (ULONG)(0xffffefff)

#define DMA_IER_FBEE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_FBEE_WR_MASK)\
	|((data & DMA_IER_FBEE_MASK)<<12));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_FBEE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 12) & DMA_IER_FBEE_MASK);\
} while (0)


#define DMA_IER_ERIE_MASK (ULONG)(0x1)


#define DMA_IER_ERIE_WR_MASK (ULONG)(0xfffff7ff)

#define DMA_IER_ERIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_ERIE_WR_MASK)\
	|((data & DMA_IER_ERIE_MASK)<<11));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_ERIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 11) & DMA_IER_ERIE_MASK);\
} while (0)


#define DMA_IER_ETIE_MASK (ULONG)(0x1)


#define DMA_IER_ETIE_WR_MASK (ULONG)(0xfffffbff)

#define DMA_IER_ETIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_ETIE_WR_MASK)\
	|((data & DMA_IER_ETIE_MASK)<<10));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_ETIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 10) & DMA_IER_ETIE_MASK);\
} while (0)


#define DMA_IER_RWTE_MASK (ULONG)(0x1)


#define DMA_IER_RWTE_WR_MASK (ULONG)(0xfffffdff)

#define DMA_IER_RWTE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RWTE_WR_MASK)\
	|((data & DMA_IER_RWTE_MASK)<<9));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RWTE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 9) & DMA_IER_RWTE_MASK);\
} while (0)


#define DMA_IER_RSE_MASK (ULONG)(0x1)


#define DMA_IER_RSE_WR_MASK (ULONG)(0xfffffeff)

#define DMA_IER_RSE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RSE_WR_MASK)\
	|((data & DMA_IER_RSE_MASK)<<8));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RSE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 8) & DMA_IER_RSE_MASK);\
} while (0)


#define DMA_IER_RBUE_MASK (ULONG)(0x1)


#define DMA_IER_RBUE_WR_MASK (ULONG)(0xffffff7f)

#define DMA_IER_RBUE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RBUE_WR_MASK)\
	|((data & DMA_IER_RBUE_MASK)<<7));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RBUE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 7) & DMA_IER_RBUE_MASK);\
} while (0)


#define DMA_IER_RIE_MASK (ULONG)(0x1)


#define DMA_IER_RIE_WR_MASK (ULONG)(0xffffffbf)

#define DMA_IER_RIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RIE_WR_MASK)\
	|((data & DMA_IER_RIE_MASK)<<6));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 6) & DMA_IER_RIE_MASK);\
} while (0)


#define DMA_IER_TBUE_MASK (ULONG)(0x1)


#define DMA_IER_TBUE_WR_MASK (ULONG)(0xfffffffb)

#define DMA_IER_TBUE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_TBUE_WR_MASK)\
	|((data & DMA_IER_TBUE_MASK)<<2));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_TBUE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 2) & DMA_IER_TBUE_MASK);\
} while (0)


#define DMA_IER_TXSE_MASK (ULONG)(0x1)


#define DMA_IER_TXSE_WR_MASK (ULONG)(0xfffffffd)

#define DMA_IER_TXSE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_TXSE_WR_MASK)\
	|((data & DMA_IER_TXSE_MASK)<<1));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_TXSE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 1) & DMA_IER_TXSE_MASK);\
} while (0)


#define DMA_IER_TIE_MASK (ULONG)(0x1)


#define DMA_IER_TIE_WR_MASK (ULONG)(0xfffffffe)

#define DMA_IER_TIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_17))\
	|(((0) & (DMA_IER_MASK_17))<<17);\
	v = (v & (DMA_IER_RES_WR_MASK_14))\
	|(((0) & (DMA_IER_MASK_14))<<14);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_TIE_WR_MASK)\
	|((data & DMA_IER_TIE_MASK)<<0));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_TIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 0) & DMA_IER_TIE_MASK);\
} while (0)

#else
	/*****************************************/
#define DMA_IER_OFFSET (BASE_ADDRESS + 0x1134)

#define DMA_IER_OFFSET_Q(i) ((volatile ULONG *)(DMA_IER_OFFSET + ((i-0)*128)))

#define DMA_IER_WR(i, data) do {\
	iowrite32(data, (void *)DMA_IER_OFFSET_Q(i));\
} while (0)

#define DMA_IER_RD(i, data) do {\
	(data) = ioread32((void *)DMA_IER_OFFSET_Q(i));\
} while (0)

#define DMA_IER_MASK_16 (ULONG)(0xffff)
#define DMA_IER_RES_WR_MASK_16 (ULONG)(0xffff)

#define  DMA_IER_MASK_3 (ULONG)(0x7)
#define DMA_IER_RES_WR_MASK_3 (ULONG)(0xffffffc7)

#define DMA_IER_NIE_MASK (ULONG)(0x1)
#define DMA_IER_NIE_WR_MASK (ULONG)(0xffff7fff)

#define DMA_IER_NIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_NIE_WR_MASK)\
	|((data & DMA_IER_NIE_MASK)<<15));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_NIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 15) & DMA_IER_NIE_MASK);\
} while (0)

#define DMA_IER_AIE_MASK (ULONG)(0x1)

#define DMA_IER_AIE_WR_MASK (ULONG)(0xffffbfff)

#define DMA_IER_AIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_AIE_WR_MASK)\
	|((data & DMA_IER_AIE_MASK)<<14));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_AIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 14) & DMA_IER_AIE_MASK);\
} while (0)

#define DMA_IER_CDEE_MASK (ULONG)(0x1)

#define DMA_IER_CDEE_WR_MASK (ULONG)(0xffffdfff)

#define DMA_IER_CDEE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_CDEE_WR_MASK)\
	|((data & DMA_IER_CDEE_MASK)<<13));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_CDEE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 13) & DMA_IER_CDEE_MASK);\
} while (0)

#define DMA_IER_FBEE_MASK (ULONG)(0x1)

#define DMA_IER_FBEE_WR_MASK (ULONG)(0xffffefff)

#define DMA_IER_FBEE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_FBEE_WR_MASK)\
	|((data & DMA_IER_FBEE_MASK)<<12));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_FBEE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 12) & DMA_IER_FBEE_MASK);\
} while (0)

#define DMA_IER_ERIE_MASK (ULONG)(0x1)

#define DMA_IER_ERIE_WR_MASK (ULONG)(0xfffff7ff)

#define DMA_IER_ERIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_ERIE_WR_MASK)\
	|((data & DMA_IER_ERIE_MASK)<<11));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_ERIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 11) & DMA_IER_ERIE_MASK);\
} while (0)

#define DMA_IER_ETIE_MASK (ULONG)(0x1)

#define DMA_IER_ETIE_WR_MASK (ULONG)(0xfffffbff)

#define DMA_IER_ETIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_ETIE_WR_MASK)\
	|((data & DMA_IER_ETIE_MASK)<<10));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_ETIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 10) & DMA_IER_ETIE_MASK);\
} while (0)

#define DMA_IER_RWTE_MASK (ULONG)(0x1)

#define DMA_IER_RWTE_WR_MASK (ULONG)(0xfffffdff)

#define DMA_IER_RWTE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RWTE_WR_MASK)\
	|((data & DMA_IER_RWTE_MASK)<<9));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RWTE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 9) & DMA_IER_RWTE_MASK);\
} while (0)

#define DMA_IER_RSE_MASK (ULONG)(0x1)

#define DMA_IER_RSE_WR_MASK (ULONG)(0xfffffeff)

#define DMA_IER_RSE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RSE_WR_MASK)\
	|((data & DMA_IER_RSE_MASK)<<8));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RSE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 8) & DMA_IER_RSE_MASK);\
} while (0)

#define DMA_IER_RBUE_MASK (ULONG)(0x1)

#define DMA_IER_RBUE_WR_MASK (ULONG)(0xffffff7f)

#define DMA_IER_RBUE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RBUE_WR_MASK)\
	|((data & DMA_IER_RBUE_MASK)<<7));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RBUE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 7) & DMA_IER_RBUE_MASK);\
} while (0)

#define DMA_IER_RIE_MASK (ULONG)(0x1)

#define DMA_IER_RIE_WR_MASK (ULONG)(0xffffffbf)

#define DMA_IER_RIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_RIE_WR_MASK)\
	|((data & DMA_IER_RIE_MASK)<<6));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_RIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 6) & DMA_IER_RIE_MASK);\
} while (0)

#define DMA_IER_TBUE_MASK (ULONG)(0x1)

#define DMA_IER_TBUE_WR_MASK (ULONG)(0xfffffffb)

#define DMA_IER_TBUE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_TBUE_WR_MASK)\
	|((data & DMA_IER_TBUE_MASK)<<2));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_TBUE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 2) & DMA_IER_TBUE_MASK);\
} while (0)

#define DMA_IER_TXSE_MASK (ULONG)(0x1)

#define DMA_IER_TXSE_WR_MASK (ULONG)(0xfffffffd)

#define DMA_IER_TXSE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_TXSE_WR_MASK)\
	|((data & DMA_IER_TXSE_MASK)<<1));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_TXSE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 1) & DMA_IER_TXSE_MASK);\
} while (0)

#define DMA_IER_TIE_MASK (ULONG)(0x1)

#define DMA_IER_TIE_WR_MASK (ULONG)(0xfffffffe)

#define DMA_IER_TIE_WR(i, data) do {\
	ULONG v;\
	DMA_IER_RD(i, v);\
	v = (v & (DMA_IER_RES_WR_MASK_16))\
	|(((0) & (DMA_IER_MASK_16))<<16);\
	v = (v & (DMA_IER_RES_WR_MASK_3))\
	|(((0) & (DMA_IER_MASK_3))<<3);\
	v = ((v & DMA_IER_TIE_WR_MASK)\
	|((data & DMA_IER_TIE_MASK)<<0));\
	DMA_IER_WR(i, v);\
} while (0)

#define DMA_IER_TIE_RD(i, data) do {\
	DMA_IER_RD(i, data);\
	data = ((data >> 0) & DMA_IER_TIE_MASK);\
} while (0)

#endif				/* !EQOS_VER_4_0 */

#define DMA_SR_OFFSET (BASE_ADDRESS + 0x1160)

#define DMA_SR_OFFSET_Q(i) ((volatile ULONG *)(DMA_SR_OFFSET + ((i-0)*128)))

#define DMA_SR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_SR_OFFSET_Q(i));\
} while (0)

#define DMA_SR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_SR_OFFSET_Q(i));\
} while (0)


#define  DMA_SR_MASK_19 (ULONG)(0x1fff)


#define DMA_SR_RES_WR_MASK_19 (ULONG)(0x7ffff)


#define  DMA_SR_MASK_3 (ULONG)(0x7)


#define DMA_SR_RES_WR_MASK_3 (ULONG)(0xffffffc7)


#define DMA_SR_EB_MASK (ULONG)(0x7)

#define DMA_SR_EB_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 16) & DMA_SR_EB_MASK);\
} while (0)


#define DMA_SR_NIS_MASK (ULONG)(0x1)


#define DMA_SR_NIS_WR_MASK (ULONG)(0xffff7fff)

#define DMA_SR_NIS_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_NIS_WR_MASK)\
	|((data & DMA_SR_NIS_MASK)<<15));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_NIS_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 15) & DMA_SR_NIS_MASK);\
} while (0)


#define DMA_SR_AIS_MASK (ULONG)(0x1)


#define DMA_SR_AIS_WR_MASK (ULONG)(0xffffbfff)

#define DMA_SR_AIS_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_AIS_WR_MASK)\
	|((data & DMA_SR_AIS_MASK)<<14));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_AIS_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 14) & DMA_SR_AIS_MASK);\
} while (0)


#define DMA_SR_CDE_MASK (ULONG)(0x1)


#define DMA_SR_CDE_WR_MASK (ULONG)(0xffffdfff)

#define DMA_SR_CDE_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_CDE_WR_MASK)\
	|((data & DMA_SR_CDE_MASK)<<13));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_CDE_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 13) & DMA_SR_CDE_MASK);\
} while (0)


#define DMA_SR_FBE_MASK (ULONG)(0x1)


#define DMA_SR_FBE_WR_MASK (ULONG)(0xffffefff)

#define DMA_SR_FBE_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_FBE_WR_MASK)\
	|((data & DMA_SR_FBE_MASK)<<12));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_FBE_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 12) & DMA_SR_FBE_MASK);\
} while (0)


#define DMA_SR_ERI_MASK (ULONG)(0x1)


#define DMA_SR_ERI_WR_MASK (ULONG)(0xfffff7ff)

#define DMA_SR_ERI_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_ERI_WR_MASK)\
	|((data & DMA_SR_ERI_MASK)<<11));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_ERI_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 11) & DMA_SR_ERI_MASK);\
} while (0)


#define DMA_SR_ETI_MASK (ULONG)(0x1)


#define DMA_SR_ETI_WR_MASK (ULONG)(0xfffffbff)

#define DMA_SR_ETI_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_ETI_WR_MASK)\
	|((data & DMA_SR_ETI_MASK)<<10));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_ETI_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 10) & DMA_SR_ETI_MASK);\
} while (0)


#define DMA_SR_RWT_MASK (ULONG)(0x1)


#define DMA_SR_RWT_WR_MASK (ULONG)(0xfffffdff)

#define DMA_SR_RWT_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_RWT_WR_MASK)\
	|((data & DMA_SR_RWT_MASK)<<9));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_RWT_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 9) & DMA_SR_RWT_MASK);\
} while (0)


#define DMA_SR_RPS_MASK (ULONG)(0x1)


#define DMA_SR_RPS_WR_MASK (ULONG)(0xfffffeff)

#define DMA_SR_RPS_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_RPS_WR_MASK)\
	|((data & DMA_SR_RPS_MASK)<<8));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_RPS_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 8) & DMA_SR_RPS_MASK);\
} while (0)


#define DMA_SR_RBU_MASK (ULONG)(0x1)


#define DMA_SR_RBU_WR_MASK (ULONG)(0xffffff7f)

#define DMA_SR_RBU_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_RBU_WR_MASK)\
	|((data & DMA_SR_RBU_MASK)<<7));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_RBU_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 7) & DMA_SR_RBU_MASK);\
} while (0)


#define DMA_SR_RI_MASK (ULONG)(0x1)


#define DMA_SR_RI_WR_MASK (ULONG)(0xffffffbf)

#define DMA_SR_RI_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_RI_WR_MASK)\
	|((data & DMA_SR_RI_MASK)<<6));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_RI_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 6) & DMA_SR_RI_MASK);\
} while (0)


#define DMA_SR_TBU_MASK (ULONG)(0x1)


#define DMA_SR_TBU_WR_MASK (ULONG)(0xfffffffb)

#define DMA_SR_TBU_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_TBU_WR_MASK)\
	|((data & DMA_SR_TBU_MASK)<<2));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_TBU_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 2) & DMA_SR_TBU_MASK);\
} while (0)


#define DMA_SR_TPS_MASK (ULONG)(0x1)


#define DMA_SR_TPS_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SR_TPS_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_TPS_WR_MASK)\
	|((data & DMA_SR_TPS_MASK)<<1));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_TPS_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 1) & DMA_SR_TPS_MASK);\
} while (0)


#define DMA_SR_TI_MASK (ULONG)(0x1)


#define DMA_SR_TI_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SR_TI_WR(i, data) do {\
	ULONG v;\
	DMA_SR_RD(i, v);\
	v = (v & (DMA_SR_RES_WR_MASK_19))\
	|(((0) & (DMA_SR_MASK_19))<<19);\
	v = (v & (DMA_SR_RES_WR_MASK_3))\
	|(((0) & (DMA_SR_MASK_3))<<3);\
	v = ((v & DMA_SR_TI_WR_MASK)\
	|((data & DMA_SR_TI_MASK)<<0));\
	DMA_SR_WR(i, v);\
} while (0)

#define DMA_SR_TI_RD(i, data) do {\
	DMA_SR_RD(i, data);\
	data = ((data >> 0) & DMA_SR_TI_MASK);\
} while (0)

#define DMA_CHRBARH_OFFSET (BASE_ADDRESS + 0x1158)

#define DMA_CHRBAR_OFFSET (BASE_ADDRESS + 0x115c)

#define DMA_CHRBARH_OFFSET_Q(i) ((volatile ULONG *)(DMA_CHRBARH_OFFSET + ((i-0)*128)))

#define DMA_CHRBAR_OFFSET_Q(i) ((volatile ULONG *)(DMA_CHRBAR_OFFSET + ((i-0)*128)))

#define DMA_CHRBAR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_CHRBARH_OFFSET_Q(i)) << 32;\
	(data) |= ioread32((void *)DMA_CHRBAR_OFFSET_Q(i));\
} while (0)

#define DMA_CHRBAR_CURRBUFAPTR_RD(i, data) do {\
	DMA_CHRBAR_RD(i, data);\
} while (0)

#define DMA_CHTBARH_OFFSET (BASE_ADDRESS + 0x1150)

#define DMA_CHTBAR_OFFSET (BASE_ADDRESS + 0x1154)

#define DMA_CHTBARH_OFFSET_Q(i) ((volatile ULONG *)(DMA_CHTBARH_OFFSET + ((i-0)*128)))

#define DMA_CHTBAR_OFFSET_Q(i) ((volatile ULONG *)(DMA_CHTBAR_OFFSET + ((i-0)*128)))

#define DMA_CHTBAR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_CHTBARH_OFFSET_Q(i)) << 32;\
	(data) |= ioread32((void *)DMA_CHTBAR_OFFSET_Q(i));\
} while (0)

#define DMA_CHTBAR_CURTBUFAPTR_RD(i, data) do {\
	DMA_CHTBAR_RD(i, data);\
} while (0)

#define DMA_CHRDR_OFFSET (BASE_ADDRESS + 0x114c)

#define DMA_CHRDR_OFFSET_Q(i) ((volatile ULONG *)(DMA_CHRDR_OFFSET + ((i-0)*128)))

#define DMA_CHRDR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_CHRDR_OFFSET_Q(i));\
} while (0)

#define DMA_CHRDR_CURRDESAPTR_RD(i, data) do {\
	DMA_CHRDR_RD(i, data);\
} while (0)

#define DMA_CHTDR_OFFSET (BASE_ADDRESS + 0x1144)

#define DMA_CHTDR_OFFSET_Q(i) ((volatile ULONG *)(DMA_CHTDR_OFFSET + ((i-0)*128)))

#define DMA_CHTDR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_CHTDR_OFFSET_Q(i));\
} while (0)

#define DMA_CHTDR_CURTDESAPTR_RD(i, data) do {\
	DMA_CHTDR_RD(i, data);\
} while (0)

#define DMA_SFCSR_OFFSET (BASE_ADDRESS + 0x113c)

#define DMA_SFCSR_OFFSET_Q(i) ((volatile ULONG *)(DMA_SFCSR_OFFSET + ((i-0)*128)))

#define DMA_SFCSR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_SFCSR_OFFSET_Q(i));\
} while (0)

#define DMA_SFCSR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_SFCSR_OFFSET_Q(i));\
} while (0)


#define  DMA_SFCSR_MASK_20 (ULONG)(0xfff)


#define DMA_SFCSR_RES_WR_MASK_20 (ULONG)(0xfffff)


#define  DMA_SFCSR_MASK_2 (ULONG)(0x3fff)


#define DMA_SFCSR_RES_WR_MASK_2 (ULONG)(0xffff0003)


#define DMA_SFCSR_RSN_MASK (ULONG)(0xf)

#define DMA_SFCSR_RSN_RD(i, data) do {\
	DMA_SFCSR_RD(i, data);\
	data = ((data >> 16) & DMA_SFCSR_RSN_MASK);\
} while (0)


#define DMA_SFCSR_ASC_MASK (ULONG)(0x1)


#define DMA_SFCSR_ASC_WR_MASK (ULONG)(0xfffffffd)

#define DMA_SFCSR_ASC_WR(i, data) do {\
	ULONG v;\
	DMA_SFCSR_RD(i, v);\
	v = (v & (DMA_SFCSR_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR_MASK_20))<<20);\
	v = (v & (DMA_SFCSR_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR_MASK_2))<<2);\
	v = ((v & DMA_SFCSR_ASC_WR_MASK)\
	|((data & DMA_SFCSR_ASC_MASK)<<1));\
	DMA_SFCSR_WR(i, v);\
} while (0)

#define DMA_SFCSR_ASC_RD(i, data) do {\
	DMA_SFCSR_RD(i, data);\
	data = ((data >> 1) & DMA_SFCSR_ASC_MASK);\
} while (0)


#define DMA_SFCSR_ESC_MASK (ULONG)(0x1)


#define DMA_SFCSR_ESC_WR_MASK (ULONG)(0xfffffffe)

#define DMA_SFCSR_ESC_WR(i, data) do {\
	ULONG v;\
	DMA_SFCSR_RD(i, v);\
	v = (v & (DMA_SFCSR_RES_WR_MASK_20))\
	|(((0) & (DMA_SFCSR_MASK_20))<<20);\
	v = (v & (DMA_SFCSR_RES_WR_MASK_2))\
	|(((0) & (DMA_SFCSR_MASK_2))<<2);\
	v = ((v & DMA_SFCSR_ESC_WR_MASK)\
	|((data & DMA_SFCSR_ESC_MASK)<<0));\
	DMA_SFCSR_WR(i, v);\
} while (0)

#define DMA_SFCSR_SIV_WR_MASK (ULONG)(0xffff000f)
#define DMA_SFCSR_RES_WR_MASK_2_V5 (ULONG)(0xfffffff3)
#define DMA_SFCSR_SIV_MASK (ULONG)(0xfff)

#define DMA_SFCSR_SIV_WR(i, data) do {\
	ULONG v;\
	DMA_SFCSR_RD(i, v);\
	v = (v & (DMA_SFCSR_RES_WR_MASK_20))\
	| (((0) & (DMA_SFCSR_MASK_20)) << 20);\
	v = (v & (DMA_SFCSR_RES_WR_MASK_2_V5))\
	| (((0) & (DMA_SFCSR_MASK_2)) << 2);\
	v = ((v & DMA_SFCSR_SIV_WR_MASK)\
	| (((data) & DMA_SFCSR_SIV_MASK) << 4));\
	DMA_SFCSR_WR(i, v);\
} while (0)

#define DMA_SFCSR_ESC_RD(i, data) do {\
	DMA_SFCSR_RD(i, data);\
	data = ((data >> 0) & DMA_SFCSR_ESC_MASK);\
} while (0)

#define MAC_QTFCR_OFFSET (BASE_ADDRESS + 0x70)

#define MAC_QTFCR_OFFSET_Q(i) ((volatile ULONG *)(MAC_QTFCR_OFFSET + ((i-0)*4)))

#define MAC_QTFCR_WR(i, data) do {\
	iowrite32(data, (void *)MAC_QTFCR_OFFSET_Q(i));\
} while (0)

#define MAC_QTFCR_RD(i, data) do {\
	(data) = ioread32((void *)MAC_QTFCR_OFFSET_Q(i));\
} while (0)


#define  MAC_QTFCR_MASK_8 (ULONG)(0xff)


#define MAC_QTFCR_RES_WR_MASK_8 (ULONG)(0xffff00ff)


#define  MAC_QTFCR_MASK_2 (ULONG)(0x3)


#define MAC_QTFCR_RES_WR_MASK_2 (ULONG)(0xfffffff3)


#define MAC_QTFCR_PT_MASK (ULONG)(0xffff)


#define MAC_QTFCR_PT_WR_MASK (ULONG)(0xffff)

#define MAC_QTFCR_PT_WR(i, data) do {\
	ULONG v;\
	MAC_QTFCR_RD(i, v);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR_MASK_8))<<8);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR_MASK_2))<<2);\
	v = ((v & MAC_QTFCR_PT_WR_MASK)\
	|((data & MAC_QTFCR_PT_MASK)<<16));\
	MAC_QTFCR_WR(i, v);\
} while (0)

#define MAC_QTFCR_PT_RD(i, data) do {\
	MAC_QTFCR_RD(i, data);\
	data = ((data >> 16) & MAC_QTFCR_PT_MASK);\
} while (0)


#define MAC_QTFCR_DZPQ_MASK (ULONG)(0x1)


#define MAC_QTFCR_DZPQ_WR_MASK (ULONG)(0xffffff7f)

#define MAC_QTFCR_DZPQ_WR(i, data) do {\
	ULONG v;\
	MAC_QTFCR_RD(i, v);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR_MASK_8))<<8);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR_MASK_2))<<2);\
	v = ((v & MAC_QTFCR_DZPQ_WR_MASK)\
	|((data & MAC_QTFCR_DZPQ_MASK)<<7));\
	MAC_QTFCR_WR(i, v);\
} while (0)

#define MAC_QTFCR_DZPQ_RD(i, data) do {\
	MAC_QTFCR_RD(i, data);\
	data = ((data >> 7) & MAC_QTFCR_DZPQ_MASK);\
} while (0)


#define MAC_QTFCR_PLT_MASK (ULONG)(0x7)


#define MAC_QTFCR_PLT_WR_MASK (ULONG)(0xffffff8f)

#define MAC_QTFCR_PLT_WR(i, data) do {\
	ULONG v;\
	MAC_QTFCR_RD(i, v);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR_MASK_8))<<8);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR_MASK_2))<<2);\
	v = ((v & MAC_QTFCR_PLT_WR_MASK)\
	|((data & MAC_QTFCR_PLT_MASK)<<4));\
	MAC_QTFCR_WR(i, v);\
} while (0)

#define MAC_QTFCR_PLT_RD(i, data) do {\
	MAC_QTFCR_RD(i, data);\
	data = ((data >> 4) & MAC_QTFCR_PLT_MASK);\
} while (0)


#define MAC_QTFCR_TFE_MASK (ULONG)(0x1)


#define MAC_QTFCR_TFE_WR_MASK (ULONG)(0xfffffffd)

#define MAC_QTFCR_TFE_WR(i, data) do {\
	ULONG v;\
	MAC_QTFCR_RD(i, v);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR_MASK_8))<<8);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR_MASK_2))<<2);\
	v = ((v & MAC_QTFCR_TFE_WR_MASK)\
	|((data & MAC_QTFCR_TFE_MASK)<<1));\
	MAC_QTFCR_WR(i, v);\
} while (0)

#define MAC_QTFCR_TFE_RD(i, data) do {\
	MAC_QTFCR_RD(i, data);\
	data = ((data >> 1) & MAC_QTFCR_TFE_MASK);\
} while (0)


#define MAC_QTFCR_FCB_BPA_MASK (ULONG)(0x1)


#define MAC_QTFCR_FCB_BPA_WR_MASK (ULONG)(0xfffffffe)

#define MAC_QTFCR_FCB_BPA_WR(i, data) do {\
	ULONG v;\
	MAC_QTFCR_RD(i, v);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_8))\
	|(((0) & (MAC_QTFCR_MASK_8))<<8);\
	v = (v & (MAC_QTFCR_RES_WR_MASK_2))\
	|(((0) & (MAC_QTFCR_MASK_2))<<2);\
	v = ((v & MAC_QTFCR_FCB_BPA_WR_MASK)\
	|((data & MAC_QTFCR_FCB_BPA_MASK)<<0));\
	MAC_QTFCR_WR(i, v);\
} while (0)

#define MAC_QTFCR_FCB_BPA_RD(i, data) do {\
	MAC_QTFCR_RD(i, data);\
	data = ((data >> 0) & MAC_QTFCR_FCB_BPA_MASK);\
} while (0)

#define DMA_AXI4CR_OFFSET (BASE_ADDRESS + 0x1164)

#define DMA_AXI4CR_OFFSET_Q(i) ((volatile ULONG *)(DMA_AXI4CR_OFFSET + ((i-0)*128)))

#define DMA_AXI4CR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_AXI4CR_OFFSET_Q(i));\
} while (0)

#define DMA_AXI4CR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_AXI4CR_OFFSET_Q(i));\
} while (0)


#define  DMA_AXI4CR_MASK_20 (ULONG)(0xfff)


#define DMA_AXI4CR_RES_WR_MASK_20 (ULONG)(0xfffff)


#define  DMA_AXI4CR_MASK_4 (ULONG)(0xfff)


#define DMA_AXI4CR_RES_WR_MASK_4 (ULONG)(0xffff000f)


#define DMA_AXI4CR_ARQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR_ARQOS_WR_MASK (ULONG)(0xfff0ffff)

#define DMA_AXI4CR_ARQOS_WR(i, data) do {\
	ULONG v;\
	DMA_AXI4CR_RD(i, v);\
	v = (v & (DMA_AXI4CR_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR_MASK_20))<<20);\
	v = (v & (DMA_AXI4CR_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR_MASK_4))<<4);\
	v = ((v & DMA_AXI4CR_ARQOS_WR_MASK)\
	|((data & DMA_AXI4CR_ARQOS_MASK)<<16));\
	DMA_AXI4CR_WR(i, v);\
} while (0)

#define DMA_AXI4CR_ARQOS_RD(i, data) do {\
	DMA_AXI4CR_RD(i, data);\
	data = ((data >> 16) & DMA_AXI4CR_ARQOS_MASK);\
} while (0)


#define DMA_AXI4CR_AWQOS_MASK (ULONG)(0xf)


#define DMA_AXI4CR_AWQOS_WR_MASK (ULONG)(0xfffffff0)

#define DMA_AXI4CR_AWQOS_WR(i, data) do {\
	ULONG v;\
	DMA_AXI4CR_RD(i, v);\
	v = (v & (DMA_AXI4CR_RES_WR_MASK_20))\
	|(((0) & (DMA_AXI4CR_MASK_20))<<20);\
	v = (v & (DMA_AXI4CR_RES_WR_MASK_4))\
	|(((0) & (DMA_AXI4CR_MASK_4))<<4);\
	v = ((v & DMA_AXI4CR_AWQOS_WR_MASK)\
	|((data & DMA_AXI4CR_AWQOS_MASK)<<0));\
	DMA_AXI4CR_WR(i, v);\
} while (0)

#define DMA_AXI4CR_AWQOS_RD(i, data) do {\
	DMA_AXI4CR_RD(i, data);\
	data = ((data >> 0) & DMA_AXI4CR_AWQOS_MASK);\
} while (0)

#define DMA_RCR_OFFSET (BASE_ADDRESS + 0x1108)

#define DMA_RCR_OFFSET_Q(i) ((volatile ULONG *)(DMA_RCR_OFFSET + ((i-0)*128)))

#define DMA_RCR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_RCR_OFFSET_Q(i));\
} while (0)

#define DMA_RCR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_RCR_OFFSET_Q(i));\
} while (0)


#define  DMA_RCR_MASK_28 (ULONG)(0xf)


#define DMA_RCR_RES_WR_MASK_28 (ULONG)(0xfffffff)


#define  DMA_RCR_MASK_22 (ULONG)(0x7)


#define DMA_RCR_RES_WR_MASK_22 (ULONG)(0xfe3fffff)


#define  DMA_RCR_MASK_15 (ULONG)(0x1)


#define DMA_RCR_RES_WR_MASK_15 (ULONG)(0xffff7fff)


#define DMA_RCR_MAMS_MASK (ULONG)(0x1)


#define DMA_RCR_MAMS_WR_MASK (ULONG)(0xf7ffffff)

#define DMA_RCR_MAMS_WR(i, data) do {\
	ULONG v;\
	DMA_RCR_RD(i, v);\
	v = (v & (DMA_RCR_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR_MASK_28))<<28);\
	v = (v & (DMA_RCR_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR_MASK_22))<<22);\
	v = (v & (DMA_RCR_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR_MASK_15))<<15);\
	v = ((v & DMA_RCR_MAMS_WR_MASK)\
	|((data & DMA_RCR_MAMS_MASK)<<27));\
	DMA_RCR_WR(i, v);\
} while (0)

#define DMA_RCR_MAMS_RD(i, data) do {\
	DMA_RCR_RD(i, data);\
	data = ((data >> 27) & DMA_RCR_MAMS_MASK);\
} while (0)


#define DMA_RCR_DFF_MASK (ULONG)(0x1)


#define DMA_RCR_DFF_WR_MASK (ULONG)(0xfbffffff)

#define DMA_RCR_DFF_WR(i, data) do {\
	ULONG v;\
	DMA_RCR_RD(i, v);\
	v = (v & (DMA_RCR_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR_MASK_28))<<28);\
	v = (v & (DMA_RCR_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR_MASK_22))<<22);\
	v = (v & (DMA_RCR_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR_MASK_15))<<15);\
	v = ((v & DMA_RCR_DFF_WR_MASK)\
	|((data & DMA_RCR_DFF_MASK)<<26));\
	DMA_RCR_WR(i, v);\
} while (0)

#define DMA_RCR_DFF_RD(i, data) do {\
	DMA_RCR_RD(i, data);\
	data = ((data >> 26) & DMA_RCR_DFF_MASK);\
} while (0)


#define DMA_RCR_RES_MASK (ULONG)(0x1)


#define DMA_RCR_RES_WR_MASK (ULONG)(0xfdffffff)

#define DMA_RCR_RES_WR(i, data) do {\
	ULONG v;\
	DMA_RCR_RD(i, v);\
	v = (v & (DMA_RCR_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR_MASK_28))<<28);\
	v = (v & (DMA_RCR_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR_MASK_22))<<22);\
	v = (v & (DMA_RCR_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR_MASK_15))<<15);\
	v = ((v & DMA_RCR_RES_WR_MASK)\
	|((data & DMA_RCR_RES_MASK)<<25));\
	DMA_RCR_WR(i, v);\
} while (0)

#define DMA_RCR_RES_RD(i, data) do {\
	DMA_RCR_RD(i, data);\
	data = ((data >> 25) & DMA_RCR_RES_MASK);\
} while (0)


#define DMA_RCR_PBL_MASK (ULONG)(0x3f)


#define DMA_RCR_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_RCR_PBL_WR(i, data) do {\
	ULONG v;\
	DMA_RCR_RD(i, v);\
	v = (v & (DMA_RCR_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR_MASK_28))<<28);\
	v = (v & (DMA_RCR_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR_MASK_22))<<22);\
	v = (v & (DMA_RCR_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR_MASK_15))<<15);\
	v = ((v & DMA_RCR_PBL_WR_MASK)\
	|((data & DMA_RCR_PBL_MASK)<<16));\
	DMA_RCR_WR(i, v);\
} while (0)

#define DMA_RCR_PBL_RD(i, data) do {\
	DMA_RCR_RD(i, data);\
	data = ((data >> 16) & DMA_RCR_PBL_MASK);\
} while (0)


#define DMA_RCR_RBSZ_MASK (ULONG)(0x3fff)


#define DMA_RCR_RBSZ_WR_MASK (ULONG)(0xffff8001)

#define DMA_RCR_RBSZ_WR(i, data) do {\
	ULONG v;\
	DMA_RCR_RD(i, v);\
	v = (v & (DMA_RCR_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR_MASK_28))<<28);\
	v = (v & (DMA_RCR_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR_MASK_22))<<22);\
	v = (v & (DMA_RCR_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR_MASK_15))<<15);\
	v = ((v & DMA_RCR_RBSZ_WR_MASK)\
	|((data & DMA_RCR_RBSZ_MASK)<<1));\
	DMA_RCR_WR(i, v);\
} while (0)

#define DMA_RCR_RBSZ_RD(i, data) do {\
	DMA_RCR_RD(i, data);\
	data = ((data >> 1) & DMA_RCR_RBSZ_MASK);\
} while (0)


#define DMA_RCR_ST_MASK (ULONG)(0x1)


#define DMA_RCR_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_RCR_ST_WR(i, data) do {\
	ULONG v;\
	DMA_RCR_RD(i, v);\
	v = (v & (DMA_RCR_RES_WR_MASK_28))\
	|(((0) & (DMA_RCR_MASK_28))<<28);\
	v = (v & (DMA_RCR_RES_WR_MASK_22))\
	|(((0) & (DMA_RCR_MASK_22))<<22);\
	v = (v & (DMA_RCR_RES_WR_MASK_15))\
	|(((0) & (DMA_RCR_MASK_15))<<15);\
	v = ((v & DMA_RCR_ST_WR_MASK)\
	|((data & DMA_RCR_ST_MASK)<<0));\
	DMA_RCR_WR(i, v);\
} while (0)

#define DMA_RCR_ST_RD(i, data) do {\
	DMA_RCR_RD(i, data);\
	data = ((data >> 0) & DMA_RCR_ST_MASK);\
} while (0)

#define DMA_TCR_OFFSET (BASE_ADDRESS + 0x1104)

#define DMA_TCR_OFFSET_Q(i) ((volatile ULONG *)(DMA_TCR_OFFSET + ((i-0)*128)))

#define DMA_TCR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_TCR_OFFSET_Q(i));\
} while (0)

#define DMA_TCR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_TCR_OFFSET_Q(i));\
} while (0)


#define  DMA_TCR_MASK_22 (ULONG)(0x3ff)


#define DMA_TCR_RES_WR_MASK_22 (ULONG)(0x3fffff)


#define  DMA_TCR_MASK_13 (ULONG)(0x7)


#define DMA_TCR_RES_WR_MASK_13 (ULONG)(0xffff1fff)


#define  DMA_TCR_MASK_5 (ULONG)(0x7f)


#define DMA_TCR_RES_WR_MASK_5 (ULONG)(0xfffff01f)


#define DMA_TCR_PBL_MASK (ULONG)(0x3f)


#define DMA_TCR_PBL_WR_MASK (ULONG)(0xffc0ffff)

#define DMA_TCR_PBL_WR(i, data) do {\
	ULONG v;\
	DMA_TCR_RD(i, v);\
	v = (v & (DMA_TCR_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR_MASK_22))<<22);\
	v = (v & (DMA_TCR_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR_MASK_13))<<13);\
	v = (v & (DMA_TCR_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR_MASK_5))<<5);\
	v = ((v & DMA_TCR_PBL_WR_MASK)\
	|((data & DMA_TCR_PBL_MASK)<<16));\
	DMA_TCR_WR(i, v);\
} while (0)

#define DMA_TCR_PBL_RD(i, data) do {\
	DMA_TCR_RD(i, data);\
	data = ((data >> 16) & DMA_TCR_PBL_MASK);\
} while (0)


#define DMA_TCR_TSE_MASK (ULONG)(0x1)


#define DMA_TCR_TSE_WR_MASK (ULONG)(0xffffefff)

#define DMA_TCR_TSE_WR(i, data) do {\
	ULONG v;\
	DMA_TCR_RD(i, v);\
	v = (v & (DMA_TCR_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR_MASK_22))<<22);\
	v = (v & (DMA_TCR_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR_MASK_13))<<13);\
	v = (v & (DMA_TCR_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR_MASK_5))<<5);\
	v = ((v & DMA_TCR_TSE_WR_MASK)\
	|((data & DMA_TCR_TSE_MASK)<<12));\
	DMA_TCR_WR(i, v);\
} while (0)

#define DMA_TCR_TSE_RD(i, data) do {\
	DMA_TCR_RD(i, data);\
	data = ((data >> 12) & DMA_TCR_TSE_MASK);\
} while (0)


#define DMA_TCR_OSP_MASK (ULONG)(0x1)


#define DMA_TCR_OSP_WR_MASK (ULONG)(0xffffffef)

#define DMA_TCR_OSP_WR(i, data) do {\
	ULONG v;\
	DMA_TCR_RD(i, v);\
	v = (v & (DMA_TCR_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR_MASK_22))<<22);\
	v = (v & (DMA_TCR_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR_MASK_13))<<13);\
	v = (v & (DMA_TCR_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR_MASK_5))<<5);\
	v = ((v & DMA_TCR_OSP_WR_MASK)\
	|((data & DMA_TCR_OSP_MASK)<<4));\
	DMA_TCR_WR(i, v);\
} while (0)

#define DMA_TCR_OSP_RD(i, data) do {\
	DMA_TCR_RD(i, data);\
	data = ((data >> 4) & DMA_TCR_OSP_MASK);\
} while (0)


#define DMA_TCR_TCW_MASK (ULONG)(0x7)


#define DMA_TCR_TCW_WR_MASK (ULONG)(0xfffffff1)

#define DMA_TCR_TCW_WR(i, data) do {\
	ULONG v;\
	DMA_TCR_RD(i, v);\
	v = (v & (DMA_TCR_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR_MASK_22))<<22);\
	v = (v & (DMA_TCR_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR_MASK_13))<<13);\
	v = (v & (DMA_TCR_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR_MASK_5))<<5);\
	v = ((v & DMA_TCR_TCW_WR_MASK)\
	|((data & DMA_TCR_TCW_MASK)<<1));\
	DMA_TCR_WR(i, v);\
} while (0)

#define DMA_TCR_TCW_RD(i, data) do {\
	DMA_TCR_RD(i, data);\
	data = ((data >> 1) & DMA_TCR_TCW_MASK);\
} while (0)


#define DMA_TCR_ST_MASK (ULONG)(0x1)


#define DMA_TCR_ST_WR_MASK (ULONG)(0xfffffffe)

#define DMA_TCR_ST_WR(i, data) do {\
	ULONG v;\
	DMA_TCR_RD(i, v);\
	v = (v & (DMA_TCR_RES_WR_MASK_22))\
	|(((0) & (DMA_TCR_MASK_22))<<22);\
	v = (v & (DMA_TCR_RES_WR_MASK_13))\
	|(((0) & (DMA_TCR_MASK_13))<<13);\
	v = (v & (DMA_TCR_RES_WR_MASK_5))\
	|(((0) & (DMA_TCR_MASK_5))<<5);\
	v = ((v & DMA_TCR_ST_WR_MASK)\
	|((data & DMA_TCR_ST_MASK)<<0));\
	DMA_TCR_WR(i, v);\
} while (0)

#define DMA_TCR_ST_RD(i, data) do {\
	DMA_TCR_RD(i, data);\
	data = ((data >> 0) & DMA_TCR_ST_MASK);\
} while (0)

#define DMA_CR_OFFSET (BASE_ADDRESS + 0x1100)

#define DMA_CR_OFFSET_Q(i) ((volatile ULONG *)(DMA_CR_OFFSET + ((i-0)*128)))

#define DMA_CR_WR(i, data) do {\
	iowrite32(data, (void *)DMA_CR_OFFSET_Q(i));\
} while (0)

#define DMA_CR_RD(i, data) do {\
	(data) = ioread32((void *)DMA_CR_OFFSET_Q(i));\
} while (0)


#define  DMA_CR_MASK_25 (ULONG)(0x7f)


#define DMA_CR_RES_WR_MASK_25 (ULONG)(0x1ffffff)


#define  DMA_CR_MASK_21 (ULONG)(0x3)


#define DMA_CR_RES_WR_MASK_21 (ULONG)(0xff9fffff)


#define DMA_CR_SPH_MASK (ULONG)(0x1)


#define DMA_CR_SPH_WR_MASK (ULONG)(0xfeffffff)

#define DMA_CR_SPH_WR(i, data) do {\
	ULONG v;\
	DMA_CR_RD(i, v);\
	v = (v & (DMA_CR_RES_WR_MASK_25))\
	|(((0) & (DMA_CR_MASK_25))<<25);\
	v = (v & (DMA_CR_RES_WR_MASK_21))\
	|(((0) & (DMA_CR_MASK_21))<<21);\
	v = ((v & DMA_CR_SPH_WR_MASK)\
	|((data & DMA_CR_SPH_MASK)<<24));\
	DMA_CR_WR(i, v);\
} while (0)

#define DMA_CR_SPH_RD(i, data) do {\
	DMA_CR_RD(i, data);\
	data = ((data >> 24) & DMA_CR_SPH_MASK);\
} while (0)


#define DMA_CR_CH_MASK (ULONG)(0x1)


#define DMA_CR_CH_WR_MASK (ULONG)(0xff7fffff)

#define DMA_CR_CH_WR(i, data) do {\
	ULONG v;\
	DMA_CR_RD(i, v);\
	v = (v & (DMA_CR_RES_WR_MASK_25))\
	|(((0) & (DMA_CR_MASK_25))<<25);\
	v = (v & (DMA_CR_RES_WR_MASK_21))\
	|(((0) & (DMA_CR_MASK_21))<<21);\
	v = ((v & DMA_CR_CH_WR_MASK)\
	|((data & DMA_CR_CH_MASK)<<23));\
	DMA_CR_WR(i, v);\
} while (0)

#define DMA_CR_CH_RD(i, data) do {\
	DMA_CR_RD(i, data);\
	data = ((data >> 23) & DMA_CR_CH_MASK);\
} while (0)


#define DMA_CR_DSL_MASK (ULONG)(0x7)


#define DMA_CR_DSL_WR_MASK (ULONG)(0xffe3ffff)

#define DMA_CR_DSL_WR(i, data) do {\
	ULONG v;\
	DMA_CR_RD(i, v);\
	v = (v & (DMA_CR_RES_WR_MASK_25))\
	|(((0) & (DMA_CR_MASK_25))<<25);\
	v = (v & (DMA_CR_RES_WR_MASK_21))\
	|(((0) & (DMA_CR_MASK_21))<<21);\
	v = ((v & DMA_CR_DSL_WR_MASK)\
	|((data & DMA_CR_DSL_MASK)<<18));\
	DMA_CR_WR(i, v);\
} while (0)

#define DMA_CR_DSL_RD(i, data) do {\
	DMA_CR_RD(i, data);\
	data = ((data >> 18) & DMA_CR_DSL_MASK);\
} while (0)


#define DMA_CR_DPE_MASK (ULONG)(0x1)


#define DMA_CR_DPE_WR_MASK (ULONG)(0xfffdffff)

#define DMA_CR_DPE_WR(i, data) do {\
	ULONG v;\
	DMA_CR_RD(i, v);\
	v = (v & (DMA_CR_RES_WR_MASK_25))\
	|(((0) & (DMA_CR_MASK_25))<<25);\
	v = (v & (DMA_CR_RES_WR_MASK_21))\
	|(((0) & (DMA_CR_MASK_21))<<21);\
	v = ((v & DMA_CR_DPE_WR_MASK)\
	|((data & DMA_CR_DPE_MASK)<<17));\
	DMA_CR_WR(i, v);\
} while (0)

#define DMA_CR_DPE_RD(i, data) do {\
	DMA_CR_RD(i, data);\
	data = ((data >> 17) & DMA_CR_DPE_MASK);\
} while (0)


#define DMA_CR_PBLX8_MASK (ULONG)(0x1)


#define DMA_CR_PBLX8_WR_MASK (ULONG)(0xfffeffff)

#define DMA_CR_PBLX8_WR(i, data) do {\
	ULONG v;\
	DMA_CR_RD(i, v);\
	v = (v & (DMA_CR_RES_WR_MASK_25))\
	|(((0) & (DMA_CR_MASK_25))<<25);\
	v = (v & (DMA_CR_RES_WR_MASK_21))\
	|(((0) & (DMA_CR_MASK_21))<<21);\
	v = ((v & DMA_CR_PBLX8_WR_MASK)\
	|((data & DMA_CR_PBLX8_MASK)<<16));\
	DMA_CR_WR(i, v);\
} while (0)

#define DMA_CR_PBLX8_RD(i, data) do {\
	DMA_CR_RD(i, data);\
	data = ((data >> 16) & DMA_CR_PBLX8_MASK);\
} while (0)


#define DMA_CR_MSS_MASK (ULONG)(0xffff)

#define DMA_CR_MSS_WR_MASK (ULONG)(0xffff0000)

#define DMA_CR_MSS_WR(i, data) do {\
	ULONG v;\
	DMA_CR_RD(i, v);\
	v = (v & (DMA_CR_RES_WR_MASK_25))\
	|(((0) & (DMA_CR_MASK_25))<<25);\
	v = (v & (DMA_CR_RES_WR_MASK_21))\
	|(((0) & (DMA_CR_MASK_21))<<21);\
	v = ((v & DMA_CR_MSS_WR_MASK)\
	|((data & DMA_CR_MSS_MASK)<<0));\
	DMA_CR_WR(i, v);\
} while (0)

#define DMA_CR_MSS_RD(i, data) do {\
	DMA_CR_RD(i, data);\
	data = ((data >> 0) & DMA_CR_MSS_MASK);\
} while (0)

#define MAC_ALPA_PSE_LPOS 7
#define MAC_ALPA_PSE_HPOS 8

#define MAC_ALPA_FD_LPOS 5
#define MAC_ALPA_FD_HPOS 5

#define MAC_AAD_PSE_LPOS 7
#define MAC_AAD_PSE_HPOS 8

#define MAC_AAD_FD_LPOS 5
#define MAC_AAD_FD_HPOS 5

#define MAC_TTN_TXTSSTSHI_LPOS 0
#define MAC_TTN_TXTSSTSHI_HPOS 31

#define MAC_TTSN_TXTSSTSMIS_LPOS 31
#define MAC_TTSN_TXTSSTSMIS_HPOS 31

#define MAC_TTSN_TXTSSTSLO_LPOS 0
#define MAC_TTSN_TXTSSTSLO_HPOS 30

#define MAC_STNSR_TSSS_LPOS 0
#define MAC_STNSR_TSSS_HPOS 30

#define MAC_TCR_TXTSSTSM_LPOS 24
#define MAC_TCR_TXTSSTSM_HPOS 24

#define MAC_TCR_TSCTRLSSR_LPOS 9
#define MAC_TCR_TSCTRLSSR_HPOS 9

#define MAC_TCR_TSADDREG_LPOS 5
#define MAC_TCR_TSADDREG_HPOS 5

#define MAC_TCR_TSUPDT_LPOS 3
#define MAC_TCR_TSUPDT_HPOS 3

#define MAC_TCR_TSINIT_LPOS 2
#define MAC_TCR_TSINIT_HPOS 2

#define MAC_TCR_TSCFUPDT_LPOS 1
#define MAC_TCR_TSCFUPDT_HPOS 1

#define MAC_GMIIDR_GD_LPOS 0
#define MAC_GMIIDR_GD_HPOS 15

#define MAC_GMIIAR_GB_LPOS 0
#define MAC_GMIIAR_GB_HPOS 0

#define MAC_HFR2_TXQCNT_LPOS 6
#define MAC_HFR2_TXQCNT_HPOS 9

#define MAC_HFR2_RXQCNT_LPOS 0
#define MAC_HFR2_RXQCNT_HPOS 3

#define DMA_SR_TI_LPOS 0
#define DMA_SR_TI_HPOS 0

#define DMA_SR_TPS_LPOS 1
#define DMA_SR_TPS_HPOS 1

#define DMA_SR_TBU_LPOS 2
#define DMA_SR_TBU_HPOS 2

#define DMA_SR_RI_LPOS 6
#define DMA_SR_RI_HPOS 6

#define DMA_SR_RBU_LPOS 7
#define DMA_SR_RBU_HPOS 7

#define DMA_SR_RPS_LPOS 8
#define DMA_SR_RPS_HPOS 8

#define DMA_SR_RWT_LPOS 9
#define DMA_SR_RWT_HPOS 9

#define DMA_SR_FBE_LPOS 12
#define DMA_SR_FBE_HPOS 12

#define DMA_ISR_DC0IS_LPOS 0
#define DMA_ISR_DC0IS_HPOS 0

#define DMA_ISR_MTLIS_LPOS 16
#define DMA_ISR_MTLIS_HPOS 16

#define DMA_ISR_MACIS_LPOS 17
#define DMA_ISR_MACIS_HPOS 17

#define DMA_DSR2_TPS7_LPOS 4
#define DMA_DSR2_TPS7_HPOS 7

#define DMA_DSR2_RPS7_LPOS 0
#define DMA_DSR2_RPS7_HPOS 3

#define DMA_DSR1_TPS6_LPOS 28
#define DMA_DSR1_TPS6_HPOS 31

#define DMA_DSR1_RPS6_LPOS 24
#define DMA_DSR1_RPS6_HPOS 27

#define DMA_DSR1_TPS5_LPOS 20
#define DMA_DSR1_TPS5_HPOS 23

#define DMA_DSR1_RPS5_LPOS 16
#define DMA_DSR1_RPS5_HPOS 19

#define DMA_DSR1_TPS4_LPOS 12
#define DMA_DSR1_TPS4_HPOS 15

#define DMA_DSR1_RPS4_LPOS 8
#define DMA_DSR1_RPS4_HPOS 11

#define DMA_DSR1_TPS3_LPOS 4
#define DMA_DSR1_TPS3_HPOS 7

#define DMA_DSR1_RPS3_LPOS 0
#define DMA_DSR1_RPS3_HPOS 3

#define DMA_DSR0_TPS2_LPOS 28
#define DMA_DSR0_TPS2_HPOS 31

#define DMA_DSR0_RPS2_LPOS 24
#define DMA_DSR0_RPS2_HPOS 27

#define DMA_DSR0_TPS1_LPOS 20
#define DMA_DSR0_TPS1_HPOS 23

#define DMA_DSR0_RPS1_LPOS 16
#define DMA_DSR0_RPS1_HPOS 19

#define DMA_DSR0_TPS0_LPOS 12
#define DMA_DSR0_TPS0_HPOS 15

#define DMA_DSR0_RPS0_LPOS 8
#define DMA_DSR0_RPS0_HPOS 11

#define MAC_VLANHTR_VLHT_LPOS 0
#define MAC_VLANHTR_VLHT_HPOS 15

#define DMA_BMR_SWR_LPOS 0
#define DMA_BMR_SWR_HPOS 0

#define MTL_Q0TOMR_FTQ_LPOS 0
#define MTL_Q0TOMR_FTQ_HPOS 0

#define MTL_QTOMR_FTQ_LPOS 0
#define MTL_QTOMR_FTQ_HPOS 0

#define MTL_OMR_DTXSTS_LPOS 1
#define MTL_OMR_DTXSTS_HPOS 1

#define MAC_MCR_IPC_LPOS 27
#define MAC_MCR_IPC_HPOS 27

#define MAC_ISR_PMTIS_LPOS 4
#define MAC_ISR_PMTIS_HPOS 4

#define MAC_ISR_PCSANCIS_LPOS 2
#define MAC_ISR_PCSANCIS_HPOS 2

#define MAC_ISR_PCSLCHGIS_LPOS 1
#define MAC_ISR_PCSLCHGIS_HPOS 1

#define MAC_ISR_RGSMIIS_LPOS 0
#define MAC_ISR_RGSMIIS_HPOS 0

#define MTL_QECR_ABPSSIE_LPOS 24
#define MTL_QECR_ABPSSIE_HPOS 24

#define MAC_ANS_LS_LPOS 2
#define MAC_ANS_LS_HPOS 2

#define MAC_ISR_LPI_LPOS 5
#define MAC_ISR_LPI_HPOS 5

#define GET_VALUE(data, lbit, hbit) ((data >> lbit) & (~(~0<<(hbit-lbit+1))))

#define GET_INDEXED_VALUE(data, lbit, hbit, index)\
	(GET_VALUE(data, (lbit+(index)*(hbit-lbit+1)), (hbit+(index)*(hbit-lbit+1))))
#endif
